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Using High Level Synthesis for Early Prototyping Eitan Ohayon, Eli Ben-Zino and Itai Yarom Israel Design Center, Intel

Semiconductor Trends PC market share (units) 45.2%  40% Consumer + cellphones (units) 32.4%  40.5% New king in town: consumer devices

Is it Consumer Electronic device or Computer?

The market react much faster 12 Years Years 3 Years 3 Weeks

What does it means for us? The ground rules are changing The market window is smaller The market pace is much faster Software is taking a major role It’s harder to verify each of the system’s component separately How can we address those challenges?

The Design Flow (Today) Separate design teams Separate development process Long dev. process Hard to inject changes hard to react to the market Project development 24 months 53% 34% 8% 5% Spec Detailed Spec RTL Unit Verification Chip Verification Silicon + SW Emulation + SW Dev

Desired Design Flow Synchronized design teams Synchronized development process Short dev. process Fast flow for injecting changes Easy to react to the market Silicon + SW Project development 12 months ?

Synchronized Environment Enable communication between the different teams using common model. Provides: Synchronized design teams Synchronized development process

The missing link Outcomes: Long development cycle Hard to inject changes (need to update 3 models) There isn’t automatic flow that connects the HLM to the rest of chip design flow

HLS Prospective Outcomes: Short development cycle Easy to inject changes

Driving the Change One step approach: We want to replace the RTL synthesis with a new flow: High Level Synthesis (HLS). Management respond: No way. Too risky. Two steps approach: Use HLS for Prototype (FPGA) Use HLS for Product (ASIC) Management respond: ROI looks good – go ahead with step 1.

1 st step: HLS for Prototyping We can use the HLM for the following: FPGA (Prototype) Power estimation Equivalence Checking Silicon + SW Project development 18 months Emulation + SW Dev RTL Coding MAS EAS UNIT Verification FC Verification

HLS to Prototype: DSP Testcases DSP testcases: Band Pass Filter (BPF) Single Section – IIR Results (BPF): Timing: x2 faster clock with HLS Gates count: 12% reduction with HLS Resources: HLS 2 Multipliers / RTL 12 BPF

HLS to Prototype: FSM Testcase FSM testcase: Control logic (with FSM) Results (with focus on latency) Timing: x2 faster clock with HLS Gates count: 5% addition with HLS Note: HLS is excellent tool for exploration of implementations alternatives

Implementations Alternatives Area Reduction Latency 1 st : Area Reduction 2 nd : Latency

HLS Pros & Cons Pros: Provides good results Connects to the rest of the flow Enables to explore architecture and implementations alternatives Reduces turn-around time for new feature significantly Cons: HLM needs to be ‘synthesis compatible’ New expertise are needed New mindset (new flow) The flow ramp-up is not trivial

2 nd Step: HLS for Design Gaining experience with HLS for FPGA, it’s much easier to go to HLS for Silicon HLS provides a fast lane from the HLM to the different views Emulation + SW Dev Silicon + SW Project development 12 months RTL Coding MAS EAS UNIT Verification FC Verification

Summary HLM enables synchronized development HLS provide the connection to between the HLM to the rest of the flow HLS tools are mature and provide good results We recommend on 2 steps approach for adopting HLS: Use HLS for Prototype Use HLS for Product

Using High Level Synthesis for Early Prototyping Eitan Ohayon, Eli Ben-Zino and Itai Yarom For more info: itai.yarom@intel.com

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