SlideShare a Scribd company logo
10
Most read
11
Most read
12
Most read
1
CMOS VLSI DESIGN
LAB BASED PROJECT REPORT
On
CMOS 3-Bit Binary to Square of the given Input
Submitted in partial fulfilment of the
Requirements for the award of degree
Bachelor of Technology
In
Electronics and Communication Engineering
Submitted
By
A. Sanath Kumar - 160040053
B. RameshReddy - 160040074
B. Purna - 160040124
Under the guidance of
G. RakeshChowdary
(Assistant Professor)
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
2017-2018
2
KONERU LAKSHMAIAH EDUCATIONAL FOUNDATION
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CERTIFICATE
This is to certify that the Lab based project entitled “CMOS 3-Bit Binary to
Square ofthe givenInput”, being submitted by “A. Sanathkumar– 160040074,B. Ramesh
Reddy - 160040074,B. Purna - 160040124 ” in partial fulfilment for the award of degree of
Bachelor of Technology (B. Tech) in Electronics and Communications Engineering is a
record ofconfidework carried out bythem under our guidance during the academic year 2017-
2018and it has been found worthy of acceptance according to the requirements of the
university.
Signature of the Project Guide Signature of Head of Department
Department of ECE
K L E F
3
KONERU LAKSHMAIAH EDUCATIONAL FOUNDATION
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
We declare that this Project based lab report entitled “CMOS 3-BitBinaryto Square
of the given Input” has been prepared by us in partial fulfilment of the requirement for the
award of degree “BACHELOR OF TECHNOLOGY IN ELECTRONICS AND
COMMUNICATIONS OF ENGINEERING” during the academic year 2017-2018.
We also declare that this Project based lab report is of our own effort and it has not
been submitted to any other university for the award of any degree.
DECLARATION
4
Acknowledgement
We are greatly indebted to our KL University that has provided a healthy environment
to drive us to achieve our ambitions and goals. We would like to express our sincere thanks to
our project Incharge Mr. G. Rakesh Chowdary (Assistant Professor) sir for the guidance,
support and assistance they have provided in completing this project.
With immense pleasure, we would like to thank the Head of the Department, Dr. V. S.
V. Prabhakarsir for his valuable suggestions and guidance for the timely completion of this
project.
We are very much glad for having the support given by our principal, K. Subba Rao
sir who inspired us with his words filled with dedication and discipline towards work.
We believe that “Practical Leads A Man Towards Performance”.
Last but not the least, our special thanks goes to the Parents, staff and classmates who
are helpful either directly or indirectly in completion of the Lab based project
5
CONTENTS Page. No
Abstract ------------------------------------------------------------------------------------------------------------ 6
1. Introduction------------------------------------------------------------------------- 7
2. Aim of The Project----------------------------------------------------------------- 7
3. Components Required------------------------------------------------------------- 7
4. Rules to design a CMOS Schematic--------------------------------------------- 8
5. Stick Diagram and it’s rules------------------------------------------------------ 8
6. Lambda based design rules for layout------------------------------------------- 8-9
7. About the Project------------------------------------------------------------------- 9
8. Truth Table and Circuit Diagram------------------------------------------------- 10
9. Schematic---------------------------------------------------------------------------- 11
10. Stick Diagram for the Schematic----------------------------------------------- 12
11. Layout for the Schematic-------------------------------------------------------- 12
12. Output Waveforms--------------------------------------------------------------- 12
13. Applications ---------------------------------------------------------------------- 13
14. Precautions------------------------------------------------------------------------ 13
15. Results and Observations-------------------------------------------------------- 13
16. Conclusion------------------------------------------------------------------------ 14
17. References------------------------------------------------------------------------- 15
6
Project Title: CMOS 3-Bit Binary to Square of the given Input
ABSTRACT
Area and power minimization are the prime concerns in recent VLSI design. As chip size is shrinking and
many other micro-electronics reliabilities are developing gradually, low power and small area design of any
system has become priority. The performance is an important element to determine the efficiency of the whole
circuit. In this Project, an area efficient layout design of has been proposed.
7
1. Introduction
CMOS Technology
The first working point contact transistor developed by John Bardeen, Walter Brattain and William
Shockley at Bell laboratories in 1947 initiated the rapid growth of the information technology industry. In
1958, J Kilby invented the first integrated circuit flip flop at Texas and soon after this; Frank Wan lass at
Fairchild described the first CMOS logic gate (NMOS and PMOS) in 1963.
One of the most popular MOSFET technologies available today is the Complementary MOS or CMOS
technology. CMOS technology is the dominant semiconductor technology for microprocessors, memories
and application specific integrated circuits (ASICs).
The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power
dissipation. Unlike NMOS or BIPOLAR circuits, a CMOS circuit has almost no static power dissipation.
Power is only dissipated in case the circuit actually switches. This allows to integrate many more CMOS gates
on an IC than in NMOS or bipolar technology, resulting in much better performance.
In CMOS logic gates a collection of n-type MOSFETs is arranged in a pulldown network between the
output and the lower voltage power supply rail ( Vss or quite often ground). Instead of the load resistor of
NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between
the output and the higher voltage rail (often named Vdd). Thus, if both a p-type and n-type transistor have
their gates connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is off, and
vice-versa. Area and power minimization are the prime concerns in recent VLSI design. As chip size is
shrinking and many other micro-electronics reliabilities are developing gradually, low power and small area
design of any system has become priority. The performance is an important element to determine the
efficiency of the whole circuit. In this project, an area efficient layout design of has been proposed.
2. AIM OF THE PROJECT:
1. The Main Aim of the Project is To Understand how to design a schematic circuit using complimentary logic
with respect to the inputs and outputs.
2. To learn how to design a schematic in DSH Software without errors.
3. To understand how to draw stick diagrams for a circuit and how to draw their layouts using Micro-Wind
Software.
3. COMPONENTS REQUIRED:
1. DSH Software
a) PMos and NMos c) Power Sources
8
b) Port In, Port out d) Connecting wires
2. Micro-Wind Software
4. Rules to design a CMOS Schematic
1. Before going to draw the CMOS logic circuits, we have to know the basic CMOS circuits for logic gates.
2. The given expression should contain whole bar.
3. No, two inputs have a common bar other than whole bar. But we can have bar for single input.
4. We should not remove any input during simplification of the Boolean expression.
Note: For NAND PMOS – Parallel; NMOS – Series
For NOR PMOS – Series; NMOS – Parallel
5. Stick Diagram and it’s Rules
VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing
topography and layer information using simple diagrams. Stick diagrams convey layer information through
colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout.
Does show all components. It shows relative placement of components. Goes one step closer to the
layout. Helps plan the layout and routing. A stick diagram is a cartoon of a layout.
Notations
Metal-1  Sky Blue
Metal-2  Thick Blue
Poly Silicon  Red
Contact Cut  Black Dot
N- Diff  Green
P- Diff  Yellow
Rules need to be followed
Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.
Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).
Rule 3. When a poly crosses diffusion it represents a transistor.
Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on
one side of the line and all nMOS will have to be on the other side.
6. Lambda based Rules to draw a Layout
9
7. About the Project
In these Project we are performing the operation of the square of the given 3-bit binary input. For these
we are using complementary gate logic. Here, first of all we write the truth table of the required operation.
10
After that we construct the K-maps for the outputs individually. After getting the required Boolean expressions
for each output, we have to draw the schematic for those expressions by following rules mentioned above. For
these Project we get the output “e” as zero. So, no need to apply k-map, we directly take It as zero. And for
output “f” we get the values same as input 3 that is Z. so we no need to get the expression for these also. We
can directly take these 2inputs.
After drawing the schematic, we have to check for the output. We are doing this by using DSH-
software. After the getting the exact output of the schematic in DSH, we have to draw the stick diagram for
the schematic by following proper rules and colours. Drawing the stick diagram doesn’t completes your
project. We have to do the layout for the schematic based on stick diagram in Micro-Wind. After the
completion compare the waveforms with the expected output. So that we can go for the extension of these
project.
8. Truth Table
Truth table
Circuit Diagram
11
9. Schematic of the Project
12
Output Waveforms in DSCH
10. Stick Diagram for the Schematic
13
11. Layout for the Schematic
12. Output Waveforms in Micro Wind
14
13. Applications
Used in Calculators, mobiles and some other electronic appliances.
14. Precautions
1. Connections should be made carefully
2. Make sure that VDD, GND are given.
3. At the time of stick diagram no same colours should be crossed if there is no connection at the point.
4. Layout should be done by checking DRC at step to step connection.
5. Observe the waveforms properly.
15. Results and Observations
1. From this experiment we are able to design the Schematic using CMOS logic.
2. Developed the experience of how to observe the output Waveforms by comparing with
truth table.
3. Learned to draw a stick diagram for complex circuits.
4. And also learned how to use DSH, Micro-wind softwares without getting errors.
15
16. Conclusion
Area and power minimization are the prime concerns in recent VLSI design. As chip size is shrinking
and many other micro-electronics reliabilities are developing gradually, low power and small area design of
any system has become priority. The performance is an important element to determine the efficiency of the
whole circuit. The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller
power dissipation. Unlike NMOS or BIPOLAR circuits, a CMOS circuit has almost no static power
dissipation. Power is only dissipated in case the circuit actually switches. This allows to integrate many more
CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.
16
17. References
1. https://www.elprocus.com/cmos-working-principle-and-applications/
2. https://www.slideshare.net/.../layout-stick-diagram-design-rules-60758496
3. https://www.canva.com/learn/design-rules/
4. www.egr.msu.edu/~mason/iucee/bog4/4-SNBhat_Stickdiagrams_IUCEEE.ppt
5. https://electronics.stackexchange.com/.../how-to-draw-stick-diagram-of-a-function

More Related Content

PPTX
Understanding-Artificial-Intelligence-in-Research (1).pptx
PPT
Layout design on MICROWIND
PDF
JavaScript Interview Questions with Answers
PPTX
Mos transistor theory
PPT
Karnaugh map
PPTX
Vlsi design flow
PPTX
integrator and differentiator op-amp
PPTX
Optimization Simulated Annealing
Understanding-Artificial-Intelligence-in-Research (1).pptx
Layout design on MICROWIND
JavaScript Interview Questions with Answers
Mos transistor theory
Karnaugh map
Vlsi design flow
integrator and differentiator op-amp
Optimization Simulated Annealing

What's hot (20)

PPT
Pass Transistor Logic
PPTX
Study of vlsi design methodologies and limitations using cad tools for cmos t...
PPT
Switch level modeling
PPTX
Pass Transistor Logic
PPTX
Sequential cmos logic circuits
PPSX
CPLD xc9500
PPTX
VLSI Design Methodologies
PPTX
PPTX
Pic16cxx instruction set
DOC
Industrial training report of vlsi,vhdl and pcb designing
PDF
Logic synthesis using Verilog HDL
PDF
Monte Carlo simulation (Mismatch and Process) in Cadence
PPTX
Reliability and yield
PDF
Microcontroller pic 16f877 architecture and basics
PPTX
Comparison between the FPGA vs CPLD
PPTX
PDF
Automatic Test Pattern Generation (Testing of VLSI Design)
DOCX
Lambda design rule
PPTX
8051 Microcontroller ppt
Pass Transistor Logic
Study of vlsi design methodologies and limitations using cad tools for cmos t...
Switch level modeling
Pass Transistor Logic
Sequential cmos logic circuits
CPLD xc9500
VLSI Design Methodologies
Pic16cxx instruction set
Industrial training report of vlsi,vhdl and pcb designing
Logic synthesis using Verilog HDL
Monte Carlo simulation (Mismatch and Process) in Cadence
Reliability and yield
Microcontroller pic 16f877 architecture and basics
Comparison between the FPGA vs CPLD
Automatic Test Pattern Generation (Testing of VLSI Design)
Lambda design rule
8051 Microcontroller ppt
Ad

Similar to CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIPLIER (20)

PDF
Vlsi Summer training report pdf
PDF
Cmos uma
PDF
Cmos uma
DOCX
VLSI NOTES.docx notes for vlsi ece deptmnt
DOC
Communication Design Engineer
PPTX
Vlsi td introduction
PDF
VLSID_2023 Unit V FPGA Design switches programming
PDF
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach
PDF
Samtec whitepaper
PDF
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
PPT
Performance Analysis of Encoder in Different Logic Techniques for High-Speed ...
PPTX
Stick Diagrams design and lamda dia.pptx
PDF
Ijetr011811
PPT
Analog vlsi
PDF
Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
DOCX
Full IC Flow.docx
PDF
VLSI-Desig
PDF
CMOS_Basics_PPT.pdf
Vlsi Summer training report pdf
Cmos uma
Cmos uma
VLSI NOTES.docx notes for vlsi ece deptmnt
Communication Design Engineer
Vlsi td introduction
VLSID_2023 Unit V FPGA Design switches programming
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach
Samtec whitepaper
IC Layout Design of 4-bit Magnitude Comparator using Electric VLSI Design System
Performance Analysis of Encoder in Different Logic Techniques for High-Speed ...
Stick Diagrams design and lamda dia.pptx
Ijetr011811
Analog vlsi
Design of Low Power Energy Efficient Carry Select Adder Using CMOS Technology
Full IC Flow.docx
VLSI-Desig
CMOS_Basics_PPT.pdf
Ad

Recently uploaded (20)

PDF
Black Hat USA 2025 - Micro ICS Summit - ICS/OT Threat Landscape
PDF
Microbial disease of the cardiovascular and lymphatic systems
PDF
3rd Neelam Sanjeevareddy Memorial Lecture.pdf
PDF
STATICS OF THE RIGID BODIES Hibbelers.pdf
PDF
TR - Agricultural Crops Production NC III.pdf
PPTX
Pharmacology of Heart Failure /Pharmacotherapy of CHF
PDF
Basic Mud Logging Guide for educational purpose
PPTX
Final Presentation General Medicine 03-08-2024.pptx
PDF
01-Introduction-to-Information-Management.pdf
PPTX
master seminar digital applications in india
PDF
O7-L3 Supply Chain Operations - ICLT Program
PPTX
Introduction_to_Human_Anatomy_and_Physiology_for_B.Pharm.pptx
PDF
Module 4: Burden of Disease Tutorial Slides S2 2025
PPTX
BOWEL ELIMINATION FACTORS AFFECTING AND TYPES
PPTX
Lesson notes of climatology university.
PPTX
PPH.pptx obstetrics and gynecology in nursing
PPTX
Cell Structure & Organelles in detailed.
PPTX
PPT- ENG7_QUARTER1_LESSON1_WEEK1. IMAGERY -DESCRIPTIONS pptx.pptx
PDF
ANTIBIOTICS.pptx.pdf………………… xxxxxxxxxxxxx
PDF
Abdominal Access Techniques with Prof. Dr. R K Mishra
Black Hat USA 2025 - Micro ICS Summit - ICS/OT Threat Landscape
Microbial disease of the cardiovascular and lymphatic systems
3rd Neelam Sanjeevareddy Memorial Lecture.pdf
STATICS OF THE RIGID BODIES Hibbelers.pdf
TR - Agricultural Crops Production NC III.pdf
Pharmacology of Heart Failure /Pharmacotherapy of CHF
Basic Mud Logging Guide for educational purpose
Final Presentation General Medicine 03-08-2024.pptx
01-Introduction-to-Information-Management.pdf
master seminar digital applications in india
O7-L3 Supply Chain Operations - ICLT Program
Introduction_to_Human_Anatomy_and_Physiology_for_B.Pharm.pptx
Module 4: Burden of Disease Tutorial Slides S2 2025
BOWEL ELIMINATION FACTORS AFFECTING AND TYPES
Lesson notes of climatology university.
PPH.pptx obstetrics and gynecology in nursing
Cell Structure & Organelles in detailed.
PPT- ENG7_QUARTER1_LESSON1_WEEK1. IMAGERY -DESCRIPTIONS pptx.pptx
ANTIBIOTICS.pptx.pdf………………… xxxxxxxxxxxxx
Abdominal Access Techniques with Prof. Dr. R K Mishra

CMOS VLSI PROJECT || CMOS 3-Bit Binary to Square of the given Input || MULTIPLIER

  • 1. 1 CMOS VLSI DESIGN LAB BASED PROJECT REPORT On CMOS 3-Bit Binary to Square of the given Input Submitted in partial fulfilment of the Requirements for the award of degree Bachelor of Technology In Electronics and Communication Engineering Submitted By A. Sanath Kumar - 160040053 B. RameshReddy - 160040074 B. Purna - 160040124 Under the guidance of G. RakeshChowdary (Assistant Professor) DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING 2017-2018
  • 2. 2 KONERU LAKSHMAIAH EDUCATIONAL FOUNDATION DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING CERTIFICATE This is to certify that the Lab based project entitled “CMOS 3-Bit Binary to Square ofthe givenInput”, being submitted by “A. Sanathkumar– 160040074,B. Ramesh Reddy - 160040074,B. Purna - 160040124 ” in partial fulfilment for the award of degree of Bachelor of Technology (B. Tech) in Electronics and Communications Engineering is a record ofconfidework carried out bythem under our guidance during the academic year 2017- 2018and it has been found worthy of acceptance according to the requirements of the university. Signature of the Project Guide Signature of Head of Department Department of ECE K L E F
  • 3. 3 KONERU LAKSHMAIAH EDUCATIONAL FOUNDATION DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING We declare that this Project based lab report entitled “CMOS 3-BitBinaryto Square of the given Input” has been prepared by us in partial fulfilment of the requirement for the award of degree “BACHELOR OF TECHNOLOGY IN ELECTRONICS AND COMMUNICATIONS OF ENGINEERING” during the academic year 2017-2018. We also declare that this Project based lab report is of our own effort and it has not been submitted to any other university for the award of any degree. DECLARATION
  • 4. 4 Acknowledgement We are greatly indebted to our KL University that has provided a healthy environment to drive us to achieve our ambitions and goals. We would like to express our sincere thanks to our project Incharge Mr. G. Rakesh Chowdary (Assistant Professor) sir for the guidance, support and assistance they have provided in completing this project. With immense pleasure, we would like to thank the Head of the Department, Dr. V. S. V. Prabhakarsir for his valuable suggestions and guidance for the timely completion of this project. We are very much glad for having the support given by our principal, K. Subba Rao sir who inspired us with his words filled with dedication and discipline towards work. We believe that “Practical Leads A Man Towards Performance”. Last but not the least, our special thanks goes to the Parents, staff and classmates who are helpful either directly or indirectly in completion of the Lab based project
  • 5. 5 CONTENTS Page. No Abstract ------------------------------------------------------------------------------------------------------------ 6 1. Introduction------------------------------------------------------------------------- 7 2. Aim of The Project----------------------------------------------------------------- 7 3. Components Required------------------------------------------------------------- 7 4. Rules to design a CMOS Schematic--------------------------------------------- 8 5. Stick Diagram and it’s rules------------------------------------------------------ 8 6. Lambda based design rules for layout------------------------------------------- 8-9 7. About the Project------------------------------------------------------------------- 9 8. Truth Table and Circuit Diagram------------------------------------------------- 10 9. Schematic---------------------------------------------------------------------------- 11 10. Stick Diagram for the Schematic----------------------------------------------- 12 11. Layout for the Schematic-------------------------------------------------------- 12 12. Output Waveforms--------------------------------------------------------------- 12 13. Applications ---------------------------------------------------------------------- 13 14. Precautions------------------------------------------------------------------------ 13 15. Results and Observations-------------------------------------------------------- 13 16. Conclusion------------------------------------------------------------------------ 14 17. References------------------------------------------------------------------------- 15
  • 6. 6 Project Title: CMOS 3-Bit Binary to Square of the given Input ABSTRACT Area and power minimization are the prime concerns in recent VLSI design. As chip size is shrinking and many other micro-electronics reliabilities are developing gradually, low power and small area design of any system has become priority. The performance is an important element to determine the efficiency of the whole circuit. In this Project, an area efficient layout design of has been proposed.
  • 7. 7 1. Introduction CMOS Technology The first working point contact transistor developed by John Bardeen, Walter Brattain and William Shockley at Bell laboratories in 1947 initiated the rapid growth of the information technology industry. In 1958, J Kilby invented the first integrated circuit flip flop at Texas and soon after this; Frank Wan lass at Fairchild described the first CMOS logic gate (NMOS and PMOS) in 1963. One of the most popular MOSFET technologies available today is the Complementary MOS or CMOS technology. CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows to integrate many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance. In CMOS logic gates a collection of n-type MOSFETs is arranged in a pulldown network between the output and the lower voltage power supply rail ( Vss or quite often ground). Instead of the load resistor of NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up network between the output and the higher voltage rail (often named Vdd). Thus, if both a p-type and n-type transistor have their gates connected to the same input, the p-type MOSFET will be on when the n-type MOSFET is off, and vice-versa. Area and power minimization are the prime concerns in recent VLSI design. As chip size is shrinking and many other micro-electronics reliabilities are developing gradually, low power and small area design of any system has become priority. The performance is an important element to determine the efficiency of the whole circuit. In this project, an area efficient layout design of has been proposed. 2. AIM OF THE PROJECT: 1. The Main Aim of the Project is To Understand how to design a schematic circuit using complimentary logic with respect to the inputs and outputs. 2. To learn how to design a schematic in DSH Software without errors. 3. To understand how to draw stick diagrams for a circuit and how to draw their layouts using Micro-Wind Software. 3. COMPONENTS REQUIRED: 1. DSH Software a) PMos and NMos c) Power Sources
  • 8. 8 b) Port In, Port out d) Connecting wires 2. Micro-Wind Software 4. Rules to design a CMOS Schematic 1. Before going to draw the CMOS logic circuits, we have to know the basic CMOS circuits for logic gates. 2. The given expression should contain whole bar. 3. No, two inputs have a common bar other than whole bar. But we can have bar for single input. 4. We should not remove any input during simplification of the Boolean expression. Note: For NAND PMOS – Parallel; NMOS – Series For NOR PMOS – Series; NMOS – Parallel 5. Stick Diagram and it’s Rules VLSI design aims to translate circuit concepts onto silicon. stick diagrams are a means of capturing topography and layer information using simple diagrams. Stick diagrams convey layer information through colour codes (or monochrome encoding). Acts as an interface between symbolic circuit and the actual layout. Does show all components. It shows relative placement of components. Goes one step closer to the layout. Helps plan the layout and routing. A stick diagram is a cartoon of a layout. Notations Metal-1  Sky Blue Metal-2  Thick Blue Poly Silicon  Red Contact Cut  Black Dot N- Diff  Green P- Diff  Yellow Rules need to be followed Rule 1. When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact. Rule 2. When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly). Rule 3. When a poly crosses diffusion it represents a transistor. Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side. 6. Lambda based Rules to draw a Layout
  • 9. 9 7. About the Project In these Project we are performing the operation of the square of the given 3-bit binary input. For these we are using complementary gate logic. Here, first of all we write the truth table of the required operation.
  • 10. 10 After that we construct the K-maps for the outputs individually. After getting the required Boolean expressions for each output, we have to draw the schematic for those expressions by following rules mentioned above. For these Project we get the output “e” as zero. So, no need to apply k-map, we directly take It as zero. And for output “f” we get the values same as input 3 that is Z. so we no need to get the expression for these also. We can directly take these 2inputs. After drawing the schematic, we have to check for the output. We are doing this by using DSH- software. After the getting the exact output of the schematic in DSH, we have to draw the stick diagram for the schematic by following proper rules and colours. Drawing the stick diagram doesn’t completes your project. We have to do the layout for the schematic based on stick diagram in Micro-Wind. After the completion compare the waveforms with the expected output. So that we can go for the extension of these project. 8. Truth Table Truth table Circuit Diagram
  • 11. 11 9. Schematic of the Project
  • 12. 12 Output Waveforms in DSCH 10. Stick Diagram for the Schematic
  • 13. 13 11. Layout for the Schematic 12. Output Waveforms in Micro Wind
  • 14. 14 13. Applications Used in Calculators, mobiles and some other electronic appliances. 14. Precautions 1. Connections should be made carefully 2. Make sure that VDD, GND are given. 3. At the time of stick diagram no same colours should be crossed if there is no connection at the point. 4. Layout should be done by checking DRC at step to step connection. 5. Observe the waveforms properly. 15. Results and Observations 1. From this experiment we are able to design the Schematic using CMOS logic. 2. Developed the experience of how to observe the output Waveforms by comparing with truth table. 3. Learned to draw a stick diagram for complex circuits. 4. And also learned how to use DSH, Micro-wind softwares without getting errors.
  • 15. 15 16. Conclusion Area and power minimization are the prime concerns in recent VLSI design. As chip size is shrinking and many other micro-electronics reliabilities are developing gradually, low power and small area design of any system has become priority. The performance is an important element to determine the efficiency of the whole circuit. The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows to integrate many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.
  • 16. 16 17. References 1. https://www.elprocus.com/cmos-working-principle-and-applications/ 2. https://www.slideshare.net/.../layout-stick-diagram-design-rules-60758496 3. https://www.canva.com/learn/design-rules/ 4. www.egr.msu.edu/~mason/iucee/bog4/4-SNBhat_Stickdiagrams_IUCEEE.ppt 5. https://electronics.stackexchange.com/.../how-to-draw-stick-diagram-of-a-function