07 sequential verilog
0 likes1,141 views
This document describes several Verilog modules: 1) An 8-bit register with synchronous reset that uses a clock signal to load data or reset the register to 0. 2) An N-bit register with asynchronous reset that can asynchronously reset or synchronously load data. 3) A shift register example that can clear, load, or shift data left on each clock cycle based on control signals.
![More Verilog 8-bit Register with Synchronous Reset
module reg8 (reset, CLK, D, Q);
input reset;
input CLK;
input [7:0] D;
output [7:0] Q;
reg [7:0] Q;
always @(posedge CLK)
if (reset)
Q = 0;
else
Q = D;
endmodule // reg8
Verilog - 1 Verilog - 2
N-bit Register with Asynchronous Reset Shift Register Example
// 8-bit register can be cleared, loaded, shifted left
module regN (reset, CLK, D, Q); // Retains value if no control signal is asserted
input reset;
input CLK; module shiftReg (CLK, clr, shift, ld, Din, SI, Dout);
input CLK;
parameter N = 8; // Allow N to be changed
input clr; // clear register
input [N-1:0] D;
input shift; // shift
output [N-1:0] Q; input ld; // load register from Din
reg [N-1:0] Q; input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
always @(posedge CLK or posedge reset) output [7:0] Dout;
if (reset) reg [7:0] Dout;
Q = 0;
else if (CLK == 1) always @(posedge CLK) begin
if (clr) Dout <= 0;
Q = D;
else if (ld) Dout <= Din;
else if (shift) Dout <= { Dout[6:0], SI };
endmodule // regN end
endmodule // shiftReg
Verilog - 3 Verilog - 4
Blocking and Non-Blocking Assignments Swap (continued)
Q = A % %
! " %
# $ Q <= A
always @(posedge CLK) always @(posedge CLK)
begin begin
A = B; B = A;
% end end
&
! (
posedge CLK
' % & ! %
always @(posedge CLK) always @(posedge CLK)
always @(posedge CLK) begin begin
always @(posedge CLK) A <= B; B <= A;
begin begin
temp = B; end end
A <= B;
B = A; B <= A;
A = temp; end
end
Verilog - 5 Verilog - 6](https://image.slidesharecdn.com/07-sequentialverilog-121004013237-phpapp02/85/07-sequential-verilog-1-320.jpg)
![Non-Blocking Assignment Counter Example
# $ ! )
! % % ! %
$ $ * %$ % 0 1 22
& + ), + - ./ " %
// this implements 3 parallel flip-flops
always @(posedge clk) // 8-bit counter with clear and count enable controls
begin module count8 (CLK, clr, cntEn, Dout);
B = A; // this implements a shift register input CLK;
C = B; always @(posedge clk)
D = C; input clr; // clear counter
begin
end {D, C, B} = {C, B, A};
input cntEn; // enable count
end output [7:0] Dout; // counter value
// this implements a shift register
reg [7:0] Dout;
always @(posedge clk)
begin always @(posedge CLK)
B <= A; if (clr) Dout <= 0;
C <= B; else if (cntEn) Dout <= Dout + 1;
D <= C;
end endmodule
Verilog - 7 Verilog - 8
Finite State Machines Verilog FSM - Reduce 1s example
4 5 46
Mealy outputs ' % %
next state Moore outputs
inputs
combinational // State assignment
logic parameter zero = 0, one1 = 1, two1s = 2;
current state module reduce (clk, reset, in, out);
input clk, reset, in;
output out;
reg out;
reg [1:0] state; // state register
reg [1:0] next_state;
% // Implement the state register
always @(posedge clk)
3 % ! if (reset) state = zero;
3 % % ! else state = next_state;
Verilog - 9 Verilog - 10
Moore Verilog FSM (cont’d) Mealy Verilog FSM for Reduce-1s example
always @(in or state) module reduce (clk, reset, in, out);
case (state) input clk, reset, in;
out = 0; // defaults output out;
next_state = zero; reg out;
zero: begin // last input was a zero reg state; // state register
if (in) next_state = one1; reg next_state;
end parameter zero = 0, one = 1;
always @(posedge clk)
one1: begin // we've seen one 1 if (reset) state = zero;
if (in) next_state = two1s; else state = next_state;
end
always @(in or state)
two1s: begin // we've seen at least 2 ones out = 0;
out = 1; next_state = zero;
if (in) next_state = two1s; case (state)
end zero: begin // last input was a zero
// Don’t need case default because of default assignments if (in) next_state = one;
endcase end
endmodule one: // we've seen one 1
if (in) begin
next_state = one; out = 1;
end
endcase
endmodule
Verilog - 11 Verilog - 12
6](https://image.slidesharecdn.com/07-sequentialverilog-121004013237-phpapp02/85/07-sequential-verilog-2-320.jpg)
![Single-always Moore Machine
Restricted FSM Implementation Style (Not Recommended!)
" ! !
% )7 module reduce (clk, reset, in, out);
% % input clk, reset, in;
output out;
! ! reg out;
reg [1:0] state; // state register
22 % parameter zero = 0, one1 = 1, two1s = 2;
%
%
! 1
Verilog - 13 Verilog - 14
Single-always Moore Machine
(Not Recommended!) Delays
always @(posedge clk)
case (state)
All outputs are registered
zero: begin
out = 0;
if (in) state = one1;
else state = zero;
end
one1: 3 1 0 !
if (in) begin
state = two1s; % !
out = 1;
end else begin This is confusing: the 8 45 45
state = zero;
out = 0; output does not change
end until the next clock cycle module and_gate (out, in1, in2);
two1s:
if (in) begin input in1, in2;
state = two1s;
out = 1; output out;
end else begin
state = zero;
end
out = 0; assign #10 out = in1 & in2;
default: begin
state = zero;
out = 0; endmodule
end
endcase
endmodule
Verilog - 15 Verilog - 16
6
Verilog Propagation Delay Initial Blocks
! ) !
assign #5 c = a | b; 0
assign #4 {Cout, S} = Cin + A + B;
always @(A or B or Cin)
#4 S = A + B + Cin;
#2 Cout = (A & B) | (B & Cin) | (A & Cin);
assign #3 zero = (sum == 0) ? 1 : 0;
always @(sum)
if (sum == 0)
#6 zero = 1;
else
#3 zero = 0;
Verilog - 17 Verilog - 18](https://image.slidesharecdn.com/07-sequentialverilog-121004013237-phpapp02/85/07-sequential-verilog-3-320.jpg)
![Tri-State Buffers Test Fixtures
<
9: 6 $
< =
% % $ ;
% %
module tstate (EnA, EnB, BusA, BusB, BusOut);
input EnA, EnB; % %
input [7:0] BusA, BusB;
output [7:0] BusOut; 1 1 =! 1 2
assign BusOut = EnA ? BusA : 8’bZ; Simulation
assign BusOut = EnB ? BusB : 8’bZ;
endmodule
Test Fixture Circuit Description
(Specification) (Synthesizeable)
Verilog - 19 Verilog - 20
Verilog Clocks Verilog Clocks
> +
module clockGenerator (CLK);
parameter period = 10; module clock_gen (masterclk); ! "
parameter howlong = 100; "
output CLK;
reg CLK; `define PERIOD = 10;
initial begin output masterclk;
CLK = 0; reg masterclk;
#(period/2);
repeat (howlong) begin
CLK = 1; initial masterclk = 0;
#(period-period/2);
CLK = 0; always begin " #
#(period/2);
end
#`PERIOD/2
$finish; masterclk = ~masterclk;
end end
endmodule // clockGenerator
endmodule
Verilog - 21 Verilog - 22
Example Test Fixture Simulation Driver
module stimulus (a, b, c);
module stimulus (a, b);
parameter delay = 10; module full_addr1 (A, B, Cin, S, Cout);
input A, B, Cin;
parameter delay = 10;
output a, b, c;
reg [2:0] cnt; output S, Cout; output a, b; $%
initial begin assign {Cout, S} = A + B + Cin; reg [1:0] cnt;
cnt = 0; endmodule
repeat (8) begin
#delay cnt=cnt+1; initial begin &
end
#delay $finish; cnt = 0; # "
end
repeat (4) begin
assign {c, a, b} = cnt;
endmodule
#delay cnt = cnt + 1;
end
module driver; // Structural Verilog connects test-fixture to full adder
wire a, b, cin, sum, cout; #delay $finish;
stimulus stim (a, b, cin);
full_addr1 fa1 (a, b, cin, sum, cout); end
initial begin
$monitor ("@ time=%0d cin=%b, a=%b, b=%b, cout=%d, sum=%d", assign {a, b} = cnt;
$time, cin, a, b, cout, sum);
end endmodule
endmodule
Verilog - 23 Verilog - 24](https://image.slidesharecdn.com/07-sequentialverilog-121004013237-phpapp02/85/07-sequential-verilog-4-320.jpg)
![Test Vectors Verilog Simulation
module testData(clk, reset, data);
3 % 2 %
input clk; %
output reset, data;
reg [1:0] testVector [100:0]; )
reg reset, data;
integer count;
initial begin %
$readmemb("data.b", testVector);
count = 0; 0 ?
{ reset, data } = testVector[0];
end
always @(posedge clk) begin
count = count + 1;
#1 { reset, data } = testVector[count];
end
endmodule
Verilog - 25 Verilog - 26
Intepreted vs. Compiled Simulation Simulation Level
3 % '
% "
! ! % % !
&
" 1 ! $
1% ! " 1 %
%
>
% % = !
! $
&
% ! ! % $
% " 1
% 0 % % %
*
% @ %
Verilog - 27 Verilog - 28
Simulation Time and Event Queues Verilog Time
' " + % %% 0 %
A A% " !
" % % 8 $ %
% " % % " ! %
% " B ! $! 1 22B %
1 ! //5
%% "
! " , " 1
% %
=!
% %
! ! ! 0 ? %
% !
% C
% %
Verilog - 29 Verilog - 30](https://image.slidesharecdn.com/07-sequentialverilog-121004013237-phpapp02/85/07-sequential-verilog-5-320.jpg)
07 sequential verilog
- 1. More Verilog 8-bit Register with Synchronous Reset module reg8 (reset, CLK, D, Q); input reset; input CLK; input [7:0] D; output [7:0] Q; reg [7:0] Q; always @(posedge CLK) if (reset) Q = 0; else Q = D; endmodule // reg8 Verilog - 1 Verilog - 2 N-bit Register with Asynchronous Reset Shift Register Example // 8-bit register can be cleared, loaded, shifted left module regN (reset, CLK, D, Q); // Retains value if no control signal is asserted input reset; input CLK; module shiftReg (CLK, clr, shift, ld, Din, SI, Dout); input CLK; parameter N = 8; // Allow N to be changed input clr; // clear register input [N-1:0] D; input shift; // shift output [N-1:0] Q; input ld; // load register from Din reg [N-1:0] Q; input [7:0] Din; // Data input for load input SI; // Input bit to shift in always @(posedge CLK or posedge reset) output [7:0] Dout; if (reset) reg [7:0] Dout; Q = 0; else if (CLK == 1) always @(posedge CLK) begin if (clr) Dout <= 0; Q = D; else if (ld) Dout <= Din; else if (shift) Dout <= { Dout[6:0], SI }; endmodule // regN end endmodule // shiftReg Verilog - 3 Verilog - 4 Blocking and Non-Blocking Assignments Swap (continued) Q = A % % ! " % # $ Q <= A always @(posedge CLK) always @(posedge CLK) begin begin A = B; B = A; % end end & ! ( posedge CLK ' % & ! % always @(posedge CLK) always @(posedge CLK) always @(posedge CLK) begin begin always @(posedge CLK) A <= B; B <= A; begin begin temp = B; end end A <= B; B = A; B <= A; A = temp; end end Verilog - 5 Verilog - 6
- 2. Non-Blocking Assignment Counter Example # $ ! ) ! % % ! % $ $ * %$ % 0 1 22 & + ), + - ./ " % // this implements 3 parallel flip-flops always @(posedge clk) // 8-bit counter with clear and count enable controls begin module count8 (CLK, clr, cntEn, Dout); B = A; // this implements a shift register input CLK; C = B; always @(posedge clk) D = C; input clr; // clear counter begin end {D, C, B} = {C, B, A}; input cntEn; // enable count end output [7:0] Dout; // counter value // this implements a shift register reg [7:0] Dout; always @(posedge clk) begin always @(posedge CLK) B <= A; if (clr) Dout <= 0; C <= B; else if (cntEn) Dout <= Dout + 1; D <= C; end endmodule Verilog - 7 Verilog - 8 Finite State Machines Verilog FSM - Reduce 1s example 4 5 46 Mealy outputs ' % % next state Moore outputs inputs combinational // State assignment logic parameter zero = 0, one1 = 1, two1s = 2; current state module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg [1:0] state; // state register reg [1:0] next_state; % // Implement the state register always @(posedge clk) 3 % ! if (reset) state = zero; 3 % % ! else state = next_state; Verilog - 9 Verilog - 10 Moore Verilog FSM (cont’d) Mealy Verilog FSM for Reduce-1s example always @(in or state) module reduce (clk, reset, in, out); case (state) input clk, reset, in; out = 0; // defaults output out; next_state = zero; reg out; zero: begin // last input was a zero reg state; // state register if (in) next_state = one1; reg next_state; end parameter zero = 0, one = 1; always @(posedge clk) one1: begin // we've seen one 1 if (reset) state = zero; if (in) next_state = two1s; else state = next_state; end always @(in or state) two1s: begin // we've seen at least 2 ones out = 0; out = 1; next_state = zero; if (in) next_state = two1s; case (state) end zero: begin // last input was a zero // Don’t need case default because of default assignments if (in) next_state = one; endcase end endmodule one: // we've seen one 1 if (in) begin next_state = one; out = 1; end endcase endmodule Verilog - 11 Verilog - 12 6
- 3. Single-always Moore Machine Restricted FSM Implementation Style (Not Recommended!) " ! ! % )7 module reduce (clk, reset, in, out); % % input clk, reset, in; output out; ! ! reg out; reg [1:0] state; // state register 22 % parameter zero = 0, one1 = 1, two1s = 2; % % ! 1 Verilog - 13 Verilog - 14 Single-always Moore Machine (Not Recommended!) Delays always @(posedge clk) case (state) All outputs are registered zero: begin out = 0; if (in) state = one1; else state = zero; end one1: 3 1 0 ! if (in) begin state = two1s; % ! out = 1; end else begin This is confusing: the 8 45 45 state = zero; out = 0; output does not change end until the next clock cycle module and_gate (out, in1, in2); two1s: if (in) begin input in1, in2; state = two1s; out = 1; output out; end else begin state = zero; end out = 0; assign #10 out = in1 & in2; default: begin state = zero; out = 0; endmodule end endcase endmodule Verilog - 15 Verilog - 16 6 Verilog Propagation Delay Initial Blocks ! ) ! assign #5 c = a | b; 0 assign #4 {Cout, S} = Cin + A + B; always @(A or B or Cin) #4 S = A + B + Cin; #2 Cout = (A & B) | (B & Cin) | (A & Cin); assign #3 zero = (sum == 0) ? 1 : 0; always @(sum) if (sum == 0) #6 zero = 1; else #3 zero = 0; Verilog - 17 Verilog - 18
- 4. Tri-State Buffers Test Fixtures < 9: 6 $ < = % % $ ; % % module tstate (EnA, EnB, BusA, BusB, BusOut); input EnA, EnB; % % input [7:0] BusA, BusB; output [7:0] BusOut; 1 1 =! 1 2 assign BusOut = EnA ? BusA : 8’bZ; Simulation assign BusOut = EnB ? BusB : 8’bZ; endmodule Test Fixture Circuit Description (Specification) (Synthesizeable) Verilog - 19 Verilog - 20 Verilog Clocks Verilog Clocks > + module clockGenerator (CLK); parameter period = 10; module clock_gen (masterclk); ! " parameter howlong = 100; " output CLK; reg CLK; `define PERIOD = 10; initial begin output masterclk; CLK = 0; reg masterclk; #(period/2); repeat (howlong) begin CLK = 1; initial masterclk = 0; #(period-period/2); CLK = 0; always begin " # #(period/2); end #`PERIOD/2 $finish; masterclk = ~masterclk; end end endmodule // clockGenerator endmodule Verilog - 21 Verilog - 22 Example Test Fixture Simulation Driver module stimulus (a, b, c); module stimulus (a, b); parameter delay = 10; module full_addr1 (A, B, Cin, S, Cout); input A, B, Cin; parameter delay = 10; output a, b, c; reg [2:0] cnt; output S, Cout; output a, b; $% initial begin assign {Cout, S} = A + B + Cin; reg [1:0] cnt; cnt = 0; endmodule repeat (8) begin #delay cnt=cnt+1; initial begin & end #delay $finish; cnt = 0; # " end repeat (4) begin assign {c, a, b} = cnt; endmodule #delay cnt = cnt + 1; end module driver; // Structural Verilog connects test-fixture to full adder wire a, b, cin, sum, cout; #delay $finish; stimulus stim (a, b, cin); full_addr1 fa1 (a, b, cin, sum, cout); end initial begin $monitor ("@ time=%0d cin=%b, a=%b, b=%b, cout=%d, sum=%d", assign {a, b} = cnt; $time, cin, a, b, cout, sum); end endmodule endmodule Verilog - 23 Verilog - 24
- 5. Test Vectors Verilog Simulation module testData(clk, reset, data); 3 % 2 % input clk; % output reset, data; reg [1:0] testVector [100:0]; ) reg reset, data; integer count; initial begin % $readmemb("data.b", testVector); count = 0; 0 ? { reset, data } = testVector[0]; end always @(posedge clk) begin count = count + 1; #1 { reset, data } = testVector[count]; end endmodule Verilog - 25 Verilog - 26 Intepreted vs. Compiled Simulation Simulation Level 3 % ' % " ! ! % % ! & " 1 ! $ 1% ! " 1 % % > % % = ! ! $ & % ! ! % $ % " 1 % 0 % % % * % @ % Verilog - 27 Verilog - 28 Simulation Time and Event Queues Verilog Time ' " + % %% 0 % A A% " ! " % % 8 $ % % " % % " ! % % " B ! $! 1 22B % 1 ! //5 %% " ! " , " 1 % % =! % % ! ! ! 0 ? % % ! % C % % Verilog - 29 Verilog - 30
- 6. Inertial and Transport Delays A few requirements for CSE467... 3 ! $ ! 8DE /+ F + ! % , D 1 + E G E ! ! + % ; $ E ./ 8 D + F % 8 % + E1 D ) 1 $ % ; % % 6 ) % 0 Verilog - 31 Verilog - 32