22). smlevel energy eff-dynamictaskschedng

System-Level Energy-Efficient Dynamic Task Scheduling∗

Jianli Zhuo Chaitali Chakrabarti
Department of Electrical Engineering Department of Electrical Engineering
Arizona State University, Tempe, AZ, 85287 Arizona State University, Tempe, AZ, 85287
jianli.zhuo@asu.edu chaitali@asu.edu

ABSTRACT voltage / frequency. It achieves significant dynamic power sav-
Dynamic voltage scaling (DVS) is a well-known low power design ing due to the quadratic relationship between voltage and dynamic
technique that reduces the processor energy by slowing down the power.
DVS processor and stretching the task execution time. But in a In recent years, there has been significant amount of work done
DVS system consisting of a DVS processor and multiple devices, in energy-efficient task scheduling for DVS processors. The work
slowing down the processor increases the device energy consump- can be classified into static scheduling algorithms [2, 3, 4] based
tion and thereby the system-level energy consumption. In this pa- on apriori task information, two-phase algorithms [5, 6, 7, 8] that
per, we present dynamic task scheduling algorithms for periodic operate in two phases: an off-line phase (based on W CET or other
tasks that minimize the system-level energy (CPU energy + device execution time estimates) followed by an online phase where the
standby energy). The algorithms use a combination of (i) optimal slack is greedily absorbed, and pure dynamic algorithms [2, 9, 10]
speed setting, which is the speed that minimizes the system en- that only operate in the online phase. Most of these techniques
ergy for a specific task, and (ii) limited preemption which reduces absorb the system slack greedily to reduce the processor operating
the numbers of possible preemptions. For the case when the CPU voltage and thereby reduce the CPU dynamic power consumption.
power and device power are comparable, these algorithms achieve Now consider a DVS system which consists of a DVS proces-
up to 43% energy savings compared to [1], but only up to 12% over sor interacting with other devices such as SDRAM memory, flash
the non-DVS scheduling. If the device power is large compared to drive, wireless interface, etc. Extending the execution time of a
the CPU power, we show that DVS should not be employed. task results in a reduction in the CPU dynamic power consumption
but it also results in an increase in the device standby energy con-
sumption. Since the device energy consumption can be comparable
Categories and Subject Descriptors to that of a DVS processor (such as StrongArm), their contribution
D.4.1 [Operating Systems]: Process Management—Scheduling cannot be ignored.
Recently, there has been some effort in developing task schedul-
General Terms: Algorithms. ing algorithms that minimize the system-level energy consumption
defined by CPU energy + device energy [11, 1]. These include
Keywords an algorithm that procrastinates the execution of tasks in a static
Dynamic task scheduling, energy minimization, optimal scaling schedule [11], and an algorithm that reduces the number of pre-
point, DVS system, real-time emptions for a dynamic schedule [1].
In this paper, we consider the problem of developing dynamic
task scheduling algorithms for periodic tasks that minimize the
1. INTRODUCTION system-level energy. The algorithms use a combination of (i) opti-
With the rapid growth in the portable and mobile device mar- mal speed setting, which is the speed that minimizes the system en-
ket, reducing the energy consumption to extend the battery lifetime ergy for a specific task, and (ii) limited preemption, which reduces
has become an important design metric. Dynamic voltage scaling the number of preemptions and thereby reduces the device standby
(DVS) is a well-known technique in low power design that trades energy. For the case when the CPU power and device power are
off performance for power consumption by lowering the operating comparable, the proposed algorithms duSYS and duSYS PC achieve
large energy savings (up to 30%) compared to the CPU-energy effi-
∗This research was funded in part by the NSF S/I/UCRC Center for cient algorithm duEDF, and up to 43% energy saving compared to
Low Power Electronics (EEC-9523338), and by the NSF I/UCRC the existing system-level energy efficient algorithm lpSEH DP [1].
center, Connection One (EEC-0226846). However, these algorithms save only up to 12% energy saving over
the non-DVS scheduling algorithm. If the device power is large
compared to the CPU power, then we show that a DVS scheme
does not result in lowest energy.
Permission to make digital or hard copies of all or part of this work for The rest of the paper is organized as follows. The paper begins
personal or classroom use is granted without fee provided that copies are with preliminaries like task definitions, DVS system configuration
not made or distributed for profit or commercial advantage and that copies and calculation of optimal speed setting in Section 2. The new
bear this notice and the full citation on the first page. To copy otherwise, to scheduling algorithms are presented in Section 3. The simulation
republish, to post on servers or to redistribute to lists, requires prior specific
permission and/or a fee.
results with random examples are described in Section 4. The paper
DAC 2005, June 13–17, 2005, Anaheim, California, USA. is concluded in Section 5.
Copyright 2005 ACM 1-59593-058-2/05/0006 ...$5.00.

2. BACKGROUND Assume that a single task instance Ji (Ji ∈ T [k] ) is active and it
is scaled by factor s. Then the system energy during the execution
2.1 Task Definition of Ji is
[k]
In this paper, we consider periodic tasks in which the relative E(s) = Pproc · s · AETi + Pdev · s · AETi + E atv
deadline of a task is equal to its period. We denote the k − th [k]
= (s−2 Pref + s · Pdev )AETi + E atv
periodic task in the task set as T [k], which has period P [k] , worst
[k]
case execution time W CET [k], required device set Φ[k] , and opti- where Pdev = Dj ∈Φ[k] Pjstd is the summation of standby energy
mal scaling factor θ [k] which corresponds to the scaling factor that of all devices in the required device set Φ[k] . E atv does not depend
minimizes the energy consumption for executing task T [k] (more on s and is assumed constant during execution of task Ji .
details in Section 2.3). All task execution times are defined accord- [k]
Let Q(s) = s−2 · Pref + s · Pdev . Then E(s) = Q(s) · AETi +
ing to the highest frequency of the DVS processor. atv
E . Since AETi for a task is fixed and Eatv is constant, the
There are multiple instances of each task, and each instance has
value of s that minimizes Q(s) will also minimize E(s).
the same W CET , P , Φ and θ, but has different arrival time, dead-
Since Q(s) is a convex function, we can easily find its minimum
line and execution time. To make the notation simple, we relabel
by calculating the value of s which makes Q (s) = 0. This value
all task instances in the scheduling profile by label J with the in-
dex representative of the order of execution. Task instance Ji has is the optimal scaling factor θ [k] for task T [k].
parameters W CETi , Pi , Φi , θi , arrival time ai and deadline di . 2Pref
θ[k] = ( [k]
)1/3 (1)
2.2 DVS System Configuration Pdev
Consider a typical DVS system that consists of one DVS pro- Thus for every task, there is an optimal scaling factor for which
cessor (also referred to as CPU) and N devices denoted by D1 , the total energy (CPU + device) is minimized.
D2 ,..DN . The DVS processor can operate at different frequency [k]
If Pdev ≥ 2Pref , then θ[k] ≤ 1. In such cases, DVS should
and voltage settings in the active mode. The devices (e.g. SDRAM, [k]
not be employed. If Pdev << 2Pref , the CPU energy dominates,
Flash Drive, etc.), on the other hand, operate at a single frequency and we can ignore the device energy during task scheduling. If
and voltage in the active mode. CPU and device energy are comparable, the optimal scaling factor
θ plays an important role.
2.2.1 DVS Processor Energy Model Since most DVS processors operate on a limited set of voltage
The following parameters are defined for the DVS processor: and frequency levels, we can also numerically find the optimal scal-
fproc , Pproc represent the operating frequency and power; fref , Pref ing point for each task. Let Q(s) = Qproc(s) + Qdev (s), where
represent the reference frequency and power (which are also the Qproc (s) = s · Pproc and Qdev (s) = s · P d[k] .
highest values of fproc , Pproc ). The scaling factor is defined as
fref
s = fproc , s ≥ 1. For long channel devices, scaling the frequency
by a factor of s causes voltage to scale by a factor of s, the cur-
rent to scale by a factor of s2 , and the power to scale by a factor
of s3 . Thus Pproc = s−3 Pref . The optimal scaling factor which
minimizes the CPU energy is defined as Θ.

2.2.2 Device Energy Model
We assume that the devices have three modes of operation: ac-
tive, standby and shutdown. The standby power of device Dj is
Pjstd , and the standby energy is Ej = Pjstd · τ , where τ is the
std
atv
time during which Dj is on. Ej is the active energy of Dj , which
is the active power Pjatv times the number of access during task ex-
ecution. Ej f is the energy when the device is shutdown and we
of

assume that Ej f = 0. If Dj is required by a task, then the device
of
Figure 1: Q(s) vs s for a SA1100 based system
std atv
energy consumption is Ej + Ej when the task is being exe-
Fig 1 illustrates the variation of Qproc (s), Qdev (s) and Q(s)
cuted, and Ej when the task is preempted. If a task is scaled by a
std
with s for a DVS system that consists of a StrongArm SA1100 pro-
factor s (s ≥ 1), Ej is increased by a factor s. There is, however,
std
cessor [12] and devices with different standby power. Note that
atv
no change in Ej . Qproc (s) (line with cross) is not a monotonically decreasing func-
tion. This trend in Qproc (s) has also been pointed out in [4, 13].
2.3 Optimal Scaling Point In fact, if only the SA1100 processor is considered, the optimal
Our goal is to minimize the total energy consumption of the sys- scaling factor is Θ = 2.8. Note that Θ differs from processor to
tem Eproc + Edev , where Eproc is the processor energy, and Edev processor. For the system with P std = 0.2W (such as SDRAM
is the device energy given by Edev = E std + E atv . The optimal [14]), Qdev (s) is shown by the dotted line, and the corresponding
scaling factor for such a system is a function of Eproc + Edev . Q(s) is shown by the line with circles. The optimal scaling factor
Different tasks trigger different sets of devices, and the optimal for this case is θ [k] = 1.39, and the corresponding frequency is 148
scaling factor for each task is different. Let θ [k] be the optimal MHz. For the system when P std is 0.4W (such as flash drive [11]),
scaling factor of a task which minimizes the system energy when θ[k] is 1.07 as shown by the line with squares, and the correspond-
there are no deadline constraints. θ [k] is determined off-line and is ing frequency is 192 MHz. Thus we see that as the device standby
calculated only once for each periodic task T [k]. The procedure is power increases, the scaling factor reduces. Note that the optimal
described below. scaling factor does not depend on the active power of the device.

3. DYNAMIC TASK SCHEDULING device power when tasks are preempted is larger, ϑact ≤ θact , the
Next we present task scheduling algorithms that (i) generate fea- scaling factor of the active task, sact , is smaller.
sible task sets, and (ii) minimize the energy consumption (CPU en-
ergy + device standby energy) of the system. We consider dynamic
3.3 duSYS PC - Preemption Control
scheduling where the AET of the task set is not known apriori. Task preemption helps in better slack utilization and has been
We use the following definitions in the algorithm description. extensively used in DVS schemes that are based on CPU energy
RunQ is the run queue containing all released tasks, Jact is the minimization. However, task preemption increases the lifetime of
active task executed by the processor, Jhigh is the task with highest the preempted task, resulting in an increase in the standby device
priority in RunQ, and Jpre is the active task in the previous cycle energy consumption of the preempted tasks.
which is not finished yet. Here, we describe an algorithm duSYS PC that reduces the pre-
We first use dynamic utilization information to get the maximum emption of tasks scheduled by duSYS. At time t, assume Jhigh is
scaling factor of Jact at time t. For a hyper-period H (L.C.M of about to preempt the execution of Jpre . If we can delay the execu-
periods of tasks), The maximum scaling factor is tion of Jhigh by a time duration τdelay without deadline violation,
and if Jpre finishes in τdelay , then we can successfully avoid pre-
H − t − µ−1 · (W − W CETact) emption. In some cases, Jpre may not be able to finish in τdelay .
du(t) = , (0 ≤ t ≤ H) (2) By delaying the preemption of Jpre , the standby energy of all de-
W CETact
[k]
vices used by Jpre is reduced. Note that τdelay has to respect the
where W is the estimated remaining workload, µ = m W CET k=1 P [k]
deadline of Jhigh .
is the static utilization in EDF (Earliest Deadline First) scheduling. The idea of delay preemption is borrowed from [1] and is used
The speed derived setting by equation (2) lets the active task ab- to calculate τ = W CEThigh × (du(t) − 1). In this algorithm,
sorb all the available slack and at the same time ensures that the τdelay is given by τdelay = τ × m x(i−1) , where x = µ·s1
i=1 pre
remaining tasks can be scaled by a factor not less than µ−1 . and m is typically taken to be 10. (details omitted.)
The skeleton of the proposed EDF based dynamic task schedul-
ing algorithms is given in Algorithm 1. 4. EXPERIMENTAL RESULTS
Algorithm 1 Skeleton of the proposed algorithms In this section, we compare the performance of the algorithms
for randomly generated tasks. We include lpSEH DP [1] in the
1: W = H · µ; comparison since it is the best algorithm (to date) for achieving
2: while time() < hyperperiod do system level energy efficiency for dynamic task scheduling. All the
3: determine sact and execute Jact using sact ; energy consumption values shown in this section are normalized
4: if Jact is not finished then with respect to the non-DVS scheduling result.
5: ExeP art = current duration/sact ; We vary the processor utilization of the tasks from 0.1 to 0.9
6: W = W − ExeP art; with a step of 0.2 and run 100 random task sets for each utilization
7: W CETact = W CETact − ExeP art; value. Each task set consists of 4 periodic tasks, and is generated
8: AETact = AETact − ExeP art; in the following way: period of the tasks is randomly chosen from
9: else 0.1s to 1s, W CET s of the tasks are chosen to satisfy the utilization
10: W = W − W CETact; constraint given apriori (0.1, 0.3, etc.), AET for each task instance
11: end if is given by a Gaussian distribution with mean m = 0.8 × W CET
12: end while and variance σ = 0.067 × W CET . All the task sets are run in a
hyper-period (i.e. the L.C.M of all periods).
The DVS processor is StrongArm SA1100 [12] with 11 frequency
3.1 duEDF - CPU energy only values, and power ranging from 0.1W to 0.54W. We assume that the
Algorithm duEDF minimizes the CPU energy (and not the sys- processor does not consume energy when it is idle and the overhead
tem energy). It is applicable to a system where the CPU energy is of moving from one voltage to another is negligible.
dominant. In this algorithm, Jhigh is always selected as Jact , and
the scaling factor is given by sact = min(du(t), WdCETact , Θ).
act −t 4.1 Experiment 1
Here the first term exploits the maximum available slack, the sec- In this experiment, the processor power and the device standby
ond term ensures that the deadline is not violated, and the third term power are comparable. The required device set for each task is
considers the optimal scaling factor of the processor, Θ. fixed: Φ[1] = {D1 }, Φ[2] = {D1 , D2 }, Φ[3] = D1 and Φ[4] = ∅.
std std
The standby power for devices is P1 = 0.2W and P2 = 0.4W
3.2 duSYS - CPU + device energy (typical values for SDRAM and flash drive [11]).
Algorithm duSYS considers the optimal scaling factor (that takes CPU energy: When only CPU energy is considered, algorithms
into account both the CPU energy and device energy) in the deriva- duEDF and lpSEH DP have energy saving up to 40% compared to
tion of sact . non-DVS scheduling (see Fig 2). Algorithms duSYS and duSYS PC,
on the other hand, have only 25% energy saving compared to the
1: IF Jpre exists, THEN sact = min(du(t), WdCETact , ϑact );
act −t non-DVS case.
dact −t
2: ELSE sact = min(du(t), W CETact , θact ); ENDIF System-level energy: When the processor + device energy is
considered, duEDF and lpSEH DP have consistently higher energy
consumption compared to duSYS and duSYS PC. In fact, duEDF
Here ϑact is the optimal scaling factor when we consider all the and lpSEH DP have much higher energy consumption compared
devices that are on. These include devices associated with pre- to non-DVS scheduling for low processor utilization. For high
empted tasks that are in standby and the devices associated with processor utilization, the increase is not as significant. duSYS and
Jact . θact , on the other hand, is the optimal scaling factor when duSYS PC have up to 12% energy saving compared to the non-DVS
we consider only the devices associated with Jact . Since the total case (see Fig 3).

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Figure 2: Processor energy (Exp.1) Figure 3: System energy (Exp.1) Figure 4: Complexity (Exp.1)

From Fig 3, we also see that the energy consumption of Algo- 5. CONCLUSION
rithms duSYS and duSYS PC is comparable. This implies that pre- In this paper, we consider the problem of developing dynamic
emption control may not really be required for algorithms that min- task scheduling algorithms for periodic tasks that minimize the
imize CPU + device energy. If, however, the cost of preemption is system-level energy. We first determine the ’optimal’ scaling factor
accurately taken into account, duSYS PC would have a noticeably by which a task should be scaled to minimize energy (if there are no
lower energy consumption compared to duSYS. deadline constraints). Then we propose scheduling algorithms that
Complexity: The complexity of each algorithm shown in Fig 4 use a combination of optimal speed setting and limited preemption.
is represented by the average processor time spent on running the When the CPU power and device power are comparable, experi-
algorithm. lpSEH DP has significantly high runtime complexity ments on randomly generated task sets show that the proposed al-
compared to the other algorithms. The proposed algorithms have gorithms duSYS and duSYS PC achieve large energy savings (up to
comparable complexity with duSYS PC being the most complex. 43%) compared to existing dynamic scheduling algorithm [1], and
up to 12% compared to the non-DVS case. We also show that if
4.2 Experiment 2 the device power is large compared to CPU power, then a non-DVS
In this experiment, we study the effect of standby power on the scheme is the one with the lowest energy consumption.
system level energy consumption. We consider three settings of
the standby power: (i) P1 = 20mW and P2 = 40mW , (ii)
std std
std std
P1 = 0.2W and P2 = 0.4W , and (iii) P1 = 2W and std 6. REFERENCES
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22). smlevel energy eff-dynamictaskschedng

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