4. 8085 instruction set i
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This document discusses the instruction set of the 8085 microprocessor. It covers the different instruction groups - data transfer, arithmetic, logical, branch, stack/I/O and machine control. Specific data transfer instructions like MOV, MVI, LXI are explained along with examples. The execution of the MVI B,05H instruction is described step-by-step. Finally, an assignment is given to write programs using data transfer instructions.
![DATA TRANSFER
GROUPMOV 𝑟1, 𝑟2 Move content of 𝑟2 to 𝑟1 T-states: 4 Flags affected: None M-
cycle-1
MOV r, M Move content of [H-L] to r T-states: 7 Flags affected: None M-
cycle-2
MOV M,r Move content of r to [H-L] T-states: 7 Flags affected: None M-
cycle-2
MVI r,data Move immediate data to register T-states: 7 Flags affected: None M-
cycle-2
MVI M,data Move immediate data to memory T-states: 10 Flags affected: None M-
cycle-3
LXI rp, data Load register pair immediate with T-states:10 Flags affected: None M-
cycle-3
16 bit data
Example: LXI H,2500H will load 16 bit data 2500H into H-L pair. In code form it is written
as 21,00,25, where
1st byte of the instruction 21 is the opcode for LXI H. The 2nd byte 00 is 8 LSBs of the data
loaded in L and 25 is the 3rd byte of the instruction which is 8 bit MSBs loaded in H.
LDA addr Load accumulator direct T-states: 13 Flags affected: None
M-cycle-4](https://image.slidesharecdn.com/4-180812142705/85/4-8085-instruction-set-i-3-320.jpg)
![EXECUTION OF MVI
B,05H
T-states: 7, M-cycle: 2
• In T1-state, the high order address {10H} is placed
on the bus A15 ⇔ A8 and low-order address {00H}
on the bus AD7 ⇔ AD0 and ALE = 1.
• In T2 -state, the RD line goes low, and the data 06H
from memory location 1000H are placed on the
data bus. The fetch cycle becomes complete in T3-
state.The instruction is decoded in the T4-state.
• During T4-state, the contents of the bus are
unknown. With the change in the status signal, IO/
M = 0, S1 = 1 and S0 = 0, the
2nd machine cycle is identified as the memory read.
• The address is 1001H and the data byte [05H] is
fetched via the data bus. Both M1 and M2 perform
memory read operation, but the M1 is called op-
code fetch i.e., the 1st machine cycle of each
instruction is identified as the opcode
fetch cycle](https://image.slidesharecdn.com/4-180812142705/85/4-8085-instruction-set-i-5-320.jpg)
4. 8085 instruction set i
- 1. MICROPROCESSOR 8085 LECTURE 7 INSTRUCTION SET-I PROF. SANDIP DAS
- 2. INSTRUCTION CLASSIFICATION • Data Transfer group • Arithmetic group • Logical group • Branch group • Stack, I/O and Machine Control group
- 3. DATA TRANSFER GROUPMOV 𝑟1, 𝑟2 Move content of 𝑟2 to 𝑟1 T-states: 4 Flags affected: None M- cycle-1 MOV r, M Move content of [H-L] to r T-states: 7 Flags affected: None M- cycle-2 MOV M,r Move content of r to [H-L] T-states: 7 Flags affected: None M- cycle-2 MVI r,data Move immediate data to register T-states: 7 Flags affected: None M- cycle-2 MVI M,data Move immediate data to memory T-states: 10 Flags affected: None M- cycle-3 LXI rp, data Load register pair immediate with T-states:10 Flags affected: None M- cycle-3 16 bit data Example: LXI H,2500H will load 16 bit data 2500H into H-L pair. In code form it is written as 21,00,25, where 1st byte of the instruction 21 is the opcode for LXI H. The 2nd byte 00 is 8 LSBs of the data loaded in L and 25 is the 3rd byte of the instruction which is 8 bit MSBs loaded in H. LDA addr Load accumulator direct T-states: 13 Flags affected: None M-cycle-4
- 4. SHLD addr Store H-L pair direct T-states: 16 Flags affected: None M-cycle-5 Example: SHLD 2500 will store the content of L in memory location 2500H and the content of H is stored in 2501H LDAX rp Load accumulator indirect T-states: 7 Flags affected: none M-cycle: 2 Example: LDAX B will load the content of the memory location, whose address is in the B-C pair, into the accumulator. This instruction is used only for B-C and D-E pairs. STAX rp Store accumulator indirect T-states: 7 Flags affected: none M-cycle: 2 Example: STAX D will store the content of the accumulator in the memory location whose address is in the D-E pair. This instruction is used only for B-C and D-E pairs. XCHG Exchange the contents of T-states: 4 Flags affected: none M-cycle: 1 DATA TRANSFER GROUP
- 5. EXECUTION OF MVI B,05H T-states: 7, M-cycle: 2 • In T1-state, the high order address {10H} is placed on the bus A15 ⇔ A8 and low-order address {00H} on the bus AD7 ⇔ AD0 and ALE = 1. • In T2 -state, the RD line goes low, and the data 06H from memory location 1000H are placed on the data bus. The fetch cycle becomes complete in T3- state.The instruction is decoded in the T4-state. • During T4-state, the contents of the bus are unknown. With the change in the status signal, IO/ M = 0, S1 = 1 and S0 = 0, the 2nd machine cycle is identified as the memory read. • The address is 1001H and the data byte [05H] is fetched via the data bus. Both M1 and M2 perform memory read operation, but the M1 is called op- code fetch i.e., the 1st machine cycle of each instruction is identified as the opcode fetch cycle
- 6. EXECUTION TIME OF MVI B,05H Execution time for MVI B,05H i.e., memory read machine cycle and instruction cycle: As we know, clock frequency of 8085 is 3.125 MHz Time (T) for one clock is 1/3.125= 0.32µs Time for memory read=3T=3*0.32µs=0.96µs Total execution time= 7T= 7*0.32µs=2.24µs
- 7. ASSIGNMENT-2 MARKS-5 1. Write a program to get 05H in register A, then MOV it to register B. 2. Write a program to load the content of the memory location FC50H directly to the accumulator, then transfer it to register B. The content of the memory location FC50H is 05. SUBMISSION DATE: 26/07/17