4 ee600 lab2_grp

LAB 2: MODELING IN SPICE 1

Lab 2: Validity, Accuracy, Appropriateness, and Usefulness of Modeling in SPICE

L. Schwappach, T. Thede, D. Wehnes

EE600: Modern Solid State Devices

Colorado Technical University

15 September 2011


Abstract

This lab report begins by testing the validity of an NMOS (MBreakN) transistor model built

using SPICE. Next, given measured data is matched to a model using appropriate MOSFET

theory and equations as necessary to identify accurate parameter values that will correctly fit the

measured results. Once the parameter values are identified and verified for accuracy using

SPICE the appropriateness of modeling is gauged by using models of an NMOS and PMOS

transistor to build a digital CMOS inverter using SPICE and analyzing the CMOS models digital

characteristics. Finally, the usefulness of modeling is obtained by comparing the CMOS model

digital characteristics to the model of a BJT TTL inverter also built using SPICE.


Table of Contents

Objectives

Theory and Design Approaches / Trade-offs

Circuit Schematics

Analysis

Part a - Validity: Model of a MOSFET Transistor in SPICE

Equations and Given Parameter Values

Hand Calculation Results

SPICE Model Results

Validity Comparison of Model and Hand Calculation Results

Part b – Accuracy: Finding Parameters for Accurate MOSFET Modeling.

Equations and Measured Values


Using Results in SPICE to Create an Accurate Model

Accuracy Comparison of Model and Measured Values

Part c: Appropriateness: Modeling a CMOS inverter in SPICE

CMOS: DC Analysis

Function

Threshold Voltage

Noise Margins

Power Curve

CMOS: Time Domain Analysis

Propagation Delays

Rise and Fall Times

Max Switching Frequency

CMOS: Frequency Analysis

CMOS: Fanout Analysis

Table of Results

Conclusions


Part d: Usefulness: Comparison of BJT TTL and CMOS Using SPICE Modeling

TTL: DC Analysis

Function

Threshold Voltage

Noise Margins

Power Curve

TTL: Time Domain Analysis

Propagation Delays

Rise and Fall Times


TTL: Frequency Analysis

Comparison of CMOS and TTL Results

Conclusions


Lab 2: Validity, Accuracy, Appropriateness, and Usefulness of Modeling in SPICE

Objectives

The lab is divided into four parts with different objectives for each part as shown below:

A: The purpose of Lab 2A is to calculate by hand the drain currents Id for various values

of VGS and VDS for a MOSFET in the cut-off, linear and saturation regions of operations. These

calculations will be compared to a SPICE model to verify that the SPICE model is valid.

B: The purpose of Lab 2B is to determine the accuracy of the SPICE model. Measured

values of a MOSFET circuit will be used to hand calculate appropriate input values (VTO, k’

and LAMBDA) for the SPICE model to determine if it provides similar results.

C: The purpose of Lab 2C is to determine if the SPICE model is appropriate for design

efforts by evaluating the digital characteristics of a CMOS inverter. The characteristics to be

evaluated include the voltage transfer, power usage, pulse, frequency response and fanout.

D: The purpose of Lab 2D is to use SPICE modeling to compare two circuits to

determine the usefulness of the SPICE model. The CMOS inverter circuit in Lab 2C will be

compared to a BJT TTL inverter circuit by evaluating the characteristics of each circuit.

Theory and Design Approaches / Trade-offs

There are no specific design requirements for this project since it is not a design project,

but an evaluation of the validity, accuracy, appropriateness, and usefulness of the SPICE model


Circuit Schematics

The schematics for each of the circuits developed in SPICE for each part of the Lab 2 are shown

below:

GND_0

Lab2a VDrain
PSpice Circuit 0Vdc

VGate NMOS
GND_0 I
MbreaknLab2a
0Vdc L = 1u
W = 14u

GND_0 R
1

0

GND_0

Figure 1: MOSFET SPICE NMOS Transistor Model for DC Analysis of Lab 2A


GND_0

Lab2b VDrain
PSpice Circuit 0Vdc

VGate NMOS
GND_0 I
MbreaknLab2a
0Vdc L = 1u
W = 24u

GND_0 R
1

0

GND_0

Figure 2: Modified MOSFET SPICE NMOS Transistor Model for DC Analysis of Lab 2B


GND_0

Vdd
Lab2c CMOS Inverter 5Vdc

PMOS
MbreakpPMOS
W = 24u
L = 1u
Vin
Out
GND_0

0Vdc
NMOS
MbreaknNMOS
GND_0 W = 14u
L = 1u C
90p

0

GND_0 GND_0

Figure 3: CMOS SPICE Model used for DC Analysis of Lab 2C


GND_0

Vdd
Lab2c CMOS Inverter 5Vdc

PMOS
MbreakpPMOS
W = 24u
L = 1u
Vin
Out
GND_0

V1 = 0
V2 = 5 NMOS
PER = 10u MbreaknNMOS
PW = 5u W = 14u
TR = .01u L = 1u C
TF = .01u 90p
TD = 2u

GND_0

GND_0 GND_0

0

Figure 4: CMOS SPICE Model used for Time Domain Analysis of Lab 2C


GND_0

Vdd
5Vdc
Lab2c CMOS Inverter

PMOS
MbreakpPMOS
W = 24u
L = 1u
Vin
Out
GND_0

1mVac
2.1771Vdc NMOS
MbreaknNMOS
W = 14u
L = 1u
GND_0 C1
90p

0
GND_0 GND_0

Figure 5: CMOS SPICE Model used for Frequency Analysis of Lab 2C


GND_0

Vdd
5Vdc
Lab2c CMOS Inverter

PMOS PMOS2
MbreakpPMOS MbreakpPMOS
W = 24u W = 24u
L = 1u L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5
PER = 146.19u NMOS NMOS2
PW = 73.095u MbreaknNMOS MbreaknNMOS
TR = 1n W = 14u W = 14u
TF = 1n L = 1u L = 1u
TD = 2u GND_0 C1
90p

0
GND_0 GND_0 GND_0

Figure 6: CMOS SPICE Model used for Fanout Analysis of Lab 2C at


GND_0

Vdd
5Vdc
Lab2c CMOS Inverter

PMOS PMOS2
W = 24u W = 24u
L = 1u L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5
PER = 1.4619m NMOS NMOS2
TR = 1n W = 14u W = 14u
TF = 1n L = 1u L = 1u
TD = 2u GND_0 C1
90p

0
GND_0 GND_0 GND_0



GND_0

Vdd
5Vdc
Lab2c CMOS Inverter

PMOS PMOS2
W = 24u W = 24u
L = 1u L = 1u
Vin
Out
GND_0
V1 = 0
V2 = 5
PER = 14.619u NMOS NMOS2
TR = 1n W = 14u W = 14u
TF = 1n L = 1u L = 1u
TD = 2u GND_0 C1
90p

0
GND_0 GND_0 GND_0



Lab 2d BJT TTL

Vcc R R1 R3
5Vdc 4k 1.6k 130

Q4
Q2N3904

Vin
Q2
Q1 Q2N3904
Q2N3904 D2
0Vdc D1N4001

Out

CL
Q3 90p
Q2N3904
GND_0
R2
1k
0

GND_0

Figure 9: BJT TTL SPICE Model used for DC Analysis of Lab 2D


Lab 2d BJT TTL

Vcc R R1 R3
5Vdc 4k 1.6k 130

Q4
Q2N3904

Vin
Q2
Q1 Q2N3904
V1 = 0 Q2N3904 D2
V2 = 5 D1N4001
PER = 10u
PW = 5u
TR = .01u Out
TF = .01u
TD = 2u
CL
Q3 90p
Q2N3904
GND_0
R2
1k
0

GND_0

Figure 10: BJT TTL SPICE Model used Time Domain Analysis of Lab 2D


Lab 2d BJT TTL

Vcc R R1 R3
5Vdc 4k 1.6k 130

Q4
Q2N3904

Vin
Q2
Q1 Q2N3904
Q2N3904 D2
1mVac D1N4001
1.3925Vdc
Out

CL
Q3 90p
Q2N3904
GND_0
R2
1k
0

GND_0

Figure 11: BJT TTL SPICE Model used Frequency Analysis of Lab 2D


Analysis

Lab 2A - Validity: Model of a MOSFET in SPICE

Equations and Given Parameter Values

A MOSFET transistor has 3 modes of operation: Cut-off mode, Triode or linear mode,

and saturation mode. The mode of operation is determined by the values of (the voltage

from the Gate to Source), (the Voltage from the Gate to Source), (the Threshold

Voltage). The following simplified equations can be utilized to calculate the effects of the drain

current .

When the transistor is in Cut-off mode:

Equation 1: MOSFET in Cut-off Mode

When the transistor is in Triode or Linear mode:

Equation 2: MOSFET in Triode Mode

When the transistor is in Saturation mode:

Where

Equation 3: MOSFET in Saturated Mode


We were also provided with the following parameters:

Parameter values for &

VGS VDS
a) 0.5 V 3.2 V
b) 1.5 V 0.3 V
c) 1.5 V 1.0 V
d) 1.5 V 2.3 V
e) 3.0 V 0.5 V
f) 3.0 V 2.3 V
g) 3.0 V 5.0 V
h) 5.0 V 0.3 V
i) 5.0 V 5.0 V
Table 1: Table of Values Providing and


Using the given values of , and ; the mode of operation was checked for each

row of Table 1 above. The results are shown by Table 2 below.

Modes of Operation

MODE
a) Cut-off
b) Linear
c) Saturated
d) Saturated
e) Linear
f) Saturated
g) Saturated
h) Linear
i) Saturated
Table 2: Modes of Operation



Hand Calculations were then compiled using the appropriate formulas corresponding

with the various appropriate modes of operation and confirmed by all group members. These

results are displayed by Figure 12 below.

Figure 12: Hand Calculations for Lab 2A


SPICE Model Results

Next a SPICE project file was created by modeling a NMOS MOSFET using a MbreakN

part in SPICE as shown by Figure 1 in the schematics section. The attributes of the MbreakN

were then modified to contain and display the correct width and length values of the model

. The model for the part was then modified for the correct given model parameter

values as shown by Figure 13.

Figure 13: Model Parameters Used to Modify MbreakN (NMOS) Transistor in Lab 2A

A SPICE DC analysis simulation was ran for analyzing whether or not the model

developed in SPICE would correctly provide the same drain current results calculated using

the fundamental theory and formulas for a MOSFET device. The results are shown in Figure

14.


Figure 14: Spice DC Analysis Results for Lab 2A

Validity Comparison of Model and Hand Calculation Results

The hand calculation results were next compared against the SPICE models results to

determine the validity of the SPICE model NMOS MOSFET. The comparison results are shown

in Table 3.


Validity Comparison

Hand Calculated SPICE Model
% error
ID ID

a) 0 3.21 pA NA

b) 6.615 µA 6.7041 µA 1%

c) 8.052 µA 8.2291 µA 2%

d) 8.513 µA 8.6898 µA 2%

e) 55.125 µA 56.358 µA 2%

f) 127.701 µA 139.021 µA 8%

g) 140.01 µA 154.292 µA 10%

h) 72.765 µA 73.728 µA 1%

i) 526.68 µA 617.23 µA 17%

Table 3: Comparison of Model and Hand Calculations

The model closely matched the hand calculated results in the cut-off and linear or triode

regions (%error was less than 3%). The only significant amount of error 10% and 17% was

observed in the extremely saturated regions at large values of . These differences in values

could be accounted for the fact that SPICE uses additional equations and factors in its

calculations. With such small percent error, it is our conclusion that this SPICE model is a valid

model. We have also gained confidence in using SPICE for modeling NMOS MOSFET devices.


Lab 2B – Accuracy: Finding Parameters for Accurate MOSFET Modeling

Equations and Measured Values

The MOSFET Equations 1-3 were again used along with given measured values and

currents through a MOSFET in order to develop a more accurate MOSFET model using SPICE.

The given measured voltages and currents are shown by Table 4.

Validity Comparison

VGS VDS ID
a) 0.5 V 0.5 V 0.51 pA
b) 0.5 V 2.5 V 2.51 pA
c) 0.5 V 5V 5 pA
d) 1.5 V 0.5 V 895 nA
e) 1.5 V 1V 1 µA
f) 1.5 V 2.5 V 1 µA
g) 3V 0.5 V 3.5778 µA
h) 3V 2.5 V 9.153 µA
i) 3V 5V 9.26 µA
j) 5V 0.5 V 7.15 µA
k) 5V 2.5 V 27 µA
l) 5V 5V 33 µA
Table 4: Measured Values for Lab 2B


In order to create an accurate model our group first needed to identify the mode of

operation that each row of Table 4 above was in. Since we did not know the value of ,we

needed to provide a range of values for . Thus we assumed that was in the range of (0.5 V

< < 1.5 V). Using this range it was discovered that rows g and j were most likely linear

while row I was most likely saturated. With W/L’s ratio given as 24 we were able to use the


linear equation (Equation 2) with the data from rows g and j using linear algebra (substitution

method) in order to solve for a common value of and that could be utilized in SPICE.

Figure 15: Hand Calculation Results for finding Vt and K’ in Lab 2B


From the hand calculated results using data that followed the linear equations for a n-

channel MOSFET we obtained a VT (VTO) of 746.865 mV and (KP) of 148.842 nA/V2.

Now by using both of these values with the formula for a MOSFET in saturation (Equation 3)

and the data from row i (most likely to be saturated) we could find (LAMBDA) as shown by

Figure 16 below.

Figure 16: Hand Calculation Results for finding in Lab 2B

The value of (LAMBDA) was calculated to be .0077342/V.


Using Results in SPICE to Create an Accurate Model

Using these values a new MOSFET model was created (Figure 2) this time providing a

W (width) of 24 um and a L (length) of 1 um. The model for the MbreakN was changed using

the calculated values for LAMBDA, KP, and VTO. A DC Sweep simulation was then

completed to see how the SPICE model approximated the premeasured values. The results are

shown in Figure 17 below.

Figure 17: SPICE Simulation Results for NBreakN (NMOS) Model used in Lab 2B


Accuracy Comparison of Model and Measured Values

The values provided as measured data were then evaluated against the results obtained by

the SPICE model simulation. This comparison is showed by Table 5 below.

Measured drain SPICE model
%
VGS VDS current drain current
error
ID ID
a) 0.5 V 0.5 V 0.51 pA 510 fA 0
b) 0.5 V 2.5 V 2.51 pA 2.51 pA 0
c) 0.5 V 5V 5 pA 5.01 pA 0
d) 1.5 V 0.5 V 895 nA 902.142 nA 1
e) 1.5 V 1V 1 µA 1.0209 µA 2
f) 1.5 V 2.5 V 1 µA 1.0327 µA 3
g) 3V 0.5 V 3.5778 µA 3.5983 µA 1
h) 3V 2.5 V 9.153 µA 9.2427 µA 1
i) 3V 5V 9.26 µA 9.4177 µA 2
j) 5V 0.5 V 7.15 µA 7.233 µA 1
k) 5V 2.5 V 27 µA 27.343 µA 1
l) 5V 5V 33 µA 33.557 µA 2
Table 5: Comparison of SPICE Model and Given Measured Values

From the comparison results, it seems our SPICE model created by fitting the values of

VTO, KP, and LAMBDA to actual measured data was ninety eight percent accurate at modeling

the results provided by given measured values. Thus, this model acted as a highly accurate

(<5% error) model of our real world NMOS MOSFET. It is now apparent that SPICE can

achieve results with an even greater accuracy when the SPICE model uses parameters that best-

fit the real world device. Overall, this is portion of the lab was a success in modeling and in

showing how SPICE models can handle accuracy and complexity.


Lab 2C: Appropriateness: Modeling a CMOS inverter in SPICE

DC Analysis

Function

A CMOS inverter was developed in SPICE (Figure 3) to examine the digital characteristics of

the circuit using the given values shown in Figure 18 and Figure 19 below.

Figure 18: Model Parameters for MbreakN (PMOS) MOSFET used for Lab 2C

Figure 19: Model Parameters for MbreakN (NMOS) MOSFET used for Lab 2C

A plot of the transfer characteristics was then created in SPICE for Vout vs. Vin as shown

in Figure 20 on the next page. From the results it is observed that when a logic low (0) input (0

V) is provided to the circuit a logic high (1) output (5 V) results. Likewise when a logic high (1)

input (5 V) is provided a logic low (0) output (0 V) results. Thus the circuit is functioning as an

inverter.


Inverter Truth Table
In Out
0 1
1 0

Table 6: Inverter Truth Table

Threshold Voltage

There are several ways to identify the circuit’s logic threshold or switching point. One

method used is to draw a line with a slope of one across the output results. For an inverter this is

the point where Vin equals Vout and occurs for this CMOS inverter circuit at 2.1771 V making

this value our switching point also known as voltage threshold VT=2.1771 V as shown by Figure

20 on the next page.

Figure 20: DC Analysis Plots for Vout vs. Vin


Noise Margins

The noise margins for the circuit can also be found using the previously identified (VinA

(low), Vout(high)) and (VinA (high), Vout(low)) points in Figure 20 by finding the values

where the slope of Vout equals -1 (identified in the top plot of Figure 20). The Logic Noise

Margin is the difference between what the circuit outputs as a valid logic voltage and what the

circuit expects to see as a valid logic voltage. The two equations used to find noise margins are:

Noise Margin High = NMH = Vout(high) – Vin(high)

Equation 4: Noise Margin High

Noise Margin Low = NML = Vin(low) – Vout(low)

Equation 5: Noise Margin Low

The higher the noise margins, the better the circuit will be able to handle a diverse range

of logic values. You can find Vout(high), Vout(low), and thus Vin(low), and Vin(high) by using

the method previously mentioned (where slope of Vout equaled -1) or by estimating and using

minimum numbers for high output and maximum numbers for the low output. Since Vout(high)

= 4.7138 V and Vin(high) = 2.5164 V, NMH is 2.197 V. Since Vin(low) = 1.740 V and

Vout(low) = 347mV, NML is 1.393 V. Ideal noise margins would be approximately 2.5 V for

this inverter circuit. Thus the CMOS inverter circuit has a good NMH and a poor NML.


Power Curve

The power used was next analyzed next using the plot in Figure 21 showing power vs.

Vin. As shown in the figure, the power used at Vin = 0 V and Vin = 5 V are both at 25 pW with

the maximum power used when the circuit is switching (inverting) Vin = 2.2020 of 240 µW.

This is an advantage for CMOS, since nearly all of the power used is during the relatively small

time taken for switching.

Figure 21: DC Analysis Plot for Power vs. Vin for CMOS Inverter for Lab 2C


CMOS Time Domain Analysis

Propagation Delays

The circuit was modified as shown by Figure 4 with a 5 us digital pulse (10 µs period, 2

µs delay and 0.01 µs rise and fall times). The low to high propagation delay time for this circuit

(tPLH) is calculated by taking the time at the point the output has risen to fifty percent of the

inputs maximum range plus the inputs minimum value and subtracting the time at which the

input voltage had dropped to fifty percent of its maximum range plus the inputs minimum value.

The high to low propagation delay time for this circuit (tPHL) is calculated by taking the time at

the point the output has dropped to fifty percent of the inputs maximum range plus the inputs

minimum value and subtracting the time at which the input voltage had risen to fifty percent of

its maximum range plus the inputs minimum value. The total propagation delay is the sum of the

two propagation delays (tP = tPLH + tPHL). The following formulas were used for calculating the

propagation delay times. The results are shown by Figure 22 on the next page.

Equation 6: Propagation Delay Low to High

Equation 7: Propagation Delay High to Low

Equation 8: Total Propagation Delay


‘

Figure 22: Pulse Analysis Plot for tPLH and tPHL of CMOS Inverter used in Lab 2C

From the results show by Figure 22 tPLH =721 ns and tPHL = 396 ns. The total

propagation delay tP = 1.117 µs.


Rise and Fall Times

The rise time for this circuit is calculated by taking the time at the point the output has

risen from its minimum to ninety percent of its maximum output range plus the outputs

minimum and subtracting the time at which the output has risen from its minimum to ten percent

of the maximum output range plus its minimum. The fall time for this circuit is calculated by

taking the time at the point the output has fallen from its maximum to ten percent of its

maximum output range plus the outputs minimum and subtracting the time at which the output

has fallen from its maximum to ninety percent of the maximum output range plus its minimum.

These are defined by the following formulas:

Equation 9: Rise Time

Equation 10: Fall Time


Figure 23: Pulse Analysis Plot for tR and tF of CMOS Inverter used in Lab 2C

From the results show by Figure 23 tR =1.688 µs and tF = 969 ns.


The maximum switching frequency for a circuit is normally defined by the time it takes

the circuit to rise and fall from to its maximum and minimum output values. This is normally

computed using the circuits rise and fall times as shown by the formula:

Equation 9: Max Switching Frequency

Using this formula fmax = 376 kHz.


CMOS Frequency Analysis

The power supply in the SPICE model was changed for the next part of the analysis as

shown by Figure 5 and a frequency analysis of the circuit was completed by biasing the circuit

at the threshold voltage. The corner frequency (-3db) of this circuit occurred at f3dB = 6.84 kHz

as shown by Figure 24. The corner frequency represents the -3dB point at which the power is

reduced to ½ of the maximum and the voltage gain is reduced to .707 of maximum.

Figure 24: Frequency Analysis Plot for CMOS Inverter used in Lab 2C


CMOS Fanout Analysis

The pulse input in the SPICE model was changed for the next part of the analysis as

shown in Figure 6 with a second inverter added driven by the output of the first inverter using

the same power supply with a Period of (1/f3dB) = 146.2 µs and PW=73.1 µs. A time domain

analysis of this circuit is shown by Figure 25 below. The pulse input was then modified for a

Period of (1/(.1*f3dB)) = 1.462 ms and PW=731 µs as shown by Figure 7. A time domain

analysis of this circuit is shown by Figure 26 on the next page. The pulse input was then

modified for a Period of (1/(10*f3dB)) = 14.62 µs and PW=7.31 µs as shown by Figure 8. A

time domain analysis of this circuit is shown by Figure 27 on the next page.

Figure 25: Results for CMOS Inverter w/2nd Inverter Added and Period at 1/f3dB.


Figure 26: Results for CMOS Inverter w/2nd Inverter Added and Period at 1/(.1*f3dB).

Figure 27: Results for CMOS Inverter w/2nd Inverter Added and Period at 1/(10*f3dB).


It is apparent from Figures 25-27 that the CMOS inverter creates good output pulses

when the frequency is at (Figure 25) or below (Figure 26) the f3dB point. However as the

output rectangular pulse quickly fails to retain its shape once the frequency is driven beyond the

f3dB frequency.

Table of Results

Ideal This
Evaluation Procedure Parameter
Inverter Inverter
Transfer
VThreshold 2.5 V 2.1771 V
Characteristic
NMH 2.5 V 2.197 V
Noise Margins
NML 2.5 V 1.393 V
P @ VinA = 0
0W 25 pW
V
Power Used P @ VinA = 5
0W 25 pW
V
PMax 0W 240 uW
tPHL 0s 396 ns
Propagation Delays tPLH 0s 721 ns
tP 0s 1.117 us
Rise Time tR 0s 1.688 us
Fall Time tF 0s 969 ns
3dB Corner Frequency F3dB inf. 6.84 kHz
Max Frequency
(Using P-delay fMax inf. 376 kHz
method)
Dual Inverter Pulse Digital Pulse
Perfect Good
Output at f3dB Quality
Perfect Excellent
Output at .1*f3dB Quality
Perfect Poor
Output at 10*f3dB Quality
Table 7: CMOS Results


Part C Conclusions:

In summary, SPICE provided an appropriate model for analyzing the real world CMOS

inverter. Overall, this portion of the lab was a success in modeling and in showing how SPICE

modeling can provide a variety of appropriate analyses results for evaluating integrated circuits.

It took only a few hours in a group to complete all of part 2’s analyses in SPICE making it a

much more efficient use of time than would have occurred by measuring each result physically.

Aspiring engineers need to understand and use the SPICE in order to conduct quality IC

evaluations. The CMOS inverter studied in this section offers great advantages in power over

the TTL inverter studied in Lab 1 and has a good NMH. However the NML, propagation delays,

rise and fall times were worse than the TTL inverter. It was also observed that the CMOS circuit

responded poorly when an additional CMOS circuit was added and the clock frequency was

pushed higher than the f3dB frequency. As a result this CMOS circuit will not function at as

high of speeds as the TTL circuit and has poor fanout.


Lab 2D: Usefulness: Comparison of BJT TTL and CMOS Using SPICE Modeling

DC Analysis

Function

A BJT TTL inverter was developed in SPICE (Figure 9) to obtain the DC characteristics

of the circuit so they can be used to compare the circuit with the CMOS inverter in Lab 2C.

A plot of the transfer characteristics was then created in SPICE for Vout vs. Vin as shown

in Figure 28 on the next page. From the results it is observed that when a logic low (0) input (0

V) is provided to the circuit a logic high (1) output (5 V) results. Likewise when a logic high (1)

input (5 V) is provided a logic low (0) output (0 V) results. Thus the circuit is functioning as an

inverter.

Inverter Truth Table
In Out
0 1
1 0

Table 8: Inverter Truth Table

Threshold Voltage

There are several ways to identify the circuit’s logic threshold or switching point. One

method used is to draw a line with a slope of one across the output results. For an inverter this is

the point where Vin equals Vout and occurs for this CMOS inverter circuit at 1.3925 V making

this value our switching point also known as voltage threshold VT=1.3925 V as shown by Figure

28 on the next page.


Figure 28: DC Analysis Plots for Vout vs. Vin for BJT TTL Inverter for Lab 2D


Noise Margins

The noise margins for the circuit can also be found using the previously identified (Vin

(low), Vout(high)) and (Vin (high), Vout(low)) points in Figure 28 by finding the values where

the slope of Vout equals -1 (identified in the top plot of Figure 28). The Logic Noise Margin is

the difference between what the circuit outputs as a valid logic voltage and what the circuit

expects to see as a valid logic voltage. Once again Equation 4 and Equation 5 were used to

compute noise margins.

Since Vout(high) = 4.7423 V and Vin(high) = 1.4370 V, NMH is 3.305 V. Since

Vin(low) = 606 mV and Vout(low) = 23 mV, NML = 583 mV. Ideal noise margins would be

balanced at approximately 2.5 V for this inverter circuit. Thus the TTL inverter circuit has a

great NMH and a very poor NML.


Power Curve

The power used was next analyzed next using the plot in Figure 29 showing power vs.

Vin. As shown in the figure, the power used at Vin = 0 is 5.386 mW and the power used at Vin

= 5 is 16.772 mW with the maximum power used when the circuit is switching (inverting) at Vin

= 1.43 V is 165 mW. This is a disadvantage of TTL, even when the circuit is not switching it

uses several milliwatts of power.

Figure 29: DC Analysis Plot for Power vs. Vin for BBJT TTL Inverter for Lab 2D


TTL Time Domain Analysis

Propagation Delays

The circuit was modified as shown by Figure 10 with a 5 us digital pulse (10 µs period, 2

µs delay and 0.01 µs rise and fall times) matching the values used for the CMOS inverter. Once

again Equations 6-8 were used for calculating the propagation delay times. The simulation

results are shown by Figure 30.

‘

Figure 30: Pulse Analysis Plot for tPLH and tPHL of TTL Inverter used in Lab 2D

From the results show by Figure 30 tPLH =267 ns and tPHL = 3 ns. The total propagation

delay tP = 270 ns.


Rise and Fall Times

The rise times for the TTL circuit were calculated using Equation 9 and Equation 10,

the formulas for rise and fall time. The simulation results are displayed by Figure 31 below.

Figure 31: Pulse Analysis Plot for tR and tF of CMOS Inverter used in Lab 2C

From the results show by Figure 31 tR =35.4 ns and tF = 4 ns.



Using Equation 9 to compute the maximum frequency the TTL circuit has fmax = 25.4

MHz.

TTL Frequency Analysis

The power supply in the SPICE model was changed for the next part of the analysis as

shown by Figure 11 and a frequency analysis of the circuit was completed by biasing the circuit

at the threshold voltage. The corner frequency (-3db) of this circuit occurred at f3dB = 18.9 MHz

as shown by Figure 32 below.

Figure 32: Frequency Analysis Plot for TTL Inverter used in Lab 2D


Comparison of CMOS and TTL Results

Ideal CMOS TTL
Evaluation Procedure Parameter
Inverter Inverter Inverter
Transfer
VThreshold 2.5 V 2.177 V 1.393 V
Characteristic
NMH 2.5 V 2.197 V 3.305 V
Noise Margins
NML 2.5 V 1.393 V 583 mV
P @ VinA = 0
0W 25 pW 5.386 mW
V
Power Used P @ VinA = 5
0W 25 pW 16.773 mW
V
PMax 0W 240 uW 165 mW
tPHL 0s 396 ns 3 ns
Propagation Delays tPLH 0s 721 ns 267 ns
tP 0s 1.117 us 3 ns
Rise Time tR 0s 1.688 us 35.4 ns
Fall Time tF 0s 969 ns 4 ns
3dB Corner Frequency F3dB inf. 6.84 kHz 18.9 MHz
Max Frequency
(Using P-delay fMax inf. 376 kHz 25.4 MHz
method)
Table 9: Comparison of CMOS and TTL Circuits

Table 9 shows a comparison of the characteristics for the BJT TLL inverter with the

CMOS inverter from Lab 2C. As shown in the table, the BJT TTL inverter is must faster with a

significantly lower rise time, fall time and propagation delays and is able to handle faster clock

speeds. The CMOS inverter makes up for its lack of speed by using significantly less power and

only using that power during switching. Therefore, if speed is the most important circuit

characteristic, the BJT TTL inverter would win. However, if minimum power usage is the most

important characteristic, the CMOS inverter would win. Finally the TTL has a much smaller

NML than the CMOS inverter making the device less resistant to noise interference.


Conclusion for Lab 2D:

In summary, SPICE provided a valid, accurate, appropriate and useful model for

analyzing the BJT TTL and CMOS inverters. This portion of the lab was a success in modeling

and in showing how SPICE modeling can provide a variety of useful analyses for comparing

integrated circuits. Overall this lab demonstrated the power and features of modeling using

SPICE.

4 ee600 lab2_grp

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