Acs ip-so c-10-tips-presentation
- 1. Total Solution Requirements for Enabling Digital and Analog IP Adoption Somnath Viswanath Arasan Chip Systems San Jose, CA, USA Arasan Confidential
- 2. Agenda State of SoC Design Total IP Solution Case Study Conclusion Arasan Confidential
- 3. Trends in IP based SoC design SoCs of today were systems of yesterday Increasing feature integration and resultant design complexity of SoCs translated to horizontal specialization viz EDA Companies, IP Companies, Fabs, etc Design resources and in particular Program Management stretched Arasan Confidential
- 4. Trends in IP based SoC design Increasing complexity of SoCs resulting in pervasive use of 3 rd party Bus IPs Higher speeds necessitating an AFE (PHY) Requires a complete IP solution consisting of RTL IP, PHY IP, vIP, Software stacks and Hardware Platforms for a successful experience Arasan Confidential
- 5. Analog IP for Bus Interfaces Trend in BUS Interfaces is increasing speeds Necessitates an Analog Front-end or PHY UHS II, USB 2.0, USB 3.0, MIPI D-PHY, M-PHY, PCIe …. Analog IPs are ‘Hard Macros’ compared to digital ‘soft macros’, hence not easily portable Silicon proof through Test Chips on different process nodes critical to IP acceptance by customers and to instill confidence Hence a different kind of IP integration challenge Arasan Confidential
- 6. Components of SoC Design Arasan Confidential
- 7. Evolving IP Business Requires a complete IP solution consisting of RTL IP, PHY IP, vIP, Software stacks and Hardware Platforms for a successful experience Arasan Confidential
- 8. “ A Total IP Solution” … but takes much more It starts with… RTL IP Core Oct 5, 2010 Proprietary Arasan Chip Systems SoC Arasan Confidential Verification IP BFM, Test Suites Monitor, Checker Services Customization Tech Support Platforms HDKs, HVPs Analyzers Software Firmware, Drivers Software Stacks SoC
- 9. RTL IP Cores 3 rd Party IP for standardized interfaces Processors, Peripheral Buses, Internal Buses RMM (spyglass) compliant Verilog RTL Silicon proven – FPGA or Test Chips Optimized for area and performance Customizable to fit user SoC environment Arasan Confidential
- 10. verification IP OVM Verification Environment BFMs (Bus Functional Model) Monitor / Checker Compliance Test Suite Test Vectors Suite Arasan Confidential
- 11. Software And Services Firmware and Drivers related to IP cores Software Stack as a function of OS Software development/porting services IP customization & integration services High quality technical support Arasan Confidential
- 12. Hardware Platforms Hardware Development Kits (HDKs) Hardware Validation Platforms (HVPs) Protocol Analyzers Exercising & analysis of bus protocol Arasan Confidential
- 13. MIPI SLIMbus Case Study Arasan Confidential
- 14. MIPI SLIMbus Case Study SLIMbus RTL IP & vIP for peripheral & application processors A portable software stack for creating reference designs and validation of SLIMbus implementations for productization An HDK implementing an instance of host and device for creating a complete reference designs to enable OEM/ODM’s to use SLIM enabled devices in end products An analyzer and exerciser tool to help during development, test and integration of SLIM enabled products Design Services and support to integrate into application and create end products Arasan Confidential
- 15. Arasan Chip Systems Founded in 1995 Headquarters in San Jose, California 100+ Employees Worldwide Profitable IP Solutions Company delivering highly integrated solutions Technology and Solutions Leader – Domain Expertise Leveraging core competency in standards based compliant IP – Internally developed IP solutions Focused on mobile and portable multimedia interface standards, connectivity & bus interfaces and storage memory controllers Delivering on a promise to deliver a “Total IP Solution” Standards Based IP, Verification IP, Hardware Development Kits, Hardware Validation Platforms, Drivers/Stacks and ICs Professional Design Services with focus on customization and IP integration into system-level applications Arasan Confidential Page Arasan Confidential
- 16. IP Portfolio MIPI: Mobile Industry Processor Interface DSI CSI2 SLIMbus UniPro HSI DigRF 3G/4G D-PHY: digital D-PHY: mixed signal M-PHY: digital M-PHY: mixed signal SMIA (not MIPI) Arasan Confidential Page USB: Universal Serial Bus USB 3.0 Host USB 3.0 Device USB 3.0 Hub USB 2.0 Host USB 2.0 Device USB 2.0 Hub USB 2.0 OTG USB 1.1 Host USB 1.1 Device USB 1.1 Hub IP: Intellectual Property Hardware: HDK, HVP, Chips Software: Firmware, Drivers, Stack Memory Controllers SD SDIO eMMC UFS UHS II CF xD Memory Stick Memory Stick Pro CE-ATA NAND Flash Multi-Card Reader * IP can be customized – native local bus, additional features / functions Arasan Confidential VIP: Verification IP Customer Support: Design Services, Consulting
- 17. IP Portfolio Controllers 10/100 Ethernet 10/100/1000 Ethernet Gigabit Ethernet 10 Gigabit Ethernet 1588 PCI PCIe MiniPCI CardBus UART I2C I2S SPI Arasan Confidential Page Bus Interfaces AHB APB AXI BVCI OCP Avalon (Altera) VLIO (Intel) PIF (Tensillica ) Analog PHYs DPHY MPHY USB 3.0 PHY UHS II PHY IP: Intellectual Property Hardware: HDK, HVP, Chips Software: Firmware, Drivers, Stack * IP can be customized – native local bus, additional features / functions Arasan Confidential VIP: Verification IP Customer Support: Design Services, Consulting
- 18. Conclusion Few design companies can do it all Horizontal specialization and the establishment of IP business model Design companies can save effort and improve quality by sourcing complete IP collateral – IP Cores, vIP, Software, HDK from a single vendor Arasan Confidential
Editor's Notes
- #4: Semi IP market ~2B$ Dominated by processor, memory, interface, IP
- #7: Anywhere from 50% to 70+% of blocks can be composed of reusable IP ASIC teams are squeezed
- #9: By providing all of this collateral – design teams can contain design complexity while improving productivitiy Very difficult for Soc teams to have depth of expertise in point protocols
- #11: Open verification methodology verification occupies 70% of time and resources in pre-silicon phase
- #12: System software takes upto 70% of system development time
- #13: SoC architecture prototyping and parallelize system software development
- #19: SoC teams are constantly examining ecosystem to see how they can leverage it – no company can do it all As the IP business evolves – collateral will expand to other downstream areas such as test vectors, and upstream etc. Consultative role of leading IP providers – large OEMs have expertise – smaller players want to take advantage of latest interface IP – but need more hand-holding Vendors that have significant domain expertise, keep up with interface/protocol roadmaps, and provide complete collateral – can achieve significant traction Various risk/reward/licensing models Benefit – TTM, Resource, focus on secret sauce, verification effort Reduce vendor management – under-estimated part of project effort