Mind tree ip soc
- 1. IP Re Engineering – Challenges
- 2. Agenda IP Re Engineering Challenges Introduction
- 3. IP Re Use and Challenges
- 5. Internal IP Vs Third Party IP
- 6. Challenges and solutions
- 7. Challenges
- 8. Internal Vs External Team
- 9. Capabilities of the external Team
- 11. IP ReD
- 12. CSoC Initiative
- 14. IntroductionIP Reuse Time to MarketCostOptimized area, performanceIP Re-engineeringEngineering activities that are aimed to customize, port and make the existing IP available for new designsChallenges: Porting to different Technology libraries (Power, Performance) Verification/Validation/Proto type (Quality) Quality Documentation Support for different teams (internal/external)Enablers: Standard processes/methodology/Framework for Reusable IP DevelopmentIP Qualification and VerificationChip IntegrationIP Distribution and supportSlide 3
- 15. IP Re Engineering ActivitiesDesign Feature Enhancements, Functionality modifications (fixing bugs)Optimizing the design for Power, Performance, AreaInterface/Bus modificationsMaking the design more DFT/implementation friendlyVerification/ValidationVerification Environment optimization for coverage improvement Modifications to reflect and test the DUT enhancementsMethodology migration (e – SV; Legacy – HVL)Integration/Physical Implementation/MaintenanceValidating the IP for Integration Flow validation Release / Version ControlUser Documentation/updateSlide 4
- 16. Internal IP Vs Third Party IP Internal IP IP that were developed and used within the organization Standard based, proprietaryMore visibility to the different designs in which the IP was usedAccess to the design team and details of the design, environment Legacy environment, custom tool flow and proprietary design componentsIntegration issues due to insufficient documentation and validationSupport from the IP owner to re-engineer the IP is possible Third Party IPIndependent vendor developed IP Mostly Standard based Lesser visibility to the different design scenarios in which the IP was used Better user documentation possible as the IP is to be shared with different usersGood qualification process to be in place before the reuse Support for customization from the vendor is key for successSlide 5
- 19. Resource optimization (activities Vs resources)
- 20. Legacy and third party IP
- 21. Team Preparation (training)Reuse Targets Optimization (power, area, Performance)
- 22. Multiple SoC Platforms
- 23. Bus interfaces, ProcessorsQuality/ProcessProcess adherence
- 24. Different flow qualification (CAD)
- 25. Metrics collection and analysis
- 28. Support for global teams and local centers
- 30. Support for external customersScalability & Maintenance Peak requirements handling
- 31. Support for existing IP
- 32. Multiple Target Platforms (Proc, Bus, OS..)Key Challenges
- 33. Internal Team Vs Design Services Team..More often the re-engineering or customization tasks are centered around Technology Migration, Bus interface modification Targeting different SoC platforms, resolving integration issues Improving the quality of the IP (Performance, Power, Area) Optimization of the design and verification environment (coverage improvement for functionality, manufacturing etc.,)Engaging a third party team for effective use of the resources and focused IP re engineering will result inCost savings due to the effective utilization of the team that manages the IP enhancements and improvementsEnables the customer team to focus on the domain specific activitiesBecomes a central team that supports different design teams Serves as a common knowledge platform where the project experiences are fed back and made available for different teamsSlide 8
- 34. Capabilities of the PartnerSlide 9
- 35. IP ReD
- 36. Slide 11Design/Verification IP Re-Engineering Life Cycle
- 37. Slide 12Design/Verification IP Re-Engineering - AuditingExisting DIPDatabase Data Base Analysis Env AnalysisMethodology Compliance Tool-SpecificTool UsedDesign DocumentationRTL Checks (Lint)Limitation on Existing Synthesis Logs & QoR ReportIntegration Compatibility at System levelVerification ReportsFeasibility analysisRe-engineering requirementsNoCustomerApprovalCustomer’s estimation on time and resourcesApproved by customerYesSOW / WBSExecution Phase startsAuditing:
- 38. IP Re-eng schedule and schedule confidence
- 39. IP Re-eng effort estimate – leading to WBS
- 40. Clearly defined Customers & MindTree role in re-eng activity, Receivable and Deliverable
- 42. Entry:
- 44. Latest Data Base of the IP
- 46. Exit:
- 47. Approved Feasibility Report - Effort, Scope, Schedule, Current Status
- 48. IP Auditing ChecklistSlide 13Design/Verification IP Re-Engineering - ExecutionRe-Engineering Requirements Design Document availability?NoYesCode UnderstandingUnderstanding the Design Creating / Enhancing Design Document Re-engineering Scenario Specific ActivitiesReview & Customer approved?NoYesPackagingExecution:
- 49. Follow the guidelines for different scenarios for re-eng and ensure less execution
- 50. Different phases of execution - Design change, RTL Modification, Verification, Synthesis, DFT, STA, P&R
- 51. Each phase is followed by an internal review and tracking
- 52. Entry:
- 53. RTL Data Base
- 54. Feasibility Report and Guidelines
- 56. Exit Criteria:
- 58. Updated design docSlide 14Design/Verification IP Re-Engineering - PackagingPackaging:
- 59. Supported by a well defined check-list for each activity
- 60. Check IP Quality and Use version control to track all the releases
- 62. Reviews and Sign-off at each stage
- 63. Package into MindTree or Customer format
- 65. Entry:
- 68. Exit Criteria:
- 69. Quality Passed IP packaged into a MindTree or Customer formatSlide 15CSoC Infrastructure
- 70. Slide 16AdvantagesRapid Prototyping of SoC’sUnified Platform from Architecture Exploration to System DevelopmentArchitecture ExplorationVirtual PrototypingSoC Development & VerificationIP / SoC ValidationSeamless Software (Low Level Firmware, Middleware, Application) DevelopmentGUI based Automation FrameworkCSoC UniquenessSeamless Migration from AE, VPP, SoC Development to PrototypingNo Processor DependenciesAdaptive Verification Environment
- 71. Slide 17Adaptive Verification Environment
- 73. Slide 19Successful CustomersHappy PeopleInnovative SolutionsOur MissionRajagopalan_venktesan@mindtree.comwww.mindtree.com© 2010 MindTree LimitedCONFIDENTIAL: For limited circulation only