Advances in VLSI Chapter 6 Superbuffers
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This document discusses various techniques for driving large capacitive loads in VLSI circuits, including superbuffers, BiCMOS, and pass transistor logic. It describes superbuffers as symmetric inverters that can supply or remove large currents to switch heavy loads faster than standard inverters. BiCMOS combines bipolar and CMOS technologies, using MOS devices for input and bipolar transistors for current drive and output. Pass transistor logic uses NMOS or CMOS transmission gates controlled by input signals to steer charge between nodes, enabling designs like ROMs and PLAs with minimal power dissipation.
Advances in VLSI Chapter 6 Superbuffers
- 1. ADVANCES IN VLSI DESIGN 12EC009 CHAPTER-6 SUPERBUFFERS, BI-CMOS AND STEERING LOGIC 1Don Bosco Institute of technology Bengaluru
- 2. INTRODUCTION • Used to drive large capacitive loads • Either a large pad Or long line • Bonding pads to interface and Probe pads to test, both present heavy capacitive loads • Long line – delay proportional to square of its length • Types: Inverting or non-inverting, NMOS or CMOS • Alternatives: Bi-CMOS, NMOS or PMOS pass transistors 2Don Bosco Institute of technology Bengaluru
- 3. RC DELAY LINES • Delay depends on Resistance of the segment driving it Capacitance of the segment it drives 3 Don Bosco Institute of technology Bengaluru
- 4. Superbuffers A Superbuffer A symmetric Inverter or ratioless Can supply or remove large currents Switch large capacitive loads faster than a standard inverter Consisting of totem-pole or Push-Pull NMOS SB design: the gate bias twice than standard pull-up inverter So Trise = Tfall CMOS SB design: Pull-up ratio twice the pull-down ratio So Trise = Tfall 4 Don Bosco Institute of technology Bengaluru
- 5. Stick diagrams 5Don Bosco Institute of technology Bengaluru
- 6. NMOS Super Superbuffer Its a combination of Inverting and non inverting superbuffers Inverting – Q1A through Q4A and Non-Inverting – Q1B through Q4B Totem pole output stage Q5 and Q6 Q3A, Q3B, Q5 are zero threshold devices This is faster and Exhibits low power consumption under No- Load condition 6 Don Bosco Institute of technology Bengaluru
- 7. NMOS Tristate Superbuffer Tristate drivers Desirable to : Multiplex a bus Drive large capacitive loads such as pads 7 Don Bosco Institute of technology Bengaluru
- 8. Cont.... 8 Don Bosco Institute of technology Bengaluru
- 9. CMOS Superbuffers Its A... wide channel CMOS inverter or Pair of Inverters When EN is True Q1B,Q3B Are OFF Q2B,Q2A are ON VO1 AND VO2 = Vin BAR When EN is False: Q2B, Q2A Are OFF VO1 = HIGH VO2 = LOW This forces Pad-driver totem pole to be OFF 9 Don Bosco Institute of technology Bengaluru
- 10. Bi-CMOS • Combination of Bipolar and MOS technology • Used for line drivers and sense amplifiers • CMOS – Low power dissipation • Bipolar – Low propagation delay and driving capability • MOS devices provide high input impedance and BJT provides current drive and low output impedance 10 Don Bosco Institute of technology Bengaluru
- 11. Cont.... Figure (a) If input is high, Pull-down FET short circuits the base of Q2 to collector and Pull-up FET is Off, Q1 has no base drive, High resistance at plus rail, resulting in a low output value, reverse happens when input is low Figure (b)- Improved bi-CMOS inverter Q4 turns ON when the input signal goes high, pulling node a down discharging Q1 quickly. As the potential at node a drops,Q6 is turned OFF, allowing Q5 to drive Q2 on hard and pull the output low. When input goes low,Q3 turns ON while Q4 turns OFF,Q1 turns ON fast 11 Don Bosco Institute of technology Bengaluru
- 12. Bi-CMOS implementation of 2-input NAND gate and 2-input NOR gate 12 Don Bosco Institute of technology Bengaluru
- 13. Dynamic Ratioless Inverters • Precharging used to improve the switching performance • Output can be precharged high and selectively discharged low • It requires minimum two clock phases • The bus can be pulled all the way up to VDD 13 Don Bosco Institute of technology Bengaluru
- 14. Pass Transistor Logic • NMOS or PMOS, or a CMOS transmission gate can be used to steer or transfer charge from one node of a circuit to other node, under the control of FETs gate voltage • These chins are used in designing arrays such as ROMs, PLAs, and multiplexers • Two major advantages – Not ratiod devices and minimum geometry – Do not dissipate standby power 14 Don Bosco Institute of technology Bengaluru
- 15. Design rules • One pass transistor never the gate of an other pass transistor • If D signal drops from 5 to 0 V ,then input to the inverter changes from 3.5 V to -1.5 V, so charging and discharging paths should be provided • If any one pass transistor turns off, a low will be latched to the inverter • Charge sharing and sneak path are other problems 15 Don Bosco Institute of technology Bengaluru
- 16. Designing pass transistor logic Strong one 4.5-5.0 V Weak one 3.5-4.5 V Weak zero 0.5-1.5 V Strong zero 0.0-.5 V 16 Don Bosco Institute of technology Bengaluru
- 17. Cont... CMOS Devices • CMOS is superior to NMOS • They output both strong one and strong zero • Two transistors are connected in parallel, it has about half the resistance of a single pass transistors 17 Don Bosco Institute of technology Bengaluru
- 18. Cont... Pass transistor 2-input NAND Gate Pass transistor 2-input NOR Gate 18 Don Bosco Institute of technology Bengaluru
- 19. General functional blocks 19 Don Bosco Institute of technology Bengaluru
- 20. NMOS Function Blocks Don Bosco Institute of technology Bengaluru 20
- 21. 2-input functional block 21Don Bosco Institute of technology Bengaluru
- 22. NOR and NAND structures NMOS ex-OR gates with fixed inputs Stick drawings of NMOS pass transistor two variable function blocks 22Don Bosco Institute of technology Bengaluru
- 23. CMOS Function blocks • This implements 16 logic functions with two input variables A and B, 4 control inputs C0 to C3 23Don Bosco Institute of technology Bengaluru
- 24. THANK YOU 24Don Bosco Institute of technology Bengaluru