CArcMOOC 07.03a - Memory hierarchy - Caching
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The document discusses memory hierarchy in computer architecture, focusing on reference locality, caching, and virtual memory. It highlights the conflicting requirements of memory size, speed, and cost, and explains the principles of locality that influence cache design. The document also covers different types of cache systems, including direct-mapped, set-associative, and fully associative caches, and discusses cache performance metrics and replacement strategies.
CArcMOOC 07.03a - Memory hierarchy - Caching
- 1. Carc 07.03 alessandro.bogliolo@uniurb.it 07. Memory 07.03.a Memory Hierarchy • Reference locality • Caching • Virtual memory Computer Architecture alessandro.bogliolo@uniurb.it
- 2. Carc 07.03 alessandro.bogliolo@uniurb.it Conflicting requirements • Requirements: • Size: Computer systems require an ever increasing amount of main memory • Speed: CPUs are designed assuming that memory accesses take 1 CPU clock cycle • Cost: The memory system should have a marginal impact on the cost of a computer system • Issues: • For a given technology, the access time of a memory device grows with its size • SRAMs are much faster than DRAMs, but they are more expansive and less dense • An ideal memory should be large and cheap as a DRAM and fast as a small SRAM
- 3. Carc 07.03 alessandro.bogliolo@uniurb.it Memory hierarchy • Locality of memory references: • Spatial locality: the likelihood of referencing a memory address is higher if an address near it was just referenced. • Temporal locality: a memory address that is referenced at one point in time is likely to be referenced again sometime in the near future. • Access time of memory devices: • Most DRAM devices can work in page mode to provide a burst of data read from the same row at a speed much higher than the typical access time of a random access
- 4. Carc 07.03 alessandro.bogliolo@uniurb.it Cache • A cache is a small and fast memory that duplicates some of the entries of main memory • Accesses to the cache are much faster than accesses to the main memory • As long as the processor finds in cache the memory entries it needs, the perceived performance is the performance of the cache • The principle of locality is used to decide what to place in cache
- 5. Carc 07.03 alessandro.bogliolo@uniurb.it 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 A 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 B 1 1 1 1 RAM Direct-mapped cache 0 1 0 0 1 1 block address tag index offset 0 0 0 1 1 0 1 1 TAG 0 0 A 0 1 0 1 1 0 B 1 1 1 1 cache
- 6. Carc 07.03 alessandro.bogliolo@uniurb.it 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 A 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 B 1 1 1 1 RAM 0 1 0 0 1 1 tag block address offset Fully associative cache 0 0 0 1 1 0 1 1 TAG 0 0 0 1 1 0 1 1 TAG 0 0 0 1 1 0 1 1 TAG 0 0 0 1 1 0 1 1 A 0 1 0 0 B 1 1 1 0 cache way3 cache way4cache way1 cache way2
- 7. Carc 07.03 alessandro.bogliolo@uniurb.it 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 A 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 B 1 1 1 1 RAM ind 0 1 0 0 1 1 tag block address offset Set-associative cache 0 0 0 1 1 0 1 1 TAG 0 0 0 1 1 0 1 1 TAG 0 A 0 1 0 0 B 1 1 1 1 1 cache way2cache way1
- 8. Carc 07.03 alessandro.bogliolo@uniurb.it 000 00 000 01 000 10 000 11 001 00 001 01 001 10 001 11 010 00 010 01 010 10 010 11 011 00 011 01 011 10 011 11 100 00 100 01 ... 111 11 Cache: block identification log2BlockSize 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 ... 11111 00 000 00 001 00 010 00 011 00 100 00 101 00 110 00 111 01 000 01 001 01 010 01 011 01 100 01 101 01 110 01 111 10 000 10 001 ... 11 111 Tag Index Block Offset Block OffsetBlock Address log2SetSize log2Sets log2Blocks Direct mapped (DM) Set associative (SA) Fully associative (FA) 1-way 2-way 8-way DM SA FA
- 9. Carc 07.03 alessandro.bogliolo@uniurb.it Cache: block replacement • Which block should be replaced on a cache miss? 1. Random (RND) 2. Least-Recently Used (LRU) 3. First In First Out (FIFO) RND and FIFO policies are easier to implement, while LRU is more coherent with locality Caches provide a used flag associated with each block to support an approximation of LRU: - the flag is periodically reset - candidates for replacement on a miss are blocks with flag 0 (i.e., unused since last reset)
- 10. Carc 07.03 alessandro.bogliolo@uniurb.it Cache performance yMissPenaltMissRateHitTimeimeAvgAccessT MissTimeMissRateHitTimeHitRateimeAvgAccessT HitTimeMissTimeyMissPenalt )222( yMissPenaltMissRateHitTimeMissRateHitTimeimeAvgAccessT Level-1 and Level-2 cache: