Chapter 3- Digital Fundamentals by Thomas L. Floyd

© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Floyd, Digital Fundamentals, 10th
ed
Digital
Fundamentals
Tenth Edition
Floyd
Chapter 3
© 2008 Pearson Education

ed
The inverter performs the Boolean NOT operation. When
the input is LOW, the output is HIGH; when the input is
HIGH, the output is LOW.
Summary
Summary
The Inverter A X
Input
A X
Output
LOW (0) HIGH (1)
HIGH (1) LOW(0)
The NOT operation (complement) is shown with an overbar.
Thus, the Boolean expression for an inverter is X = A.

ed
Summary
Summary
The Inverter
Example waveforms:
A
X
A X
A group of inverters can be used to form the 1’s
complement of a binary number: Binary number
1’s complement
1 0 0 0 1 1 0 1
0 1 1 1 0 0 1 0

ed
The AND gate produces a HIGH output when all inputs are
HIGH; otherwise, the output is LOW. For a 2-input gate,
the truth table is
Summary
Summary
The AND Gate
The AND operation is usually shown with a dot between the
variables but it may be implied (no dot). Thus, the AND
operation is written as X = A .
B or X = AB.
Inputs
A B X
Output
0 0
0 1
1 0
1 1
0
0
0
1
A
B
X &
A
B
X

ed
Summary
Summary
Example waveforms:
A
X
The AND operation is used in computer programming as a
selective mask. If you want to retain certain bits of a binary
number but reset the other bits to 0, you could set a mask
with 1’s in the position of the retained bits.
The AND Gate
A
B
X
B
00000011
If the binary number 10100011 is ANDed with
the mask 00001111, what is the result?
&
A
B
X

ed
The OR gate produces a HIGH output if any input is HIGH;
if all inputs are LOW, the output is LOW. For a 2-input
gate, the truth table is
Summary
Summary
The OR Gate
The OR operation is shown with a plus sign (+) between the
variables. Thus, the OR operation is written as X = A + B.
Inputs
A B X
Output
0 0
0 1
1 0
1 1
0
1
1
1
A
B
X A
B
X
≥ 1

ed
Summary
Summary
Example waveforms:
A
X
The OR operation can be used in computer programming to set certain
bits of a binary number to 1.
The OR Gate
B
A
B
X A
B
X
≥ 1
ASCII letters have a 1 in the bit 5 position for lower case letters
and a 0 in this position for capitals. (Bit positions are numbered
from right to left starting with 0.) What will be the result if you
OR an ASCII letter with the 8-bit mask 00100000?
The resulting letter will be lower case.

ed
The NAND gate produces a LOW output when all inputs
are HIGH; otherwise, the output is HIGH. For a 2-input
gate, the truth table is
Summary
Summary
The NAND Gate
Inputs
A B X
Output
0 0
0 1
1 0
1 1
1
1
1
0
A
B
X A
B
X
&
The NAND operation is shown with a dot between the
variables and an overbar covering them. Thus, the NAND
operation is written as X = A .
B (Alternatively, X = AB.)

ed
Summary
Summary
Example waveforms:
A
X
The NAND gate is particularly useful because it is a
“universal” gate – all other basic gates can be constructed
from NAND gates.
The NAND Gate
B
How would you connect a 2-input NAND gate
to form a basic inverter?
A
B
X A
B
X
&

ed
The NOR gate produces a LOW output if any input is
HIGH; if all inputs are HIGH, the output is LOW. For a
2-input gate, the truth table is
Summary
Summary
The NOR Gate
Inputs
A B X
Output
0 0
0 1
1 0
1 1
1
0
0
0
A
B
X A
B
X
≥1
The NOR operation is shown with a plus sign (+) between
the variables and an overbar covering them. Thus, the NOR
operation is written as X = A + B.

ed
Summary
Summary
Example waveforms:
A
X
The NOR operation will produce a LOW if any input is HIGH.
The NOR Gate
B
When is the LED is ON for the circuit shown?
The LED will be on when any of
the four inputs are HIGH.
A
C
B
D
X
330W
+5.0 V
A
B
X A
B
X
≥1

ed
The XOR gate produces a HIGH output only when both
inputs are at opposite logic levels. The truth table is
Summary
Summary
The XOR Gate
Inputs
A B X
Output
0 0
0 1
1 0
1 1
0
1
1
0
A
B
X A
B
X
= 1
The XOR operation is written as X = AB + AB.
Alternatively, it can be written with a circled plus sign
between the variables as X = A + B.

ed
Summary
Summary
Example waveforms:
A
X
Notice that the XOR gate will produce a HIGH only when exactly one
input is HIGH.
The XOR Gate
B
If the A and B waveforms are both inverted for the above
waveforms, how is the output affected?
There is no change in the output.
A
B
X A
B
X
= 1

ed
The XNOR gate produces a HIGH output only when both
inputs are at the same logic level. The truth table is
Summary
Summary
The XNOR Gate
Inputs
A B X
Output
0 0
0 1
1 0
1 1
1
0
0
1
A
B
X A
B
X
The XNOR operation shown as X = AB + AB.
Alternatively, the XNOR operation can be shown with a
circled dot between the variables. Thus, it can be shown as X
= A .
B.
= 1

ed
Summary
Summary
Example waveforms:
A
X
Notice that the XNOR gate will produce a HIGH when both inputs are the
same. This makes it useful for comparison functions.
The XNOR Gate
B
If the A waveform is inverted but B remains the same, how is
the output affected?
The output will be inverted.
A
B
X A
B
X
= 1

ed
Two major fixed function logic families are TTL and CMOS.
A third technology is BiCMOS, which combines the first
two. Packaging for fixed function logic is shown.
Summary
Summary
Fixed Function Logic
14 13 12 1
1 10 9 8
1 2 3 4 5 6 7
0.335 – 0.334 in.
0.228 – 0.244 in.
Lead no.1
identifier
14 13 12 1
1 10 9 8
1 2 3 4 5 6 7
0.740 – 0.770 in.
0.250±0.010 in.
Pin no.1
identifiers
14
1
14
1
DIP package SOIC package

ed
A dual in-line package (DIP) is an electronic device
package with a rectangular housing and two parallel rows of
electrical connecting pins. The package may be through-hole
mounted to a printed circuit board or inserted in a socket.
Summary
Summary

ed
A small-outline integrated circuit (SOIC) is a surface-
mounted integrated circuit (IC) package which occupies an
area about 30–50% less than an equivalent DIP, with a
typical thickness that is 70% less. They are generally
available in the same pinouts as their counterpart DIP ICs.
Summary
Summary

ed
Some common gate configurations are shown.
Summary
Summary
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'00
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'04
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'08
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'02
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'10
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'11
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'20
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'21
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'27
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'32
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'86
14
1
8
7
9
6
10
5
11
4
12
3
13
2
VCC
GND
'30

ed
Logic symbols show the gates and associated pin numbers.
Summary
Summary
VCC
(13) (11)
(12)
(10)
(9)
(5)
(4)
(2)
(1)
(6)
(3)
(8)
(1)
(3)
(2)
(4)
(6)
(5)
(9)
(8)
(10)
(12)
(11)
(13)
(14)
(7)
GND
&

ed
Data sheets include limits and conditions set by the
manufacturer as well as DC and AC characteristics. For
example, some maximum ratings for a 74HC00A are:
Summary
Summary
Parameter Value Unit
Symbol
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V V
VCC
DC InputVoltage (Referenced to GND) –
–
0.5 to V +0.5 V V
CC
0.5 to V +0.5 V V
CC
Vin
DC Output Voltage (Referenced to GND)
Vout
DC Input Current, per pin ± 20 mA
I in
DC Output Current, per pin ± 25 mA
Iout
DC Supply Current, V and GND pins
CC ± 50 mA
ICC
Power Dissipation in StillAir, Plastic or Ceramic DIP † 750
500
450
mW
P
D
SOIC Package †
TSSOP Package †
Storage T
emperature °C
Tstg –65 to + 150
Lead T
emperature, 1 mm from Case for 10 Seconds °C
TL
260
300
Plastic DIP, SOIC, or TSSOP Package
Ceramic DIP
MAXIMUM RATINGS

ed
A Programmable Logic Device (PLD) can be programmed
to implement logic. There are various technologies
available for PLDs. Many use an internal array of AND
gates to form logic terms. Many PLDs can be programmed
multiple times.
Summary
Summary
Programmable Logic
B
B
A
A
X= AB
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell
SRAM
cell

ed
Selected Key Terms
Selected Key Terms
Inverter
Truth table
Timing
diagram
Boolean
algebra
AND gate
A logic circuit that inverts or complements its
inputs.
A table showing the inputs and corresponding
output(s) of a logic circuit.
A diagram of waveforms showing the proper time
relationship of all of the waveforms.
The mathematics of logic circuits.
A logic gate that produces a HIGH output only
when all of its inputs are HIGH.

ed
Selected Key Terms
Selected Key Terms
OR gate
NAND gate
NOR gate
Exclusive-OR
gate
Exclusive-NOR
gate
A logic gate that produces a HIGH output when
one or more inputs are HIGH.
A logic gate that produces a LOW output only
when all of its inputs are HIGH.
A logic gate that produces a LOW output when one
or more inputs are HIGH.
A logic gate that produces a HIGH output only
when its two inputs are at opposite levels.
A logic gate that produces a LOW output only
when its two inputs are at opposite levels.

ed
1. The truth table for a 2-input AND gate is
0 0
0 1
1 0
1 1
Inputs
A B X
Output
0 0
0 1
1 0
1 1
1
0
0
0
Inputs
A B X
Output
0 0
0 1
1 0
1 1
Inputs
A B X
Output
Inputs
A B X
Output
0 0
0 1
1 0
1 1
0
1
1
1
a. b.
c. d.
0
1
1
0
0
0
0
1

ed
2. The truth table for a 2-input NOR gate is
0 0
0 1
1 0
1 1
Inputs
A B X
Output
0 0
0 1
1 0
1 1
Inputs
A B X
Output
0 0
0 1
1 0
1 1
Inputs
A B X
Output
Inputs
A B X
Output
0 0
0 1
1 0
1 1
a. b.
c. d.
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1

ed
3. The truth table for a 2-input XOR gate is
0 0
0 1
1 0
1 1
Inputs
A B X
Output
0 0
0 1
1 0
1 1
Inputs
A B X
Output
0 0
0 1
1 0
1 1
Inputs
A B X
Output
Inputs
A B X
Output
0 0
0 1
1 0
1 1
a. b.
c. d.
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1

ed
4. The symbol is for a(n)
a. OR gate
b. AND gate
c. NOR gate
d. XOR gate
A
B
X
≥ 1

ed
5. The symbol is for a(n)
a. OR gate
b. AND gate
c. NOR gate
d. XOR gate
A
B
X

ed
6. A logic gate that produces a HIGH output only when
all of its inputs are HIGH is a(n)
a. OR gate
b. AND gate
c. NOR gate
d. NAND gate

ed
7. The expression X = A + B means
a. A OR B
b. A AND B
c. A XOR B
d. A XNOR B

ed
8. A 2-input gate produces the output shown. (X represents
the output.) This is a(n)
a. OR gate
b. AND gate
c. NOR gate
d. NAND gate
A
X
B

ed
9. A 2-input gate produces a HIGH output only when the
inputs agree. This type of gate is a(n)
a. OR gate
b. AND gate
c. NOR gate
d. XNOR gate

ed
10. The required logic for a PLD can be specified in an
Hardware Description Language by
a. text entry
b. schematic entry
c. state diagrams
d. all of the above

ed
Answers:
1. c
2. b
3. a
4. a
5. d
6. b
7. c
8. d
9. d
10. d

Chapter 3- Digital Fundamentals by Thomas L. Floyd

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Chapter 3- Digital Fundamentals by Thomas L. Floyd