Cmos Arithmetic Circuits
- 3. Datapath circuit techniques for adders
- 4. Binary adder
- 5. Binary adder
- 6. Special trick for reducing No of transistor Cout = AB + C IN .(A + B) SUM = ABC CN + C ’ OUT (A + B + CIN) The advantage of these type realization is that transistor count is less as compared to earlier realization using expression of slide 5.
- 8. Mirror Adders As discussed is class, Mirror adder circuit is having symmetrical N block and P block.
- 10. Pipelined adder
- 13. Linear carry select adder
- 14. Linear carry select adder: critical path
- 16. Carry look-ahead circuit structures
- 17. Carry save (CSA) and carry propagate (CPA) adders
- 18. Adder delays
- 20. Datapath circuit techniques for multipliers
- 24. Array multiplier
- 25. MxN array multiplier critical path
- 26. Carry ripple vs. carry save array multiplier
- 28. Adder cells in array multiplier
- 36. Parallel vs. serial multipliers
- 37. Parallel vs. serial multipliers
- 42. Binary shifter
- 43. Barrel shifter
- 46. Power considerations in datapath structures
- 49. Architecture trade-offs: reference datapath
- 53. Glitching in NOR chain
- 54. Glitching in RCA
- 55. Switching activity in adders
- 56. Switching activity in multipliers
- 57. Layout strategy for datapath
- 58. Layout strategy for datapaths
- 59. Cell area: 2 vs. 3 metal layer process
- 60. Summary