Vlsi interview questions compilation
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This document contains 136 questions related to digital design topics such as timing analysis, clock tree synthesis, power analysis, physical design, Verilog coding, and more. It covers concepts like setup time equations, hold time violations, statistical timing, ring oscillators, false paths, multicycle paths, crosstalk, clock jitter, power gating, clock tree structures, power reduction techniques, Elmore delay model, IR drop, DRC violations, multi-input switching, transition delay faults, decap cells, miller capacitance, temperature inversion, clock domain crossings, Moore's law, ECC, cache misses, pipelining, resets, synchronization, Dennard scaling, multi-bit flip-flops, correlation
Vlsi interview questions compilation
- 1. 1. Setup time equation ? 2. Hold time equation ? 3. Differences between flop and a latch ? 4. What are different ways to fix a setup time violation ? 5. What are different ways to fix a hold time violation ? 6. What is GBA analysis ? 7. What is the difference between GBA and PBA analysis ? 8. What is AOCV ? 9. What is POCV ? 10. Explain the concept of statistical OCV? 11. What is a ring oscillator, how do you determine the frequency of a ring oscillator ? 12. What is CRPR ? 13. Single cycle path, multicycle path, false path, zero cycle path differences ? a. Write the constraints for a multicycle path of 3 and zero cycle path? 14. Setup and hold constraint equations for multicycle path, zero cycle path ? 15. IO budgeting 16. What is Antenna effect? 17. What is crosstalk ? 18. Different methods to minimize clock crosstalk ? a. Should we fix data crosstalk? 19. How does crosstalk affect setup timing and hold timing ? 20. Which cells among HVT, SVT, LVT cells have more variation w.r.t. P, V, T ? 21. What is a lockup latch, explain its applications ? a. Why should we add a lockup latch? 22. How many timing corners you sign-off your chip ? 23. How to design and write Verilog code for asynchronous FIFO a. Why do we need a FIFO 24. What are the differences between SRAM and DRAM 25. What is the difference between a latch and a flip-flop 26. What is metastability? How to fix this problem? 27. What is a source synchronous clocking scheme? 28. Design a circuit to divide an incoming clock by 2 29. Design a circuit to divide an incoming clock by 3 30. Why is interconnect not scaling as well as transistors? 31. What is clock jitter? a. source jitter and network jitter? 32. Relationship between master clock and generated clock? a. why do we need generated clocks? 33. What is the output of an inverter if the VDD and VSS connections are swapped? 34. Write verilog code for a 3:1 MUX 35. What is zero-wire-load timing? 36. What are various clock tree structures? a. What are the advantages, disadvantages of clock tree, H-tree, clock mesh? 37. What is power gating?
- 2. 38. What is clock gating? 39. What is an ICG? a. How do you model the fan-out of an ICG in synthesis? 40. Explain the concept of MCMM (Multi-Corner-Multi-Mode) 41. What is leakage power, dynamic power and internal power? a. How to reduce leakage power, dynamic power and internal power? 42. What is elmore delay model a. Compute the delay of an RC tree using elmore delay model 43. What is power grid? What stage of the design steps is it planned? 44. Hierarchical design planning, what complexities get added on when we split a big design into blocks? 45. What is a level shifter, retention flop? 46. How do you sign-off static IR drop and dynamic IR drop? 47. How to minimize addition of hold buffers? 48. Write verilog code for a regular encoder and a priority encoder 49. What is JTAG? 50. What is mBIST? 51. If you have 10,000 DRC violations on a post-route database, what would be your approach to fix these violations? 52. Design AND, OR and NOT gates using Muxes 53. How to fix glitch violations? 54. What is Multi-Input-Switching (MIS)? a. How to margin for MIS in timing constraints? 55. What is a Transition Delay Fault? 56. A chip fails to function when it boots up, however, as the temperature is increased, it starts to operate correctly, what could be the reason for it? 57. What are Decap cells? What is the purpose of it? 58. How to select SRAM macro cells for design ? 59. What is a CCS timing model? What deficiencies are addressed from a NLDM timing model? 60. Why should we sign-off max_trans and max_cap violations before chip tapeout? 61. What is miller cap? 62. What is temperature inversion? 63. Write a TCL script to find if two rectangles overlap 64. FSM design questions 65. What are the differences between moore and mealy models? 66. Differences between logically_exclusive, physical_exclusive, asynchronous clock groups 67. clock gating checks a. setup, hold checks 68. How do planar transistors and FinFets differ? Which transistors will have more performance and why? 69. What is DIBL effect? 70. What is double patterning?
- 3. 71. What are blocking and non-blocking assignments in verilog? Details of both these statements 72. What are various techniques to fix a timing violation a. explain with examples 73. State machine to divide the clock by 3/2 74. Two cube calendar puzzle 75. What is the impact of dummy fill on timing? a. How does it affect setup and hold timing 76. What are the different techniques to mitigate congestion in a design? a. What is cell padding? b. What is congestion driven restructuring? 77. Explain the concepts of throughput and latency 78. What is cache miss? 79. What is pipelining? 80. Differences between asynchronous reset and synchronous reset 81. What is a reset synchronizer 82. What are various synchronization techniques in clock domain crossings 83. What is moore’s law and Dennard scaling 84. What is multi-bit flip-flop? What are the advantages, disadvantages using them in synthesis? 85. How to achieve correlation between synthesis and PnR a. How to achieve correlation between PnR and sign-off timing 86. When you have a path with all combinational gates and it is violating by a big number after synthesis, there is no scope to upsize or vtswap, what will you do? 87. What is ECC correction in memories, How is it different from parity? What are the pros and cons of these techniques? 88. What are the various techniques to decrease clock skew? 89. What is useful skew? 90. Write setup and hold timing equations for a T-Flip-Flop 91. Difference between array and dictionary in TCL programming language 92. How will you fix AC EM violations during chip closure 93. What are stuck-at-faults? 94. Design a circuit to generate fibonacci numbers 95. Design a clock mux for glitch free clock switching 96. Design a XOR gate using NAND gates 97. What is time borrowing when you use latches? 98. What is FO4 (Fan-out-of-4)? 99. Can there be negative hold time? Explain a scenario/circuit resulting in negative hold time requirement? 100. Can setup requirement time be negative? Explain. 101. Is NDR better or shielding better for clock tree synthesis? 102. Explain booth’s algorithm for multiplication 103. Design a circuit which outputs a frequency of 2f with an input of f.
- 4. 104. A, B, C are unsigned 32-bit numbers. How many bits are needed for Y = (A * B) + C? 105. Design a Synchronous 2-bit counter using 2 DFFs? 106. Write verilog code for a Flip-flop with an asynchronous reset 107. How do you declare arrays in perl? Declare an array {3, 2}. 108. Maze in form of a binary rectangular matrix, find length of shortest path in the maze a. lee algorithm 109. What are feedthru cells? 110. What is noise margin? 111. Why should we use inverters on the clock tree to minimize clock cycle distortion? 112. Write UPF code for a small design a. examples 113. What techniques will you use to mitigate channel congestion? 114. What are the advantages and disadvantages of different placement algorithms? 115. After base tapeout how do you implement metal only ECOs? 116. Design a sequence detector of the pattern 11011 117. Design an XOR gate using only two 2:1 mux 118. Design a FSM for traffic light controller 119. Design a johnson counter in verilog 120. Equations for resistance and capacitance of a wire 121. What happens if we increase the number of contacts or via between metal layers (redundant via insertion)? 122. Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output? 123. Explain the operation of a 6-T SRAM cells a. read and write operations 124. What is body effect? 125. What is latchup? Explain the methods used to prevent it? 126. What is resistive shielding? 127. Details on FD-SOI technology? 128. What are various synthesis optimization techniques? 129. What is retiming? How is it used to optimize the design? 130. How are standard cells characterized? a. Example of characterization of a AND gate 131. Given a library with several functions, channel lengths, VT-types, how do you prune the cells list for synthesizing the design? 132. In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why? 133. The blocks are timing clean and when integrated at top-level there are lot of setup and hold violations. What are all the possible causes of these new violations? 134. What is binning? How do you determine the criterion for CPU binning? 135. What is DVFS?
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