Cmos digital integrated circuits analysis and design 4th edition kang solutions manual

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F
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CMOS Digital Integrated Circuits Analysis and Design 4th Edition
Kang Solutions Manual
Download:http://testbanklive.com/download/cmos-digital-integrated-
circuits-analysis-and-design-4th-edition-kang-solutions-manual/
Exercise Problems
3.1 Consider a MOS system with the following parameters:
tox 1.6nm
GC
1.04V
N =2.8 1018
cm-3
QOX
q4 1010
C/cm2
a. Determine the threshold voltage VT0 under zero bias at room temperature (T = 300 K).
Note that ox 3.970 and si 11.70 .
SOLUTION :
First, calculate the Fermi potentials for the p-type substrate and for the n-type polysilicon gate:
kT n 1.451010
(substrate)  ln i
0.026V ln 0.49V
q NA  2.81018
The depletion region charge density at VSB
= 0 is found as follows:
QB0
2 q NA Si 2F (substrate)
21.61019
(2.81018
)11.7 8.851014
2 0.49
9.53107
C/cm2
The oxide-interface charge is:
Q q N 1.61019
C 41010
cm-2
6.4109
C/cm2
ox ox
The gate oxide capacitance per unit area is calculated using the dielectric constant of silicon dioxide and
the oxide thickness tox.
3.97 8.851014
F/cm
C ox
2.2106
F/cm2
ox
ox 1.6107
cm
Now, we can combine all components and calculate the threshold voltage.
VT 0 GC 2
F (substrate)
QB0 Qox
Cox Cox
1.04 (0.98) (0.53) (0.03) 0.44V

b. Determine the type (p-type or n-type) and amount of channel implant (NI/cm2
) required to change the
threshold voltage to 0.6V

D
A
n

SOLUTION :
p-type implanted needed in the amount of:
V 0.6 VT0 0.6 0.44 1.04 
qNI
Cox
1.04C 1.04 2.2106
N ox
1.431013
cm-2
I
q 1.61019
3.2 Consider a diffusion area that has the dimensions 0.4m 0.2m and the abrupt junction depth is
32 nm . Its n-type impurity doping level is N =21020
cm-3
and the surrounding p-type substrate doping
level is N =21020
cm-3
. Determine the capacitance when the diffusion area is biased at 1.2V and
substrate is biased at 0V. In this problem, assume that there is no channel-stop implant.
SOLUTION :
C (V ) A
 si q NA ND 1
j
2 N N

VA D 0
kT
0 
q
ln
N A ND
2
i
0.026ln
21020
21020
(1.451010
)2
1.21
A 0.2 0.4 20.2 0.032 20.4 0.032 1.18109
[cm2
]
14 19 40
C (V ) 1.18109 11.7 8.85410 1.610 410 1
j
2
2.181015
[F]
41020
 1.21 1.2
3.3 Describe the relationship between the mask channel length, LM, and the electrical channel length, L.
Are they identical? If not, how would you express L in terms of LM and other parameters?
SOLUTION :
The electrical channel length is related to the mask channel length by:
L LM 2LD
Where LD is the lateral diffusion length.

D
A
3.4 How is the device junction temperature affected by the power dissipation of the chip and its package?
Can you describe the relationship between the device junction temperature, ambient temperature, chip
power dissipation and the packaging quality?
SOLUTION :
The device junction temperature at operating condition is given as Tj Ta Pdiss , where Ta is the ambient
temperature; Pdiss is the power dissipated in the chip; is the thermal resistance of the packaging. A cheap
package will have high which will result in large and possibly damaging junction temperature. Thus the
choice of packaging must be such that it is both economic and pretective of the device.
3.5 Describe the three components of the load capacitance Cload , where a logic gate is driving other fanout
gates.
SOLUTION :
The three major components of the load capacitance are interconnect capacitance, the next stage input
capacitance, i.e., the gate capacitance and the drain parasitic capacitances of the current stage.
3.6 Consider a layout of an nMOS transistor shown in Fig. P3.6.
The process parameters are:
N 21020
cm3
N 21020
cm3
X j 32nm LD
10nm tox
1.6nm VT 0
0.53V
Channelstopdoping16.0( p typesubstratedoping )
Find the effective drain parasitic capacitance when the drain node voltage changes from 1.2V to 0.6V.

GND
n+
Output
n+
i

N

Y=6μm
Wn =10μm
Figure P3.6
SOLUTION :
kT N N 21020
21020
0 ln
q
A D
0.026ln
n 2
(1.451010
)2
1.21
i 
kT N '
N 16 21020
21020
ln A D
0.026ln 2.31osw
q n 2
(1.451010
)2
C si q NA ND 1
j0
2 N N
A D 0
14 19 20
11.7 8.85410 1.610 10
2.61106
[F/cm2
]
21.21
q  N '
N 1
C si A D
josw
2 N '
A D  osw
14 19 20
11.7 8.85410 1.610 1.8810
2.59106
[F/cm2
]
2 2.31

VGS
(V) VDS
(V) VSB
(V) ID
(
0.6 0.6 0.0 6
0.65 0.6 0.0 12
0.9 1.2 0.3 44
1.2 1.2 0.3 156

Cjsw X jCjosw
32109
2.59106
0.083[pF/cm]
A Y W 610 60[m2
]
P 2(Y W ) 2(6 10) 32[m]
0 5


0 2.5
Keq 2 0  5 2.5



5.8967 3.3967 
2 0.8967 0.44
2.5
K '
2

5 2.5 
0 0
eq 0  
5 2.5


5.8967 3.3967 
2 0.8967 0.44
2.5


Cdrain Keq Cj0 A Keq 'Cjsw P
0.44 9.6109
60108
0.461.8471012
32104
5.25[ fF]
3.7 A set of I-V characteristics for an nMOS transistor at room temperature is shown for different
biasing conditions. Figure P3.7 shows the measurement setup.
Using the data, find : (a) the threshold voltage VT0
and, (b) velocity saturation vsat
.
Some of the parameters are given as: W=0.6m, EcL=0.4 V, , tox
= 16 Å, |2F
| = 1.1 V.
A)

T 0
ox 4

t
0 V ID
VDS
VGS VSB
Figure P3.7
SOLUTION :
(a)
First, the MOS transistor is on (ID
> 0) for VGS
> 0 and VDS
> 0. Thus, the transistor must be an n-
channel MOSFET. Assume that the transistor is enhancement-type and, therefore, operating mode.
(V V )2
I W v C GS T
(1 V )
D sat ox
(V V ) E L
DS
GS T c
When VGS and VT are similar, velocity saturation terms are neglected.
Let (V , I ) and (V , I ) be any two current-voltage pairs obtained from the table. Then, the V
GS1 D1 GS2 D2 T0,
can be calculated.
I (V V )2
6A
0.65V 0.6V
12A
D1 GS1 T 0
V 0.48V
(b)
ID2 (VGS 2 V )2 T 0
6A
1
12A
Find velocity saturation
C
3.9 8.851014
21610 F / m
ox
ox 0.16108
(V V )2
I W v C GS T
(1 V )
D sat ox
(V V ) E L
DS
GS T c
2
12 0.6106
v sat
216106 0.17
(1 0.05 0.6)
0.17 0.4
vsat 1.06106
m / s
3.8 Compare the two technology scaling methods, namely, (1) the constant electric field scaling and (2) the
constant power supply voltage scaling. In particular, show analytically by using equations how the delay

Const.E field Const.VDD
W, L,tox 1/ S 1/ S
VDD 1/ S 1
Cox S S
C CoxWL 1/ S 1/ S
kn ,kp S S
IDD 1/ S S
t
CV IDD
1/ S 1/ S2
Power IDDVDD 1/ S2
S
Powerdensity
Power 
Area 

1 S3
ox
20
D D
F
t
time, power dissipation, and power density are affected in terms of the scaling factor, S. To be more
specific, what would happen if the design rules change from, say, 1 μm to 1/S μm (S>1)?
SOLUTION :
delay
3.9 A pMOS transistor was fabricated on an n-type substrate with a bulk doping density of
N 11016
cm3
, gate doping density (n-type poly) of N 1020
cm3
, Q / q 41010
cm2
,
and gate oxide thickness of tox 1.6nm . Calculate the threshold voltage at room temperature for VSB=0.
Use si 11.70
SOLUTION :
kT N 11016
(substrate) ln D,sub
0.026ln 0.348[V]
q ni 1.451010
F (gate) 
kT
ln
ND, poly
q n
0.026ln
110 
1.451010
0.587[V]
i
GC F (substrate) F (gate) 0.348 0.587 0.239[V]
3.9 8.851014
C ox
3.45108
[F / cm2
]ox
ox 0.1104

F
QB0  2qND,sub si 2F
21.61019
1016
11.7 8.851014
2 0.348
4.8108
[C / cm2
]
VT 0 GC 2F
QB0 Qox
Cox Cox
4.8108
41010
1.61019
0.239 2 0.348 
3.45108
3.45108
2.51[V]
3.10 Using the parameters given, calculate the current through two nMOS transistors in series (see Fig.
P3.11), when the drain of the top transistor is tied to VDD
, the source of the bottom transistor is tied
to VSS
= 0 and their gates are tied to VDD
. The substrate is also tied to VSS
= 0 V. Assume that W/L =
10 for both transistors and L=4m.
k' = 168 A/V2
VT0
= 0.48 V
= 0.52 V1/2
|2 | = 1.01 V
Hint : The solution requires several iterations, and the body effect on threshold voltage has to be taken
into account. Start with the KCL equation.
1 V
+1 V
ID= ?
Figure P3.10
SOLUTION :


18
20
10
1 V
+1 V
ID= ?
Vx
Figure P3.10
Since gate voltage is high, the midpoint Vx is expected to be low. Therefore, the load is in saturation and
the driver is in linear region. From KCL
1
k '
W
1 V
ID ID,driver ID,load
V (V )
2 1
k '
W
21 V V V 2
2 L
x T ,L x
2 L
T 0 x x
Using the following two equations to iterate find the solution.
1 V V (V )
2
1.04V V 2
x T ,L x x x
VT ,L (Vx ) 0.48 0.52 1.01 Vx  1.01
The intermediate values are listed in the table:
VT,L(Vx) Vx
0.480 0.1523
0.518 0.1337
0.513 0.1359
0.514 0.1357
0.514 0.1357
I
1
k '
W
(1.04V V 2
) 0.516810 1.04 0.1357 0.13572
103.1[A]
D
2 L
x x
3.11 The following parameters are given for an nMOS process:
tox
= 16 Å
substrate doping NA
= 4·10 cm-3
polysilicon gate doping ND
= 2·10 cm-3
oxide-interface fixed-charge density Nox
= 2·10 cm-3
(a) Calculate VT
for an unimplanted transistor.
(b) What type and what concentration of impurities must be implanted
to achieve VT
= + 0.6 V and VT
= – 0.6 V ?


F
t
SOLUTION :
(a) For unimplanted transistor,
kT n 1.451010
(substrate)  ln i
0.026V ln 0.51V
q NA  41018
( )
kT
ln
ND, poly
 21020 
0.026V ln 0.61V
F gate 
q

ni

 1.451010
GC F (substrate) F (gate) 0.51V 0.61V 1.12V
QB0
2 q NA Si 2F (substrate)
21.61019
(41018
)11.7 8.851014
2 0.51
1.16106
C/cm2
14
C ox 3.97 8.8510 F/cm
2.2106
F/cm2
ox
ox 1.6107
cm
VT 0 GC
 2F (substrate)
QB0 Qox
Cox Cox
(b) For VT= 2V;
1.06 (1.12) (0.53) (0.03) 0.56V
V 2 V
QII
T T 0
C
0.56
QII
C
ox ox
Negative charges needed in this case, so it must be p-type implant in the amount of
QII qNI (VT VT 0 )Cox
2.2106
N (2 0.56) 1.981013
cm3 
I
1.61019

For VT=-2V, positive charges need, must be n-type implant,
6
N (2 0.56)
2.210
3.521013
cm3 
I
1.61019

3.12 Using the measured data given, determine the device parameters VT0
, k, , andassuming F
= –
1.1 V and L=4m.


VGS (V) VDS
(V) VBS
(V) ID
(A)
0.6 0.8 0 8

0.8 0.8 0 59
0.8 0.8 -0.3 37
SOLUTION :
0.8 1.0 0 60

18
20
Because the given device is a long channel device, when VDS≥VGS, the transistor operates in s
aturation region, therefore
I
k
V V
2
1 V
a) Find 
DSAT
2
GS T DS
IDSAT Row4 1VDS Row4 1 60
IDSAT Row2 1 VDS Row2
0.09 V 1

1 0.8 59
b) Find V
I Row2 0.8 V
2
DSAT T 0
I Row1 0.6 V
2
c) Find k:
From Row2 data,
DSAT T 0
VT0=0.48V
59
k
0.8 0.48
2
1 0.09 0.8
2
k 1.08mA/V2
d) Find :
From Row3 data,
37
1075
0.8 V (V 0.3)
2
1 0.09 0.8
2
T BS
VT (VBS 0.3) 0.55V
0.55 0.48  0.3 1.1  1.1
0.52 V1/2
3.13 Using the design rules specified in Chapter 2, sketch a simple layout of an
nMOS transistor on grid paper. Use a minimum feature size of 60 nm. Neglect
the substrate connection. After you complete the layout, calculate approximate
values for Cg
, Csb
, and Cdb
. The following parameters are given.
Substrate doping NA
= 4·10 cm-3
Junction depth = 32 nm
Drain/source doping ND
= 2·10 cm-3
Sidewall doping = 4·109
cm-3
W = 300 nm Drain bias = 0 V
L = 60 nm
tox
= 1.6 nm

t
SOLUTION :
Because the drain bias is equal to 0V, there is no current in the device.
First of all, Cox is calculated like below:
3.97 8.851014
F/cm
C ox
2.2106
F/cm2
ox
ox 1.6107
cm
So total gate capacitance Cg is
Cg Cgb Cgd Cgs
CoxWL CoxWLD CoxWLD
CoxWL(totallength )
2.2102
F/m2
300109
m 60109
m
0.396fF
kT N N 41018
21020
0

q
ln A D
0.026V ln 
n 2 2.1 1020
1.11V
i 
kT N (sw) N 4109
21020
0sw

q
ln A D
0.026V ln
n 2 2.1 1020
0.57V
i 



jsw j0sw j
F
Cj0
 Si q NA ND 1
2 NA ND 0
11.7 8.851014
F/cm1.61019
41018
21020
1
2
54.1108
F/cm2
41018
21020
 1.11V
Cj0sw
 Si q NA ND 1
2 NA ND 0
11.7 8.851014
F/cm 1.61019
4109
21020
1
2
24.11012
F/cm2
4109
21020
 0.57V
The zero-bias sidewall junction capacitance per unit length can also be found as follows.
C C x 24.11012
F/cm2
32107
cm 77.15aF/cm
The total area of the n+/p junctions is calculated as the sum of the bottom area and the sidewall area facing
the channel region.
A (0.3 0.15)m2
(0.15 0.032)m2
0.05m2
P 2 0.3 m 0.15m 0.75m
Cdb A Cj0 P Cjsw
0.05108
cm2
54.1108
F/cm2
0.75104
cm 77.21018
F/cm 0.2711015
F
0.271fF Csb
3.14 An enhancement-type nMOS transistor has the following parameters:
VT0
= 0.48 V
= 0.52 V1/2
= 0.05 V-1
|2 | = 1.01 V
k' = 168 A/V2
(a) When the transistor is biased with VG
= 0.6 V, VD
= 0.22 V, VS
= 0.2 V,
and VB
= 0 V, the drain current is ID
= 24A. Determine W/L.
(b) Calculate ID
for VG
= 1 V, VD
= 0.8 V, VS
= 0.4 V, and VB
= 0 V.
(c) If n = 76.3 cm2/V·s and Cg = Cox·W·L = 1.0 x 10-15 F, find W and L.
SOLUTION :

15


(a) For enhancement transistor and VT0 > 0, it must be nMOS.
VT VT 0  2F VSB  2F
0.48 0.52  1.01 0.2  1.01 0.529V
VDS 4 VGS VT 0.6 0.52 0.08
nMOS transistor is in saturation.
I sat
k
V V
2
1 V
D
2
GS T DS
W 2ID (sat)
L k 'V V
2
1 V
(b)
GS T DS
2 24106
42.92
168106
0.082
1 0.05 0.8
VT VT 0  2F VSB  2F
0.48 0.52  1.01 0.4  1.01 0.575V
VDS 0.02 VGS VT 0.6 0.575 0.025
nMOS transistor is in linear region.
I (lin.)
k ' W
2V V V V 2
1 V
D
2 L  GS T DS DS DS
(c)
84106
42.92
2.16 A
2 0.025 0.02 0.022 1 0.05 0.02
k ' 168106
C 2.2106
F/cm2
ox
n 76.3
L
Cg 10
4.5 10 8
F/cm2
W
Cox

W
42.92
2.2106
L
Solve for W and L,
W 14.2m
L 0.33m

3.15 An nMOS transistor is fabricated with the following physical parameters:
N = 2.4·1018 cm-3
D


A D
2
j
j
j
N (substrate) = 2.4·1018 cm-3
A
+
N (chan. stop) = 1019 cm-3
A
W =400 nm
Y = 175 nm
L = 60 nm
L = 0.01 mD
X = 32 nmj
(a) Determine the drain diffusion capacitance for VDB
= 1.2 V and 0.6 V.
(b) Calculate the overlap capacitance between gate and drain for an
oxide thickness of tox = 18 Å.
SOLUTION :
(a)
kT N N 2.41018
2.41018
0 ln A D
0.026V ln
20
984mV
q
Cj0
ni  2.110
 Si q NA ND 1
2 NA ND 0
11.7 8.851014
F/cm 1.61019
2.41018
2.41018
1
2
31.8108
F/cm2

A W Y W X j
2.41018
2.41018

0.4 0.175 0.4 0.32 0.198 m2

A C
984mV
C V
j0
1
V
0
8 8
C 1.2
0.19810 31.810
0.4231015
F
1
1.2
0.984
8 8
C 0.6
0.19810 31.810
0.496 1015
F
1
0.6
0.984
For sidewall capacitance calculation,
kT N swN 1019
2.41018
ln 0.026V ln 1.02 V
osw
q n 2
2.11020
i



15

t
Cjosw
 Si q NA swND 1
2 NA sw ND  osw
11.7 8.851014
F/cm1.61019
2.41018
1019
1
2
39.6108
F/cm2

2.41018
1019
 1.02V
P X C 2175 400 107
32107
39.6108
Cjsw (V )
j josw

1
V
osw
1.771014
F
1
V
osw
1
V
osw
14
Cjsw
Cjsw
(1.2V )
1.7710
121015
F
1
1.2
1.02
1.771014
(0.6V ) 1410 F
1
0.6
1.02
Cdb
Cdb
1.2V Cj 1.2V Cjsw 1.2V 0.423 12 12.423 fF
0.6V Cj 0.6V Cjsw 0.6V 0.496 39.6 40.096 fF
(b)
3.9 8.851014
C ox
1.92106
F / cm3
ox
ox 18108
C C W L 1.92106
400107
0.01104
0.077 fF
gd ox D

CMOS Digital Integrated Circuits Analysis and Design 4th Edition
Kang Solutions Manual
Download:http://testbanklive.com/download/cmos-digital-integrated-
circuits-analysis-and-design-4th-edition-kang-solutions-manual/
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