![2
3
4
1
Arithmetic expressions,
cont’d. a*b + 5*(c-d)
ADR r7,a
LDR r1,[r7]
ADR r7,b
LDR r2,[r7]
MUL r3,r1,r2
DFG
* -
*
+
a b c d
5
ADR r7,c
LDR r4,[r7]
ADR r7,d
LDR r5,[r7]
SUB r6,r4,r5
MOV r8, #5
MUL r9,r8,r6
ADD r10 r3,r9
code](https://image.slidesharecdn.com/compileroptimization-200903160816/85/Compiler-optimization-31-320.jpg)
![3
21
Control code generation,
cont’d.
ADR r5,a
LDR r1,[r5]
ADR r5,b
LDR r2,b
ADD r3,r1,r2
BLE label3
a+b>0 x=5
x=7
LDR r3,#5
ADR r5,x
STR r3,[r5]
B statement
label 3 LDR r3,#7
ADR r5,x
STR r3,[r5]
statement
...](https://image.slidesharecdn.com/compileroptimization-200903160816/85/Compiler-optimization-33-320.jpg)
![One-dimensional arrays
C array name points to 0th element:
a[0]
a[1]
a[2]
a
= *(a + 1)](https://image.slidesharecdn.com/compileroptimization-200903160816/85/Compiler-optimization-38-320.jpg)
![Two-dimensional arrays
Column-major layout:
a[0,0]
a[0,1]
a[1,0]
a[1,1] = a[i*M+j]
...
M
...
N](https://image.slidesharecdn.com/compileroptimization-200903160816/85/Compiler-optimization-39-320.jpg)
![Loop fusion and
distribution
Fusion combines two loops into 1:
for (i=0; i<N; i++)
a[i] = b[i] * 5;
for (j=0; j<N; j++)
w[j] = c[j] * d[j];
for (i=0; i<N; i++) {
a[i] = b[i] * 5;
w[i] = c[i] * d[i];
}](https://image.slidesharecdn.com/compileroptimization-200903160816/85/Compiler-optimization-44-320.jpg)
Compiler optimization
- 2. WHAT IS A COMPILER? In computing, a compiler is a computer program that translates computer code written in one programming language (the source language) into another language (the target language).
- 3. Compilation Compilation strategy : compilation = translation + optimization
- 4. 2 PHASES OF COMPILATION
- 5. Basic compilation phases HLL parsing, symbol table machine-independent optimizations machine-dependent optimizations assembly
- 8. TERMS
- 9. STEP 1 Intro to lexical analysis
- 12. LEXEMES
- 15. CONVERSION
- 18. ROLE OF ERROR HANDLER
- 19. CORRECTED
- 20. STEP 2
- 21. STEP 2
- 22. STEP 3
- 23. STEP 4
- 24. STEP 4
- 25. STEP 5
- 26. STEP 5
- 27. STEP 6
- 28. Basic compilation techniques statement translation. Procedure linkage. Data structures.
- 29. Statement translation and optimization Source code is translated into intermediate form such as CDFG. CDFG is transformed/optimized. CDFG is translated into instructions with optimization decisions. Instructions are further optimized.
- 30. Arithmetic expressions a*b + 5*(c-d) expression DFG * - * + a b c d 5
- 31. 2 3 4 1 Arithmetic expressions, cont’d. a*b + 5*(c-d) ADR r7,a LDR r1,[r7] ADR r7,b LDR r2,[r7] MUL r3,r1,r2 DFG * - * + a b c d 5 ADR r7,c LDR r4,[r7] ADR r7,d LDR r5,[r7] SUB r6,r4,r5 MOV r8, #5 MUL r9,r8,r6 ADD r10 r3,r9 code
- 32. Control code generation if (a+b > 0) x = 5; else x = 7; a+b>0 x=5 x=7 false True
- 33. 3 21 Control code generation, cont’d. ADR r5,a LDR r1,[r5] ADR r5,b LDR r2,b ADD r3,r1,r2 BLE label3 a+b>0 x=5 x=7 LDR r3,#5 ADR r5,x STR r3,[r5] B statement label 3 LDR r3,#7 ADR r5,x STR r3,[r5] statement ...
- 34. Procedure linkage Need code to: call and return; pass parameters and results. Parameters and returns are passed on stack. Procedures with few parameters may use registers.
- 35. Procedure stacks proc1 growth proc1(int a) { proc2(5); } proc2 SP stack pointer FP frame pointer 5 accessed relative to SP
- 36. ARM procedure linkage APCS (ARM Procedure Call Standard): r0-r3 pass parameters into procedure. Extra parameters are put on stack frame. r0 holds return value. r4-r7 hold register values. r11 is frame pointer, r13 is stack pointer. r10 holds limiting address on stack size to check for stack overflows.
- 37. Data structures Different types of data structures use different data layouts. Some address computation of data structure can be done at compile time, others must be computed at run time.
- 38. One-dimensional arrays C array name points to 0th element: a[0] a[1] a[2] a = *(a + 1)
- 39. Two-dimensional arrays Column-major layout: a[0,0] a[0,1] a[1,0] a[1,1] = a[i*M+j] ... M ... N
- 40. PROGRAM OPTIMIZATION / COMPILER OPTIMIZATION
- 41. Dead code elimination Dead code: #define DEBUG 0 if (DEBUG) dbg(p1); Can be eliminated by analysis of control flow, constant folding. 0 dbg(p1); 1 0
- 42. Loop transformations Goals: reduce loop overhead; increase opportunities for pipelining; improve memory system performance.
- 43. Loop unrolling Reduces loop overhead, enables some other optimizations. for (i=0; i<100; i++) add (); for (i=0; i<50; i++) { add (); add (); }
- 44. Loop fusion and distribution Fusion combines two loops into 1: for (i=0; i<N; i++) a[i] = b[i] * 5; for (j=0; j<N; j++) w[j] = c[j] * d[j]; for (i=0; i<N; i++) { a[i] = b[i] * 5; w[i] = c[i] * d[i]; }
- 45. Loop tiling Breaks one loop into a nest of loops. Changes order of accesses within array.
- 46. Register allocation Goals: choose register to hold each variable; determine lifespan of varible in the register. Basic case: within basic block.
- 47. Register lifetime graph w = a + b; x = c + w; y = c + d; time a b c d w x y 1 2 3 t=1 t=2 t=3
- 48. Instruction scheduling Non-pipelined machines do not need instruction scheduling: any order of instructions that satisfies data dependencies runs equally fast. In pipelined machines, execution time of one instruction depends on the nearby instructions: opcode, operands.
- 49. Reservation table A reservation table relates instructions/time to CPU resources. we check the reservation table to determine whether all resources needed by the instruction are available at that time Time/instr A B instr1 X instr2 X X instr3 X instr4 X
- 50. Software pipelining pipeline bubbles appear that reduce performance. Software pipelining is a technique for reordering instructions across several loop iterations to reduce pipeline bubbles
- 51. Code Rescheduling to Avoid Hazards Fast code: LW Rb,b LW Rc,c LW Re,e ADD Ra,Rb,Rc LW Rf,f SW a,Ra SUB Rd,Re,Rf SW d,Rd 51 Try producing fast code for a = b + c; d = e – f; assuming a, b, c, d ,e, and f in memory. Slow code: LW Rb,b LW Rc,c ADD Ra,Rb,Rc SW a,Ra LW Re,e LW Rf,f SUB Rd,Re,Rf SW d,Rd Compiler optimizes for performance. Hardware checks for safety.