MPI DevCon Hsinchu City 2017: MIPI C-PHY/D-PHY Dual Mode Subsystem Performance & Use Cases
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The document outlines the specifications and performance of MIPI D-PHY and C-PHY, highlighting their advantages and differences, such as data rate, power efficiency, and complexity. It presents the dual-mode subsystem that allows for compatibility between both interfaces while reducing power consumption and silicon area. Various use cases, silicon results, and challenges related to MIPI C-PHY adoption are also discussed, emphasizing its increasing traction in camera and display applications.
![© 2017 MIPI Alliance, Inc.
MIPI C-PHY Adoption
• Camera & Display
– [Cam] Sony / OVT / and others
– [Display] Completed IOT test with most Major DDIC companies
• IP
– Mixel
• AP (SOC)
– SnapDragon, and others
• Tester
– Keysight, Tektronix, Introspect, The Moving Pixel Company
• Common-mode filters
– Murata, Panasonic, TDK
29
Mixel, Inc. Qualcomm Technologies, Inc.](https://image.slidesharecdn.com/hsinchu-mixel-c-phy-d-phy-combo-implementation-171112161255/85/MPI-DevCon-Hsinchu-City-2017-MIPI-C-PHY-D-PHY-Dual-Mode-Subsystem-Performance-Use-Cases-29-320.jpg)
MPI DevCon Hsinchu City 2017: MIPI C-PHY/D-PHY Dual Mode Subsystem Performance & Use Cases
- 1. Ashraf Takla C.K. Lee President & CEO Director, Engineering Mixel, Inc. Qualcomm Technologies, Inc. MIPI C-PHYSM/D-PHYSM Dual Mode Subsystem Performance & Use Cases
- 2. © 2017 MIPI Alliance, Inc. 2 Agenda Mixel, Inc. Qualcomm Technologies, Inc. Technologies, Inc. • MIPI D-PHY spec – Overview – Block diagram • MIPI C-PHY spec – Overview – Block diagram – C-PHY additional block • Comparison: D-PHY vs. C-PHY – Advantage – Disadvantages • Dual mode MIPI D-PHY/MIPI C-PHY • Silicon Results – TX – RX • Use Cases – Camera – Display • Adoption • Challenges • Conclusion • Q & A
- 3. © 2017 MIPI Alliance, Inc. MIPI D-PHY Specifications & Performance • Spec version versus data rate 3 Mixel, Inc. Qualcomm Technologies, Inc. Standard Version Adopted Data Rate (Per Lane) PHY Interface (Per Lane) MIPI D-PHY 1.0 Sep 2009 1.0 Gbps 8 bit 1.1 Dec 2011 1.5 Gbps 8 bit 1.2 Sep 2014 2.5 Gbps 8 bit 2.0 Mar 2016 4.5 Gbps 8/16/32 bit 2.1 March 2017 4.5 Gbps 8/16/32 bit
- 5. © 2017 MIPI Alliance, Inc. MIPI D-PHY HS & LP Operation 5 Mixel, Inc. Qualcomm Technologies, Inc.
- 6. © 2017 MIPI Alliance, Inc. MIPI C-PHY Block Specifications & Performance • Spec version versus data rate 6 Mixel, Inc. Qualcomm Technologies, Inc. Standard Version Adopted Data Rate (Per Trio) PHY Interface (Per Trio) MIPI C-PHY 1.0 Oct 2014 2.5 Gsps 16 bit 1.1 Feb 2016 2.8 Gsps 16/32 bit 1.2 March 2017 3.5 Gsps 16/32 bit Note: A MIPI C-PHY lane is known as a Trio. 1 Sym = 2.28 bits
- 9. © 2017 MIPI Alliance, Inc. MIPI C-PHY Unique Features 9 Mixel, Inc. Qualcomm Technologies, Inc. • Performance (bit rate 2.28x the signaling rate, e.g. 1Gsps=2.28Gbps) – Higher than D-PHY on a nominal 10-wire port by 1.7X • Pins – Fewer pins & balls (due to higher performance per pin) – Flexibility, due to the independence of each lane, clock is embedded, you can borrow one lane from one link to another – Coexists on same pins with MIPI D-PHY • Lower Power at higher data rate applications • Flexibility – Embedded clock enables assignment of any lane on the AP to any link – Free of MIPI D-PHY ‘s need to associate data lanes with a clock lane • Interference (Low emissions) – Embedded clock eliminates clock spur emissions, particularly important in multi-band wireless devices • Embedded control codes enable efficient emerging features: – Alternate Low Power mode (ALP), enables longer reach by eliminating single-ended LP mode, which results in area reduction – Fast BTA operations – Lower latency (LRTE) for time-sensitive links • Lower toggle rate often simplifies manufacturing and lowers costs – More applicable to low cost products, such as low-end cameras
- 12. © 2017 MIPI Alliance, Inc. 12 MIPI D-PHY and MIPI C-PHY Comparison Parameter MIPI D-PHY v1.2 MIPI C-PHY v1.0 Design Simple, source synchronous clock Embedded clock, edge detection CDR Power/Gbps Larger Smaller Area (min. configuration) Smaller Area Larger, Additional blocks Area/Gbps(1) Larger Smaller Bandwidth (D-PHY 1.2 vs. C-PHY 1.0) Max 10G for 4 lanes (10pins) Max 17.1G for 3 lanes (9pins)(2) Mixel, Inc. Qualcomm Technologies, Inc. (1) Four data D-PHY lanes vs. three MIPI C-PHY trios (2) Higher bandwidth due to Encoding
- 13. © 2017 MIPI Alliance, Inc. MIPI D-PHY and MIPI C-PHY Comparison 13 Mixel, Inc. Qualcomm Technologies, Inc. Parameter MIPI D-PHY v1.2 MIPI C-PHY v1.0 Minimum # of pins 4 3 Flexibility All lanes operate together Each Lane works independently. High flexibility Transmission Efficiency 1 Bit/UI 2.28 Bit/UI Testing Challenge due to LP and HS modes Additional complexity due to 3 wires Adoption Long history of use, wider adoption Accelerated adoption, co-exists with MIPI D- PHY
- 14. © 2017 MIPI Alliance, Inc. 14 MIPI D-PHY and MIPI C-PHY Comparison Mixel, Inc. Qualcomm Technologies, Inc. • At the Same Link Rate, C-PHY has: – Fewer wires (up to 40% less) – Lower Toggle Rate/Lane (12.5% lower) – Lower Power Consumption (~20- 50% lower) – Smaller number of lanes, thus smaller area for same Gbps – No Emissions from a Clock Lane
- 15. © 2017 MIPI Alliance, Inc. Mixel Dual Mode MIPI D-PHY/MIPI C-PHY Advantages • Sharing of the serial interface pins • Sharing of common blocks, resulting in area reduction • Power/Gbps reduction • Smooth transition between MIPI D-PHY and MIPI C-PHY • Has the benefit of the MIPI C-PHY PPA improvements, while maintaining compatibility with MIPI D-PHY, using same pins 15 Mixel, Inc. Qualcomm Technologies, Inc.
- 16. © 2017 MIPI Alliance, Inc. Mixel MIPI C-PHY/MIPI D-PHY Combo IP 16 Mixel, Inc. Qualcomm Technologies, Inc. • Combo IP Blocks – Shared between MIPI C-PHY and MIPI D-PHY: • HS-TX, HS-RX, SER, DESER, LP-TX, LP-RX and LP-CD – Added for MIPI C-PHY: • Encoder, Decoder, CDR, Mapper and De-Mapper – All MIPI D-PHY functional blocks are reused for the MIPI C-PHY
- 17. © 2017 MIPI Alliance, Inc. Foundries and nodes S : Silicon-proven P: Pre-silicon Mixel and Qualcomm 17 Foundry 65nm 55nm 40nm 28nm 14nm 10nm 7nm F1 S S P P F2 S F3 S S P Mixel, Inc. Qualcomm Technologies, Inc.
- 19. © 2017 MIPI Alliance, Inc. 19 Silicon Results TX MIPI C-PHY – Eye Diagrams 1.5 GSPS 2.5 GSPS Mixel, Inc. Qualcomm Technologies, Inc.
- 20. © 2017 MIPI Alliance, Inc. 20 Silicon Results TX MIPI C-PHY – Eye Diagrams 2.5 GSPS @ short channel Qualcomm Technologies, Inc. 2.5 GSPS @ std channel1.05 GSPS @ std channel
- 21. © 2017 MIPI Alliance, Inc. 21 Silicon Results TX MIPI C-PHY – Eye Diagrams Sony 6.5 GSPS @ short channel3.5 GSPS @ standard channel
- 22. © 2017 MIPI Alliance, Inc. 22 Silicon results TX MIPI D-PHY – Eye Diagrams 1.5 GBPS 2.5 GBPS Mixel, Inc. Qualcomm Technologies, Inc.
- 23. © 2017 MIPI Alliance, Inc. 23 Silicon Results TX MIPI D-PHY – Eye Diagrams 2.5 GSPS @ short channel Qualcomm Technologies, Inc. 4.5 GSPS @ short channel
- 24. © 2017 MIPI Alliance, Inc. Silicon Results RX - Electrical 24 Mixel, Inc. Qualcomm Technologies, Inc.
- 28. © 2017 MIPI Alliance, Inc. MIPI C-PHY/MIPI D-PHY PPA - Qualcomm 28 Mixel, Inc. Qualcomm Technologies, Inc. • Combo PHY area increment < 10% • Combo PHY can cover wide range of Resolutions : 80Mpbs - 10Gbps - 17.1Gbps - 18Gbps - 23.94Gbps • MIPI C-PHY mode : ~10-30% lower power than DPHY mode because of low freq/ smaller bias / lesser # of lanes
- 29. © 2017 MIPI Alliance, Inc. MIPI C-PHY Adoption • Camera & Display – [Cam] Sony / OVT / and others – [Display] Completed IOT test with most Major DDIC companies • IP – Mixel • AP (SOC) – SnapDragon, and others • Tester – Keysight, Tektronix, Introspect, The Moving Pixel Company • Common-mode filters – Murata, Panasonic, TDK 29 Mixel, Inc. Qualcomm Technologies, Inc.
- 30. © 2017 MIPI Alliance, Inc. MIPI C-PHY Challenges • Unique CDR that needs to be programmed for different data rate ranges • Multi-level signal transmission – Introduces encoding jitter, but no need for multi-level detection on the RX side • Unique Trio-based signaling – PCB design 30 Mixel, Inc. Qualcomm Technologies, Inc.
- 31. © 2017 MIPI Alliance, Inc. Conclusion 31 Mixel, Inc. Qualcomm Technologies, Inc. • MIPI C-PHY is a more complex, powerful and efficient PHY. The MIPI D-PHY/MIPI C-PHY combo is even more so on all accounts • MIPI C-PHY provides PPA improvement at the expense of additional complexity • Combo PHY provides the flexibility to support both PHY’s using same pins with minimal overhead, while enhancing PPA • Most blocks are common between MIPI D-PHY and MIPI C-PHY, and thus are shared, resulting in small overhead for the combo IP • There is good traction for MIPI C-PHY/MIPI D-PHY combo in MIPI CSI℠ applications and MIPI DSI℠ is coming online • The MIPI C-PHY/MIPI D-PHY combo is silicon-proven in multiple nodes and foundries and has been integrated into several end products by many tier-one SOC, sensor, and display vendors
- 32. Ashraf Takla C.K. Lee President & CEO Director, Engineering Mixel, Inc. Qualcomm Technologies, Inc. MIPI C-PHYSM/D-PHYSM Dual Mode Subsystem Performance & Use Cases