CS301ES: ANALOG AND DIGITAL ELECTRONICS unit-3

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING
Instructor
D V S RAMANJANEYULU
Associate Professor
Accredited by NBA & NAAC with “A” Grade
CS301ES : ANALOG & DIGITAL ELECTRONICS

P.KIRAN KUMAR,ECE DEPARTMENT 2
UNIT - III

Digital Operations of a system
•A digital system functions in a binary manner
•It employs devices which exist only in two possible states
Binary State Terminology

Why are Binary Numbers Important?
• We implement circuits using electronic components like
transistors.
– A transistor acts like a switch: either conducting (ON) or non-
conducting (OFF).
– There are billions of such miniature switches in modern-day VLSI chips.
• A switch can represent two states.
– Binary number system also has two digits, 0 and 1.
– We can follow some convention:
• Open switch represents 0, closed switch represents 1.
• Low voltage represents 0, high voltage represents 1.
• Absence of current represents 0, flow of current represents 1.
• Absence of light represents 0, presence of light represents 1.

Why are Binary Numbers Important?
• We concentrate on binary numbers in this course.
• Some conventions followed:
– Bit:
– Nibble:
– Byte:
– Word:
single binary digit (0 or 1)
collection of 4 bits
collection of 8 bits
collection of 16/32/64 bits

Number Systems
Decimal Binary Octal Hexa-decimal
0 0 0 0
1 1 1 1
2 10 2 2
3 11 3 3
4 100 4 4
5 101 5 5
6 110 6 6
7 111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
16 10000 20 10

Binary to Decimal
•Technique
–Multiply each bit by 2n, where n is the “weight” of the bit
–The weight is the position of the bit, starting from 0 on
the right
–Add the results

Binary to Decimal

Octal to Decimal
•Technique
–Multiply each digit by 8n, where n is the
“weight” of the digit
–The weight is the position of the digit,
starting from 0 on the right
–Add the results

Octal to Decimal

Number Systems

Hexadecimal to Decimal
•Technique
–Multiply each digit by 16n, where n is the “weight”
of the digit
–The weight is the position of the digit, starting
from 0 on the right
–Add the results

Hexadecimal to Decimal

Number Systems

Decimal to Binary
•Technique
–Divide by two, keep track of the remainder
–First remainder is bit 0 (LSB, least-significant
bit)
–Second remainder is bit 1
–Etc.

Decimal to Binary

Number Systems

Octal to Binary
•Technique
–Convert each octal digit to a 3-bit equivalent binary
representation

Number Systems

Hexadecimal to Binary
•Technique
–Convert each hexadecimal digit to a 4-bit equivalent binary
representation

Number Systems

Decimal to Octal
•Technique
–Divide by 8
–Keep track of the remainder

Number Systems

Decimal to Hexadecimal
•Technique
–Divide by 16
–Keep track of the remainder

Number Systems

Binary to Octal
•Technique
–Group bits in threes, starting on right
–Convert to octal digits

Number Systems

Binary to Hexadecimal
•Technique
–Group bits in fours, starting on right
–Convert to hexadecimal digits

Number Systems

Octal to Hexadecimal
•Technique
–Use binary as an intermediary

Number Systems

Hexadecimal to Octal
•Technique
–Use binary as an intermediary

Number Systems

Binary Addition
Two n-bit values
–Add individual bits
–Propagate carries
–E.g.,
Two 1-bit values

Multiplication
Binary, two 1-bit values Binary, two n-bit values
–As with decimal values
–E.g.,

Fractions
Binary to decimal

Fractions
Decimal to Binary

Number Systems

Answers

Negative Numbers
1. Sign and Magnitude Representation
2. 1’s Complement Representation
3. 2’s Complement Representation
Goal of negative number systems
•Signed system: Simple. Just flip the sign bit
0 = positive
1 = negative
•One’s complement: Replace subtraction with addition
–Easy to derive (Just flip every bit)
•Two’s complement: Replace subtraction with addition
–Addition of one’s complement and one produces the
two’s complement.

Negative Numbers
Given a positive integer x, we represent -x

Negative Numbers
4-Bit Example

Number Systems
Given n-bits, what is the range of my numbers in each system?

Subtraction Using Addition :: 1’s Complement
• How to compute A – B ?
– Compute the 1’s complement of B (say, B1).
– Compute R = A + B1
– If a carry is obtained after addition is ‘1’:
• Add the carry back to R (called end-around carry).
• That is, R = R + 1.
• The result is a positive number.
Else
•The result is negative, and is in 1’s complement form in R.

Example 1 :: 6 – 2
1’s complement of 2 = 1101
6 :: 0110
-2 :: 1101
1 0011
1
0100 =
+4
End-
around
carry
Assume 4-bit representations.
Since there is a carry, it is added
back to the result.
The result is positive.

Example 2 :: 3 – 5
1’s complement of 5 = 1010
Assume 4-bit representations. Since
there is no carry, the result is
negative.
1101 is the 1’s complement of 0010,
that is, it represents –2.
3 :: 0011
-5 :: 1010
1101 = -2

Subtraction Using Addition :: 2’s Complement
• How to compute A – B ?
– Compute the 2’s complement of B (say, B2).
– Compute R = A + B2
– If a carry is obtained after addition is ‘1’:
• Ignore the carry.
• The result is a positive number.
Else
• The result is negative, and is in 2’s complement form in R.

Example 1 :: 6 – 2
2’s complement of 2 = 1101 + 1 = 1110
6 :: 0110
-2 :: 1110
1 0100 = +4
Ignore carry
Assume 4-bit representations.
Presence of carry indicates that
the result is positive.
No need to add the end-around
carry like in 1’s complement.

Example 2 :: 3 – 5
2’s complement of 5 = 1010 + 1 = 1011
Assume 4-bit representations. Since
there is no carry, the result is
negative.
1110 is the 2’s complement of 0010,
that is, it represents –2.
3 :: 0011
-5 :: 1011
1110 = -2

OR Gate
A Diode logic OR circuit
Boolean Identities

AND Gate
A Diode logic AND circuit
Boolean Identities

NOT Gate or Inverter
A Transistor logic NOT circuit

Exclusive OR gate (XOR gate)
• The output of a two input XOR gate assumes the 1 state if one and
only input assumes the 1 state
• The boolean notation for the XOR is

Exclusive OR gate (XOR gate)

De Morgan’s Laws
• The statement “if and only if all inputs are true(1), then the
output is true(1)” is logically equivalent to the statement “If at
least one input is false(0), then the output is false(0)”
• In boolean notation this equivalence can be written as
or
and its dual
are known as De Morgan’s laws

The NAND gate

The NOR gate

Logic Families

Characteristics
➢ Fan in : The number of inputs that the gate can
handle properly with out disturbing the output
level.
➢ Fan out : The number of inputs that can driven
simultaneously by the output with out disturbing
the output level.
➢ Noise immunity : Noise immunity is the ability of the
logic circuit to tolerate the noise voltage.
➢ Noise Margin : The quantative measure of
noise immunity is called noise margin.

Characteristics
➢ Propagation Delay : The propagation delay of gate is
the average transition delay time for the signal to
propagate from input to output. It is measured in
nanoseconds
➢ Threshold Voltage : The voltage at which the circuit
changes from one state to another state
➢ Operating Speed : The speed of operation of the
logic gate is the time that elapses between giving
input and getting output.
➢ Power Dissipation : The power dissipation is defined
as power needed by the logic circuit.

Diode Transistor Logic
•DTL was first commercial available IC logic family in 53/73 series.
•The basic circuit in the DTL logic is the NAND gate.
•Each input associated with one diode.
•The diode and resistor form an AND gate.
•The transistor services as a NOT gate
A B Y=A.B
0 0 1
0 1 1
1 0 1
1 1 0

Diode Transistor Logic Working
Three input positive NAND (or Negative NOR)gate with DTL Logic

Diode Transistor Logic Working
If any input is low
•The corresponding diode conducts current through Vcc and
resistor into the input node.
•The voltage at point p is equal to the input voltage + diode drop.
•This is an insufficient voltage for conduction of a transistor
•Since the voltage at point p is 0v then the transistor is cut off
state and the output is logic 1.
If all inputs are high
•The transistor is driven into saturation region.
•The voltage at point p is high.
•Hence the output is low.

Diode Transistor Logic Characteristics
It has fan-out of 8
It has high noise immunity.
Power dissipation is 12mw.
Propagation delay is average 30ns.
Noise margin is about 0.7V.

Modified DTL Gates
 Most logic gates are fabricated as an integrated circuit. In
this all the transistors, diodes, resistors and capacitors in a
fairly complicated circuit may be shaped within a tiny chip of
single crystal silicon
It turns out that large values of resistance and capacitance
can not be fabricated economically
In view of these facts the NAND gate is modified for
integrated circuit implementation by eliminating the
capacitor , reducing the resistance values drastically and
using diodes or transistors to replace resistors wherever
possible

Modified DTL Gates
An integrated or Modified positive DTL NAND gate

High Threshold Logic(HTL)
In an Industrial environment
the noise level is quite high
because of the presence of
motors, high voltage
switches, on – off control
circuits ……etc
By using a Zener diode in
the place of diode D2 in the
DTL gate this circuit is
converted to the high noise
immunity gate

Transistor Transistor Logic
•TTL family is a modification to the DTL. It has come to existence so as
to overcome the speed limitations of DTL family. The basic gate of
this family is TTL NAND gate.
• Modifications to DTL NAND-
1. The diodes D1, D2 and D3 are replaced by emitter-base
junctions of a multiple-emitter transistor labeled T1.
2. Diode DA is replaced by collector-base junction of T1.
3. Diode DB is replaced by emitter-base junction of transistor
labeled T2.

Transistor Transistor Logic

Transistor Transistor Logic Working
The working of this circuit is identical to that of DTL circuit.
Case1- When at least one input is logic LOW, transistor Q2 and Q3 are in
cut-off and hence, output of Q3 is HIGH.
Case2- When all inputs are HIGH, Q1 operates in active inverse mode,
driving Q2 & Q3 in saturation. Since Q3 is ON, the output is LOW.
Case3- While all inputs are HIGH, if any of the inputs suddenly goes
LOW, then Q2 and Q3 will be turned off only when stored base
charge is removed. The collector-base junction of Q1 is back-
biased and Q1 operates in normal active region. A large collector
current of Q1 is in such direction that it helps removing base
charge of Q2 and Q3. In this way, the circuit speed is increased in
TTL over speed of DTL.

Transistor Transistor Logic Characteristics
TTL has greater speed than DTL.
Less noise immunity.
It has high noise immunity.
Power dissipation is 10mw.
It has fan-in of 6 and fan-out of 1
 Propagation time delay is 5-15nsec.

Resistor Transistor Logic
 RTL is the first logic family which is not available in
monolithic form.
The basic circuit of the RTL logic family is the NOR.
Each input is associated with one resistor and one
transistor.
The collector of the transistor are tied together at the
output
The voltage levels for the circuit are 0.2v for the low level
and from 1 to 3.6v for the high level

A B Y=A+B
0
0
1
1
0
1
0
1
1
0
0
0
If any input is high the corresponding transistor is driven into
saturation and the output goes low, regardless of the states of the
other transistor.
If all inputs are low then all transistor are in cutoff state and the
output of the circuit goes high.
Truth Table

An RTL positive NOR
gate with a Fan – in of
3 and Fan – out of 5

Characteristics :
•It has a fan-out of 5.
•Propagation delay is 25 ns. Power dissipation is 12 mw.
•Noise margin for low signal input is 0.4 v. Poor noise
immunity.
•Low speed.

Direct Coupled Transistor Logic
 DCTL configuration is the same as RTL except that the
base resistors are omitted
A positive NOR DTCL
gate with a Fan – in of 3
and Fan – out of 2

Emitter Coupled Logic (ECL)

• ECL logic family implements the gates in
differential amplifier configuration in which transistors are never
driven in the saturation region thereby improving the speed
of circuit to a great extent. The ECL family is fastest of all logic families.
• The basic gate of ECL family is NOR gate (OR and NOR together)
as shown in diagram. The output1 is OR output while ouput2 is NOR
output.
• Transistor T1 is applied with input and additional inputs are applied
to transistors (T1’, T1’’, . . .) in parallel with T1. Thus transistor(s) T1
and T2 are connected in differential amplifier configuration.

• Transistors T3 and T4 are emitter-followers used for DC level-shifting
of output voltages.
•The positive supply terminal of the circuit is grounded while negative
supply terminal is at negative 5.2V. This is done to minimize the effect
of noise introduced by the power supply and also to protect the gate
from short-circuit that might occur accidently.
•Both the outputs (HIGH/LOW) for OR and NOR are negative. Thus, to
interface this logic family with other, a translator circuit is needed
which converts negative voltages to compatible positive voltage levels.

MOS Logic family
•MOS logic family implements the logic gates using MOSFET devices.
MOSFETs are high density devices which can easily and economically
fabricated on ICs. MOS logic gates can be fabricated using either only
NMOS or only PMOS devices.
•MOS logic is vastly used in LSI and VLSI devices, such as
microprocessor chips, due to their high density characteristic.

MOS Logic family
NMOS NOR gate
If both transistors T1 and T2
are off i.e. A = B = LOW, then
output is HIGH = VDD.
If either of the inputs is
HIGH, then corresponding
transistor(s) is/are ON, thus
connecting output to GND i.e.
LOW.

MOS Logic family
NMOS NAND gate
If both inputs are ON,
then only both T1 and T2
are ON and output is
LOW; otherwise (when
either or both transistors
are OFF,) the output is
HIGH.

CMOS Logic family
CMOS stands for complementary-MOS, in which both p-channel and
n-channel enhancement MOSFET devices are fabricated on same
chip. This causes density to be reduced and complex fabrication
process. However, CMOS devices consume negligible power and
hence are preferred over MOS devices in battery
operated applications.

CMOS Logic family
CMOS NAND gate T1 and T2 are n-channel
MOSFETs while T3 and T4
are p-channel MOSFETs.
When both inputs A & B
are HIGH, then T1 & T2 are
ON while T3 & T4 are OFF.
Hence, output is connected
to GND i.e. LOW.
If either input is LOW,
then either T3 or T4 is ON,
connecting output is +Vcc
i.e. HIGH.

CMOS Logic family
CMOS NOR gate
Similar is working of
CMOS NOR
gate shown in figure
aside. Here, p-channel
devices are in series and
n-channel devices are in
parallel.

Comparison of Logic Families

CS301ES: ANALOG AND DIGITAL ELECTRONICS unit-3

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