CSN221_Lec_27 Computer Architecture and Microprocessor

Course Website: http://faculty.iitr.ac.in/~sudiproy.fcs/csn221_2015.html
Piazza Site: https://piazza.com/iitr.ac.in/fall2015/csn221
Dr. Sudip Roy
CSN‐221: COMPUTER ARCHITECTURE
AND MICROPROCESSORS
Intel Microprocessor: 8086
(Lecture - 27)

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8086 Microprocessor: Summary

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8086 Microprocessor: Pin Configuration

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8086 Microprocessor: Detailed features
 8086 has 16‐bit ALU; this means 16‐bit numbers are directly processed by
8086.
 It has 16‐bit data bus, so it can read data or write data to memory or I/O
ports either 16 bits or 8 bits at a time.
 It has 20 address lines, so it can address up to 220 i.e. 1048576 = 1Mbytes of
memory (words i.e. 16 bit numbers are stored in consecutive memory
locations). Due to the 1Mbytes memory size multiprogramming is made
feasible as well as several multiprogramming features have been
incorporated in 8086 design.
 8086 comes with different versions. 8086 runs at 5 MHz, 8086‐2 runs at 8
MHz, 8086‐1 runs at 10 MHz.

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8086 Microprocessor: Detailed features
 It comes in 40‐pin configuration with HMOS technology having around
20,000 transistors in its circuitry.
 It has multiplexed address and data bus like 8085 due to which the pin
count is reduced considerably
 Higher Throughput (Speed) (This is achieved by a concept called pipelining).
Fetching the next instruction while current instruction is under execution is
called pipelining.
 But the concept of 8086’s principles and structures is very useful for
understanding other advanced Intel microprocessors

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8086 Microprocessor: Signal Groups

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8086 Microprocessor: Internal Architecture

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Block Diagram
of Internal
Architecture of
8086 (Source:
Wiki)
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Intel 8086
Registers
(Source: Wiki)
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 The execution unit contains the Data and Address registers (GP registers and
Flag Register), the Arithmetic and Logic Unit and the Control Unit.
 The Bus Interface Unit contains Bus Interface Logic, Segment registers,
Memory addressing logic and a Six byte instruction object code queue (4‐
byte instruction object‐code queue in case of 8088 microprocessor).
 The execution unit and the Bus Interface unit operate asynchronously. The
EU waits for the instruction object code to be fetched from the memory by
the BIU.
 The BIU fetches or pre‐fetches the object code (16‐bits at a time) and loads
it into the six bytes queue.
 Whenever the EU is ready to execute a new instruction, it fetches the
instruction object code from the front of the instruction queue and executes
the instruction in specified number of clock periods.

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 If memory or Input/output devices must be accessed in the course of
executing an instruction, then the EU informs the BIU of its needs.
 The BIU completes its operation code (opcode) fetch cycle, if in progress,
and executes an appropriate external access machine cycle in response to
the EU demand.
 The BIU is independent of the EU and attempts to keep the six‐bytes queue
filled with instruction object codes.
 If two or more of these six bytes are empty, then the BIU executes
instruction fetch machine cycles as long as the EU does not have an active
request for the bus access pending.
 If the EU issues a request for the bus access while the BIU is in the middle of
an instruction fetch machine cycle, then the BIU will complete the
instruction fetch machine cycle before honoring the EU bus access request.

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8086 Microprocessor: Registers
 The CPU has eight 16‐bit general registers. They are divided into two files of four
registers each. They are:
(a) The data register file and
(b) The pointer and index register file
 The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source
Index (SI) and Destination Index (DI) registers all are of 16‐bits.
 They can also be used in most arithmetic and logic operations.
 These registers are usually used to hold offset addresses for addressing within a
segment. Offset addressing reduces program size by eliminating the need for each
instruction to specify frequently used addresses.
 The Pointer registers are used to access the current stack segment.
 The index registers are used to access the current data. (Stack segment and data
segment are specific areas of memory.

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8086 Microprocessor: Flag register
 The Execution Unit has a 16‐bit flag register which indicates some conditions
affected by the execution of an instruction.
 Some bits of the flag register control certain operations of the EU.
 The flag register in the EU contains nine active flags
 Six of the nine flags are used to indicate some condition produced by an
instruction. These condition flags are also called status flags of 8086/8088
microprocessor. These are the Carry flag, Parity flag, Auxiliary carry flag, Zero flag,
Sign flag and Overflow flag.
 The other three Control flags are Trap Flag, Direction Flag and Interrupt flag.

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8086 Microprocessor: Flag register

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8086 Microprocessor: ALU

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8086 Microprocessor: BIU
 The BIU sends out addresses, fetches instructions from memory, reads data from
memory and ports, and writes data to ports and memory.
 In other words the BIU handles all transfers of data and addresses on the buses for
the execution unit. The BIU has
1. An instruction queue
2. An Instruction pointer
3. Segment registers

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Memory Segmentation:
1 Mbyte memory

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Advantages of Memory Segmentation:
 Allow the memory capacity to be 1Mb even though the addresses
associated with the individual instructions are only 16 bits wide.
 Facilitate the use of separate memory areas for the program, its data and
the stack.
 Permit a program and/or its data to be put into different areas of memory
each time the program is executed.
 Multitasking becomes easy.

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8086 Microprocessor: Generation of 20 bit physical address
 The 8086 / 8088 microprocessor has 20‐bit address lines. All the registers in
8086 / 8088 are 16‐bits in length. Hence to obtain 20‐bit addresses from the
available 16‐bit registers, all 8086 / 8088 memory addresses are computed
by summing the contents of a segment register and an effective memory
address.
 The effective memory address is computed via a variety of addressing
modes. The process of adding, to obtain 20‐bit address is as follows:
 The selected segment register contents are shifted‐left four bits (i.e., the
contents are multiplied by 16 decimal), and then added to the effective
memory address to generate the actual physical address output.

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Example problem:

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8086 Microprocessor: Addressing Modes
A] Data Category B] Branch Category
A] Data Category
1) Immediate Addressing
2) Direct Addressing ( Segment Override prefix)
3) Register Addressing
4) Register Indirect Addressing
5) Register Relative addressing
6) Base Index addressing
7) Relative Base Index addressing
B] Branch Category :
1) Intra‐segment Direct
2) Inter‐segment Direct
3) Intra‐segment Indirect
4) Inter‐segment Indirect

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8086 Microprocessor: Instruction Set
Classified into 7 categories:
1] Data Transfer
2] Arithmetic
3] Logical
4] Control
5]Processor Control Instructions
6] String Manipulation
7] Interrupt Control

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8086 Microprocessor: Data transfer instructions
Note : Data Transfer Instructions do not affect any flags
1] MOV dest, src
Note that source and destination cannot be memory location. Also source
and destination must be same type.
2] PUSH Src: Copies word on stack.
3] POP dest: Copies word from stack into dest. Reg.
4] IN acc, port : Copies 8 or 16 bit data from port to accumulator.
a) Fixed Port
b) Variable Port
5] OUT port, acc

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8086 Microprocessor: Data transfer instructions
6] LES Reg, Mem: Load register and extra segment register with words from
memory.
7] LDS Reg,Mem: Load register and data segment register with words from
memory.
8] LEA Reg,Src: load Effective address. (Offset is loaded in specified register)
9] LAHF: Copy lower byte of flag register into AH register.
10] SAHF: Copy AH register to lower byte of flag
11] XCHG dest, src: Exchange contents of source and destination.
12] XLAT: Translate a byte in AL. This instruction replaces the byte in AL with
byte pointed by BX.To point desired byte in look up table instruction adds
contains of BX with AL ( BX+ AL). Goes to this location and loads into AL.

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8086 Microprocessor: Arithmetic Instructions
1]ADD dest,src
2] ADC dest,src: Add with carry
3] AAA : ASCII adjust after addition. We can add two ASCII numbers directly
and use AAA after addition so as to get result directly in BCD. (Works with AL
only)
4] DAA : Decimal adjust accumulator. ( Works with AL only)
5] SUB dest, src
6] SBB dest, src: Subtract with borrow.
7] AAS: ASCII adjust for subtraction ( same as AAA and works with AL only)
8] DAS : Decimal adjust after Subtraction. ( works with AL only)

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8086 Microprocessor: Arithmetic Instructions
9] MUL src
10] IMUL src: Multiplication of signed byte.
11] AAM: BCD adjust after multiply. (works with AL only)
12] DIV src If any one attempts to divide by 0 , then ?
13] IDIV: Division of signed numbers
14]AAD: BCD to Binary convert before Division.
15] DEC dest
16] INC dest
17] CWD: Convert signed word to signed double word.

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8086 Microprocessor: Logical Instructions
1] AND dest, src
2] NOT dest: Invert each bit in destination
3] OR dest, src
4] XOR dest, src
5] RCL dest, count : Rotate left through Carry. Rotate as many times as
directly specified in the instruction. For more no.of rotations, count can be
specified in CL register.
6] RCR dest, count : Rotate right through carry
7] ROL dest, count : Rotate left ( into carry as well as into LSB)
8] ROR dest, Count : Rotate left ( into carry as well as into MSB)

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8086 Microprocessor: Logical Instructions
9] SAL/ SHL dest, count : Shift left and append 0s on right.
10] SAR dest, count : Shift right retain a copy of the S‐bit and shift all bits to
right.
11]SHR dest, count : Shift right append 0s on left
12] TEST dest, src: AND logically, updates flags but source and dest are
unchanged.

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8086 Microprocessor: Control Transfer Instructions
1]CALL : Call a procedure
Two types of calls:
i) Near Call ( Intrasegment)
ii) Far Call ( Intersegment)
2] RET : Return execution from procedure
3] JMP : Unconditional Jump to specified destination. Two types near
and Far
4] JA / JNBE: Jump if above / Jump if not below.
The terms above and below are used when we refer to the magnitude of
Unsigned number .
Used normally after CMP.
5] JAE / JNB / JNC
6] JB / JC / JNAE

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8086 Microprocessor: Control Transfer Instructions
7] JBE / JNA
8] JE/ JZ
9] JCXZ: Jump if CX is Zero.
10] JG / JNLE: Jump if Greater /Jump if NOT less than or equal.
The term greater than or less than is used in connection with two
signed numbers.
11] JGE / JNL:
12] JL / JNGE :
13] JLE / JNG :
14]JNE / JNZ :

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8086 Microprocessor: Processor Control Instructions
1] CLC: Clear Carry flag.
2] STC :Set carry Flag
3] CMC :Complement Carry Flag
4] CLD: Clear Direction Flag.
5] STD: Set Direction Flag
6] CLI :Clear Interrupt Flag.
7] STI : Set Interrupt Flag.
8] HLT: Halt Processing.

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8086 Microprocessor: Processor Control Instructions
9] NOP : No Operation
10] ESC: Escape
Executed by Co‐processors and actions are performed according to 6 bit
coding in the instruction.
11] LOCK : Assert bus lock Signal
This is a prefix instruction.
12] WAIT :Wait for test or Interrupt Signal.
Assert wait states.

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8086 Microprocessor: String Control Instructions
1] MOVS/ MOVSB/ MOVSW
Dest string name, src string name
This instuction moves data byte or word from location in DS to location in
ES.
2] REP / REPE / REPZ / REPNE / REPNZ
Repeat string instructions until specified conditions exist.
This is prefix a instruction.
3] CMPS / CMPSB / CMPSW
Compare string bytes or string words.
4] SCAS / SCASB / SCASW
Scan a string byte or string word.
Compares byte in AL or word in AX. String address is to be loaded in DI.
5] STOS / STOSB / STOSW
Store byte or word in a string.
Copies a byte or word in AL or AX to memory location pointed by DI.

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8086 Microprocessor: String Control Instructions
6] LODS / LODSB /LODSW
Load a byte or word in AL or AX
Copies byte or word from memory location pointed by SI into AL or
AX register.

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8086 Microprocessor: Interrupt Control Instructions
1] INT type
2] INTO Interrupt on overflow
3] IRET Interrupt return

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8086 Microprocessor:

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Difference between Minimum and Maximum modes:

CSN221_Lec_27 Computer Architecture and Microprocessor

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