Deep Sleep Mode on Microchip PIC18F and PIC24F MCUs

Editor's Notes

• #2: Welcome to the training module for Deep Sleep Mode on the Microchip PIC18 and PIC24 MCUs.
• #3: This training module will provide an overview of Deep Sleep mode in PIC MCUs.
• #4: During this training module, we may use some acronyms that you haven’t heard before—but, they will become familiar to you as we discuss Deep Sleep and its advantages. RTCC stands for Real-Time Clock/Calendar. This one, you probably know—it is a microcontroller peripheral for keeping time and triggering alarms. DSWDT, or Deep Sleep Watchdog Timer, is a new wake-up source for Deep Sleep applications. ULPWU means Ultra Low-Power Wake-Up. That is a time delay wake-up source that does not require an oscillator. DSBOR, or Deep Sleep Brown-Out Reset, is a low-power voltage monitor that prevents the microcontroller from executing if power drops too low for safe operation.
• #5: On prior PIC ® microcontrollers, sleep mode was provided to allow low-power use by shutting down the processor core. However, SRAM remained powered-on to retain data. To completely stop power consumption, an external switch circuit would be required to cut power to the microcontroller. On new PIC microcontrollers with Deep Sleep capability, both the processor core and SRAM are powered-off to drop power consumption to virtually zero, eliminating the need for an external switch. Certain key peripherals can be configured to remain powered-on, allowing greater flexibility for applications.
• #6: Microchip parts do not need a separate VBATT pin for powering the RTCC. Instead, power is provided through the normal V DD pin, so adding a second battery for powering the RTCC is not necessary. Fewer pins are used, and power levels are so low that applications will not need to add an external switch to cut power to the microcontroller when only timekeeping functionality needs to remain powered.
• #7: Deep Sleep reduces current to minimum levels by turning off power to most of the chip’s SRAM, cutting current consumption to 90% less than traditional Sleep mode. While most SRAM does not retain its data when powered-down, there are two general purpose Deep Sleep registers that will remain powered, allowing some context data to be retained easily. If more data needs to be saved, self-programmed FLASH (or EEPROM memory, if available) is an option. On parts with an internal core voltage regulator, the regulator is shut down during Deep Sleep to conserve power. The voltage regulator needs time to stabilize before the part can wake up from Deep Sleep, therefore Deep Sleep can take typically take 1 to 2 milliseconds to exit on these parts. On devices that do not have a core voltage regulator, wake-up times will be faster, typically 50 µ s. Waking up from Deep Sleep causes a Power-On Reset, so execution will resume at the Reset vector, rather than at the instructions that follow the sleep instruction. Special Function Registers will reset to their Power-On Reset default values. However, certain registers (such as TRIS bits) will not affect device behavior until the Deep Sleep “RELEASE” bit is cleared later, by software.
• #8: Deep Sleep is great for applications that are inactive for long periods of time, such as remote controls, input devices, sensors and thermometers. It is also ideal for applications that need to keep accurate time while consuming minimum power—Deep Sleep supports continuous operation of the Real-Time Clock/Calendar where desired. So what is the big advantage that Deep Sleep provides for these applications? The longer an application can stay in Deep Sleep mode, the lower the average current consumption of your device will be. Normal Sleep mode is recommended for applications that need ultrafast wake up times, complete state retention, or will only be inactive for short periods of time.
• #9: This graph shows a typical low-power application actively running at 4 MHz, with current consumption of 1.5 mA. Not bad, but still enough power consumption to drain a battery within a month or two.
• #10: Say that the application no longer needs to be active, the application can execute a SLEEP or PWRSAV instruction with Deep Sleep enabled to power-down and conserve power.
• #11: While in Deep Sleep, the device is at its lowest power state. With minimal features running, power consumption can be as low as 20 nA. Certain features such as the Real-Time Clock/Calendar, Deep Sleep Watchdog Timer, and Deep Sleep Brown-Out Reset can be configured to remain active, if desired.
• #12: Maximizing the amount of time spent at Deep Sleep current levels will lower power consumption the most. At Deep Sleep current levels, a battery can provide power for years without being depleted.
• #13: Eventually, the application wakes up. On devices without an internal core voltage regulator, wake-up times can be as low as 50 µs. Other devices may require 1 to 2 ms for Deep Sleep wake-up, due to core voltage regulator losses.
• #14: Finally, the application resumes active operation, consuming the most power.
• #15: The progression through each of these states over time defines the average power consumption of the device. While running, the average current drawn by the application would be the full run current of 1.5 mA. By maximizing time in Deep Sleep mode during periods of inactivity, the application can dramatically lower average current.
• #16: Let’s take a look at the microcontroller features that can remain powered during Deep Sleep. The Real-Time Clock/Calendar can be configured to keep time during Deep Sleep. It can even continue to output a seconds clock signal during Deep Sleep. Other I/O pins will maintain their state during Deep Sleep and throughout wake-up until the Deep Sleep “RELEASE” bit is cleared. Deep Sleep registers will retain data over Deep Sleep, even though the rest of SRAM is powered-off. If more data is needed, an application can use the table read/write features to save data to FLASH memory. On some devices, EEPROM memory is also an option. The Deep Sleep Brown-Out Reset feature can be enabled to provide an indication of integrity for the special Deep Sleep and RTCC registers in case power levels dropped too low for safe operation. In addition to these features, several different wake-up sources can be enabled to operate through Deep Sleep. Let’s take a look at them.
• #17: The most common wake-up sources available for Deep Sleep include Interrupt 0, the Deep Sleep Watchdog Timer, a Real-Time Clock/Calendar alarm, and Ultra Low-Power Wake-up. Of course, MCLR Reset can also be used as a wake-up source. However I/O pin states will be lost upon wake-up, instead of waiting for application firmware to clear the Deep Sleep “RELEASE” bit. A power off/power on sequence will also “wake” a device from Deep Sleep, but this will behave exactly like a traditional Power-On Reset. Data stored in special Deep Sleep registers will not be retained over a full power off/on cycle, since V DD voltage is required to maintain these Deep Sleep registers. Like MCLR Reset, power off/power on cycling will not retain I/O pin states.
• #18: Waking from Interrupt 0 happens when an external interrupt edge is detected on the INT0 pin. INT0 can be configured to be active high or active low. The example circuit shown is for an active high INT0 pin. A push button is used to pull the INT0 pin high briefly while a pull-down resistor normally holds the pin at a low state. To reduce switch bounce sensitivity, a capacitor can be added to low pass filter the signal.
• #19: The Deep Sleep Watchdog Timer provides another wake-up source for Deep Sleep. It is not the same module as the software Watchdog Timer you might be familiar with during active Run mode. It is a separate module specific to Deep Sleep. The Deep Sleep Watchdog Timer requires a clock source to keep track of how long to stay in Deep Sleep. Two options are available: an internal low-power RC oscillator or an external secondary oscillator. The DSWDT should always be run from the internal RC oscillator if robustness is needed, allowing an application to wake up even if a crystal failure has occurred. Configuration bits specify how long the device should stay in Deep Sleep before timing out and waking the device. 16 different timeout settings are available. If more granularity is needed, a Real-Time Clock/Calendar alarm should be used instead.
• #20: The Real-Time Clock/Calendar can keep a running clock of the current date and time, plus it has an alarm feature that can be used to wake the microcontroller from Deep Sleep at a specified date/time. Unlike the Deep Sleep Watchdog Timer, granularity is not restricted to 16 options; any date/time can be used. The internal low-power RC oscillator or the secondary oscillator can be used for a clock source, just like the Deep Sleep Watchdog Timer. If both the RTCC and Deep Sleep Watchdog Timer are going to be used, and robustness is not a key concern, the same clock source can be used so that power isn’t wasted keeping two oscillator circuits running. During Deep Sleep, I/O pins are generally held constant in their last configured state. However, the RTCC can be configured to output an alarm pulse or seconds clock output on the RTCC pin, even while the microcontroller is in Deep Sleep. This pulse could be used to continuously blink an indicator on a clock read out, for example.
• #21: The RTCC and DSWDT need a clock source to operate. When using the 31 kHz Internal RC oscillator as a clock source, no external circuitry is required. For more timing accuracy, an external 32.768 kHz crystal can be connected to the microcontroller’s secondary oscillator pins (as shown in the example circuit). To achieve low-power consumption for Deep Sleep applications, the secondary oscillator has very low drive levels. The downside is increased sensitivity to rapidly changing signals in close proximity. Locate the crystal and capacitors as close to the microcontroller as possible and avoid routing signals, other than V SS and V DD , near the oscillator circuit.
• #22: The Ultra Low-Power Wake-Up module, available on some Deep Sleep devices, allows your device to go into Deep Sleep for a certain period of time and wake up, without using an oscillator. Because ULPWU is clockless, it consumes less power than wake-up sources that need an oscillator. Instead, ULPWU uses a slowly discharging capacitor voltage to trip a wake-up after a period of time has passed. Let’s look at how this works.
• #23: Before entering Deep Sleep, firmware will configure RA0 as an output pin and drive it high to V DD . The I/O pin will charge the capacitor to V DD voltage. Once the capacitor is charged, firmware will let the Ultra Low-Power Wake-Up module take control of the RA0 pin and Deep Sleep mode is entered. During Deep Sleep, the Ultra Low-Power Wake-Up module will provide a small pull-down current to the pin, allowing the capacitor to slowly discharge over time. When the voltage of the capacitor finally drops to the I/O pin’s trip point (nominally one-half volt), the device will wake up from Deep Sleep.
• #24: When the microcontroller first powers on or wakes up from Deep Sleep, it will start executing code from the Reset vector. If the RTCC is using the secondary oscillator to keep track of time, the secondary oscillator should be enabled before clearing the Deep Sleep release bit. This allows the RTCC to continue operating continuously, without losing time. Deep Sleep hardware will keep the RTCC and secondary oscillator running throughout Deep Sleep and wake-up. Applications that aren’t using the real-time clock can skip this step. Next, firmware can check the Deep Sleep wake-up status flag to see if we are powering on for the first time or if we are coming out of Deep Sleep. If coming out of Deep Sleep, firmware can read data from the Deep Sleep registers to determine which wake-up source was triggered and restore application context. Waking up from Deep Sleep causes a Power-On Reset; which, in turn, resets most registers back to their POR default values. However, immediately applying these default settings could be undesirable in a Deep Sleep application, so a special Deep Sleep feature prevents certain register changes from being applied during start-up. Without this feature, I/O pins would all revert to being tri-stated and the secondary oscillator would be disabled immediately on wake-up. The end result would be losing track of time and losing control over external circuitry. At this point, application-specific tasks can be carried out, such as reading new data and outputting resulting data. When the application is finished, it should save its context information (if any) out to the special Deep Sleep registers and/or nonvolatile memory. Instead, application firmware has a chance after wake-up to initialize values other than the power-on defaults. Afterwards, firmware will manually clear the special Deep Sleep RELEASE state bit to allow register values to actively drive the hardware once again. Finally, Deep Sleep is re-entered and the process can begin again when the next wake-up event occurs.
• #25: Here is a table showing some of the PIC ® microcontrollers featuring Deep Sleep. The biggest difference between the parts listed is the core voltage regulator. The PIC24F16KA102 does not use a core voltage regulator, the entire device runs at full V DD voltage. In contrast, the other devices use a separate core voltage, lowering power use of the processor core logic. Deep Sleep mode on these devices turns off the processor core by disabling the internal core voltage regulator. For PIC18, the LF variants of these devices lack the internal core voltage regulator; consequently, Deep Sleep mode is not available on LF parts. For PIC24, there is a pin to enable or disable the voltage regulator and it must be enabled for Deep Sleep mode. Bare Deep Sleep mode, with no extra features enabled, draws between 20 and 24 nA. When adding the Real-Time Clock/Calendar, power consumption during Deep Sleep is generally increased to 500 nA, due to power spent on the secondary oscillator. This represents industry-leading power consumption for ultra low-power and ensures battery operation for years with the RTCC running. The PIC24F16KA102 can quickly wake up within 50 µ s. Devices that use a core voltage regulator have longer wake-up times of around 1 to 2 ms to allow the core voltage regulator to stabilize before executing code. Devices using an internal core voltage regulator require an external filter capacitor for regulator stability. Because the core voltage is turned off during Deep Sleep, this filter capacitor will end up discharging during Deep Sleep mode. Energy is used each cycle for recharging the capacitor, creating a break-even point where traditional Sleep mode may provide better efficiency for applications with short time periods between wake-up events (below 20 seconds). All devices provide two general purpose Deep Sleep registers for quickly saving context information through Deep Sleep. And, self-programmed FLASH memory is available if additional space is required. The PIC24F16KA102 adds EEPROM memory as an additional option for storing context data. Finally, the PIC18F46J50 and PIC18F46J11 parts support the Ultra Low-Power Wake-Up feature for Deep Sleep. Remember this feature enables the device to go into Deep Sleep for a certain period of time and wake up, without using an oscillator.
• #26: Using Deep Sleep allows applications that are inactive for long periods of time to dramatically lower average power consumption, and eliminates the need for an external switch to cut microcontroller power. Deep Sleep turns off the processor core, most peripherals, and SRAM to reduce power consumption to virtually zero. However, some features can be configured to remain powered, such as the RTCC to allow for timekeeping. Deep Sleep has several wake-up sources available, including Interrupt 0, the Deep Sleep Watchdog Timer, an RTCC alarm, and Ultra Low-Power Wake-Up. While SRAM is powered-down, a few special Deep Sleep registers remain available for saving context information through Deep Sleep.
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