Digital Design Session 11

Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2
Session 11: Focus
 Full Adder-subtractor Circuit
◦ Carry Propagation Delay
◦ Look-ahead Carry Implementation
◦ Advantages and disadvantages

Full Adder-Subtractor

Full Adder-Subtractor
 Subtraction of two binary numbers can be accomplished by
adding 2’s complement of the subtrahend to the minuend
 And disregarding the final carry, if any.
 If the MSB bit in the result of addition is a ‘0’, then the result
of addition is the correct answer
 If the MSB bit is a ‘1’, this implies that the answer has a
negative sign.
 The true magnitude in this case is given by 2’s complement of
the result of addition
 Full adders can be used to perform subtraction provided
 Additional hardware is there to generate 2’s complement
of the subtrahend and
 Disregard the final carry or overflow

Adder-Subtractor Circuit
Note: This parallel adder is also called Ripple Carry Adder

Carry Propagation

Gate Delays
 Timing diagram above shows gate delay graphically
 When inputs to gate change, outputs from the gate don’t change
instantaneously (they get delayed in the range of nano seconds)
◦ This delay is known as “gate” or “propagation” delay
 The exact amount of gate delay depends on the
◦ Technology used to build the gates (TTL, CMOS, etc.)
◦ The technology node used to build the gate (22 nm, 14 nm, etc.)
7
TTL: Transistor-Transistor Logic, CMOS: Complementary Metal Oxide Semiconductor
Output signal
transition based on
the input level
changes

Multiple Gate Delays
 What is the delay experienced by the signal G2 which
depends on the input signal A?
 The amount of delay experienced by the output signals
depend on
◦ The type of gates in the path (AND, OR, etc.)
◦ Particular combination of signal transitions, etc.
◦ More number of gates the signal needs to pass through, it
experiences more delay in general
40 ns

n-bit Ripple Carry Adder
 By cascading full adders, carry “ripples” from least
significant bit toward most significant bit
◦ Critical path becomes input to FA0 to output of FAn
◦ Critical path is the path which experiences the maximum
delay in a circuit

Carry Propagation Delay
 From the FA circuit, Ci+1 is delayed by two levels of gates
once Ci is available at the input
FA: Full Adder
FA: Full Adder Circuit

Carry Propagation Delay .. Contd.
 What is the delay experienced by C5?
 From the FA circuit, C5 will experience total of 8 gate delays,
with two gate delay at every stage from C1 to C5
 This delay will have more impact when more number of bits
are getting added
 Especially when the numbers to be added (A and B) are all
already available simultaneously

Solution: Look-ahead Carry (Fast adder)
 This Hardware solution attempts to look ahead and generate
the carry based on the input numbers (A and B) to be added
 Instead of waiting for the addition of lower order bits to be
completed
 Waiting for the carry bits to ripple through full adders from
lower order bits to higher order bits
 In order to explain the concept, let us define two new binary
variables
 Pi called CARRY PROPAGATE and
 Gi called CARRY GENERATE
 Gi generates carry whenever Ai and Bi are both 1s (AND)
 Pi is instrumental in the propagation of the Ci to Ci+1

Solution: Look-ahead Carry
 The Boolean Expressions of the implementation are:
From the expressions for C2, C3 and C4 it is clear that C4 does not wait for C3 and C2
to propagate. Similarly, C3 does not wait for C2 to propagate

4-bit Adder Circuit (Ripple carry)

Implementation: Look-ahead Carry
Hardware implementation of these expressions above is the look-ahead carry generator

Look-ahead Carry
Advantages:
 The parallel addition of multiple bits can happen with a fixed
amount gate delays
 The Look-ahead carry generator circuit has the same two gate
level delays for generating the carry for all the bits
 After the Pi and Gi are available with fixed one gate delay
 All the digits of A and B are assumed to be available at the beginning of
summation
Disadvantages:
 Its implementation takes up more gates and interconnections,
taking up more space and power

Session 11: Summary
 Full Adder-subtractor Circuit
◦ Carry Propagation Delay
◦ Look-ahead Carry Implementation
◦ Advantages and disadvantages

References
Ref 1 Ref 2

Digital Design Session 11

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