Digital Design Session 16
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This document discusses SR latches using NOR gates. It describes the logic diagram and truth table of an SR latch, showing it is an active high circuit where a 1 on the R input resets Q to 0 and a 1 on the S input sets Q to 1. Simultaneously having both inputs at 1 is forbidden as it causes an unpredictable state. SR latches are level sensitive storage elements unlike flip-flops, so they cannot be used in synchronous circuits but are the building blocks for flip-flops. The document explains how the NOR-based SR latch works and maintains its state while avoiding the forbidden state of both inputs being 1 at the same time.
Digital Design Session 16
- 1. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com
- 2. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 2 Session 16: Focus Storage Elements ◦ SR-Latches NOR based
- 3. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com Storage Elements SR Latches – With NOR Gates
- 4. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 4 SR-Latches with NOR Gates Logic Diagram Function Table Active HIGH circuit Active HIGH here corresponds to the control inputs (R & S) When R = 1, Q is Reset to 0 When S = 1, Q is set to 1 Always Set means setting a value to ONE Always Reset means resetting a value to ZERO It is forbidden because both Set (1) and Reset (1) commands should not be given simultaneously
- 5. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 5 Storage Elements – Latches/Flip-flops Storage element in a digital circuit can maintain a binary state indefinitely As long as power is delivered to the circuit And until directed by an input signal to switch states Storage elements that operate with signal levels (rather than signal transitions or clock edges) are referred to as latches Those controlled by a clock transitions are flip-flops Latches are said to be level sensitive devices Flip-flops are edge-sensitive devices
- 6. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 6 SR-Latches Since SR-Latches are level-sensitive and is not operated with clocks, they cannot be used in synchronous sequential circuits Since SR-Latches are the building blocks for Flip-flops We study them here
- 7. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 7 SR-Latches (NOR) Explained However, when both inputs are equal to 1 at the same time, a condition in which both outputs are equal to 0 occurs Rather than being mutually complementary If both inputs are then switched to 0 simultaneously, The device will enter an unpredictable or undefined state or a meta-stable state In practical applications, setting both inputs to 1 is forbidden Under normal conditions, both inputs of the latch remain at 0 unless the state has to be changed When Q = 0 and Q’ = 1, it is in the reset state When Q = 1 and Q’ = 0, it is in the set state Outputs Q and Q’ are normally the complement of each other Active HIGH circuit
- 8. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 8 SR-Latches (NOR) Explained … contd. Thus, when both inputs S and R are equal to 0, the latch can be in either in the set (Q = 1) or in the reset (Q = 0) state Depending on which input (S or R) was most recently a 1 In normal operation, having both inputs S and R at 1 is avoided by making sure that 1’s are not applied to both inputs simultaneously Which is a forbidden state
- 9. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 9 Session 16: Summary Storage Elements ◦ SR-Latches NOR Based
- 10. Digital Design – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com 10 References Ref 1 Ref 2