Digital Logic Design Lec13 Counters.pdf
- 1. CSE231 – Digital Logic Design Counters
- 2. 2 Asynchronous Counters (aka. Ripple Counters) Counters
- 3. 3 4-bit (up) Counter ⚫ Let each bit in the counter be represented by the output of a flip-flop. Count A3 A2 A1 A0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 Count A3 A2 A1 A0 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 0 0 0 0 0
- 4. 4 4-bit (up) Counter: T Flip-Flops Asynchronous Counter Counter does not use a common clock.
- 5. 5 4-bit (up) Counter: D Flip-Flops Asynchronous Counter Counter does not use a common clock.
- 7. 7 4-bit (up) Counter ⚫ As before, let each bit in the counter be represented by the output of a flip-flop. Count Q3 Q2 Q1 Q0 0 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 Count Q3 Q2 Q1 Q0 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 0 0 0 0 0
- 8. 8 4-bit (up) Counter: JK Flip-Flops Synchronous Counter Counter uses a common clock.
- 9. 9 Binary Counter with Parallel Load Synchronous Counters
- 10. 10 4-bit Counter with Parallel Load
- 12. 12 BCD (Decimal) Counter (aka. Modulo-10 Counter) Counters
- 13. 13 BCD Counter: State Diagram
- 14. 14 BCD Counter: JK Flip-Flops Asynchronous Counter
- 15. 15 BCD Counter: D Flip-Flops Synchronous Counter
- 16. 16 Up / Down Counter Synchronous Counters
- 17. 17 4-bit Up / Down Counter