ECE6003-Module_1.pptx electronics and communication

Low Power VLSI Design
(ECE6003)
Dr. Dharmesh K Srivastava,
Associate Professor,
Department of Electronics and Communication (ECE)
Engineering
Presidency University, Bangaluru.

Low Power VLSI Design 2
Course Content
Module 1: Device & Technology Impact on Low Power
Topics: Introduction: Sources of Power dissipation: Dynamic Power Dissipation, Short
Circuit Power, Switching Power Glitching Power. Emerging Low power approaches.
Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, Transistor
sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device
innovation., Static Power Dissipation, Degrees of Freedom, Supply Voltage Scaling
Approaches: Device feature size scaling, Multi-Vdd Circuits
Module 2: Power analysis
Topics: Simulation Power analysis: SPICE circuit simulators, gate level logic simulation,
capacitive power estimation, static state power, gate level capacitance estimation,
architecture level analysis, data correlation analysis in DSP systems, Monte Carlo simulation.
Probabilistic power analysis: Random logic signals, probability & frequency, probabilistic
power analysis techniques, signal entropy.

Course Content
Module 3: Low Power Design at circuit and logic level
Topics: Low Power Design Circuit Level: Transistor and gate sizing, network restructuring
and Reorganization. Special Flip Flops & Latches design, high capacitance nodes, low power
digital cells library.
Logic level: Gate reorganization, signal gating, logic encoding, state machine encoding, pre-
computation logic.
Module 4: Leakage Power minimization Approaches, Adiabatic switching, Memory
Design
Topics: Low power Architecture & Systems: Power & performance management,
switching activity reduction, parallel architecture with voltage reduction, flow graph
transformation, low power arithmetic components. Variable-threshold-voltage CMOS
(VTCMOS) approach, Multi-threshold-voltage CMOS (MTCMOS) approach, Power gating,
Low power Clock Distribution, CAD tools for low power synthesis
Special Techniques: Power Reduction in Clock networks, CMOS Floating Node, Low power
Bus Delay balancing, and Low Power Techniques for SRAM.

Introduction
 Due to integration of components increased the power comes in limelight
 It is much important that handheld devices must possess
 For better performance
 For long run time (Battery time)
Need for Low Power Circuit Design

 Power Dissipation: The rate of energy which is taken from the
source and converted into heat.
Definition

 Static power dissipation
- Due to leakage current
 Dynamic power dissipation.
- Due to switching activities of transistor
Types of Power Dissipation

Low Power Strategies

Three parts that we can perform low power
techniques to reduce power dissipation.
- Voltage
- Physical Capacitance
- Switching activity
Low Power Design Space

 Voltage reduction offers an effective means of power reduction
 A factor of two reduction in supply voltage yields a factor of four
decreases in power consumption.
 But the performance is also getting reduced.
 To avoid the above stated problem,
- Threshold voltage should be scaled down
Supply voltage reduction

 Dynamic power consumption depends linearly on the physical
capacitance being switched
 So minimizing capacitance offers another technique for
minimizing power consumption
 The capacitor can be kept as small by
- Minimum logic
- Smaller devices
- Fewer and Shorter wires
Physical Capacitance

 There are two components to switching activity:
- which determines the average periodicity of data arrivals.
- E(sw) which determines how many transitions each
arrival will generate.
 Switching activity is reduced by
- Selecting proper algorithms architecture optimization,
- Proper choice of logic topology
- Logic level optimization which results in less power
Switching Activity

Low Power techniques

Low Power Techniques
 Clock Gating
- To reducing dynamic power dissipation.
- works by taking the enable conditions attached to registers, and
uses them to gate the clocks.
 Power Gating
- High Vt sleep transistors which cut off VDD from a circuit block when
the block is not switching.
- Also known as MTCMOS- Multi-Threshold CMOS.

Calculation of Switching Activity
 Input Pattern Dependence
 Logic Function
 Logic Style
 Circuit Structure

Power Minimization Techniques
 Reducing chip and package capacitance
- Process development such as SOI with partially or fully depleted wells.
- Advanced interconnect substrates such as Multi-Chip Modules(MCM)
 Scaling the supply voltage
- Very effective.
- But often requires process technologies.
 Employing better design techniques
- The investment to reduce power by design in relatively small
 Using power management strategies
- Various static and dynamic power management techniques

CAD Methodologies and Techniques
 Low power VLSI design can be achieved at various levels of the design process
- System Design.
- inactive hardware modules maybe automatically turned off to save power.
- Behavioral Synthesis
- The behavioral synthesis process consists of three steps:
- Allocation
- Assignment and scheduling
- These steps determine how many instances of each resource are needed.
- Logic Synthesis
- Physical Design
-

Low power VLSI is needed
 Increasing of handheld devices
 Increasing of complex device structure
 Long battery life
 Long device life

Need for Low Power Circuit Design:
 The increasing prominence of portable systems and the need to limit power
consumption in very-high density ULSI chips have led to rapid and
innovative developments in low-power design during the recent years.
- Portable applications requiring low power dissipation and high throughput,
such as notebook computers, portable communication devices and personal
digital assistants (PDAs).
-.In most of these cases, the requirements of low power consumption must
be met along with equally demanding goals of high chip density and high
throughput.
- Hence, low-power design of digital integrated circuits has emerged as a
very active and rapidly developing field of CMOS design.

 The limited battery lifetime typically imposes very strict demands on the
overall power consumption of the portable system.
- New rechargeable battery types such as Nickel Metal Hydride (NiMH) are
being developed with higher energy capacity than that of the conventional
Nickel-Cadmium (NiCd) batteries, revolutionary increase of the energy capacity
is not expected in the near future.
- The energy density (amount of energy stored per unit weight) offered by
the new battery technologies (e.g., NiMH) is about 30 Watt-hour/pound, which
is still low in view of the expanding applications of portable systems.
-Therefore, reducing the power dissipation of integrated circuits through
design improvements is a major challenge in portable systems design.

 The need for low-power design is also becoming a major issue in high-
performance digital systems, such as microprocessors, digital signal
processors (DSPs) and other applications.
- Increasing chip density and higher operating speed lead to the design of
very complex chips with high clock frequencies.
-If the clock frequency of the chip increases then the power dissipation of
the chip, and thus, the temperature, increase linearly. Since the dissipated heat
must be removed effectively to keep the chip temperature at an acceptable
level, the cost of packaging, cooling and heat removal becomes a significant
factor.

 ULSI reliability is yet another concern which points to the need for low-
power design.
- There is a close correlation between the peak power dissipation of digital
circuits and reliability problems such as electro migration and hot-carrier
induced device degradation.
-Also, the thermal stress caused by heat dissipation on chip is a major
reliability concern. Consequently, the reduction of power consumption is also
crucial for reliability enhancement..

Low Power Design Methodologies:
 The methodologies which are used to achieve low power consumption in digital
systems span a wide range,
 from device/process level to algorithm level.
 Device characteristics (e.g., threshold voltage), device geometries and interconnect
properties are significant factors in lowering the power consumption.
 Circuit-level measures such as the proper choice of circuit design styles, reduction of
the voltage swing and clocking strategies can be used to reduce power dissipation at
the transistor level.
 Architecture-level measures include smart power management of various system
blocks, utilization of pipelining and parallelism, and design of bus structures.
 Finally, the power consumed by the system can be reduced by a proper selection of
the data processing algorithms, specifically to minimize the number of switching
events for a given task.

Sources of Power Dissipation
 The average power dissipation in conventional CMOS digital circuits can
be classified into three main components, namely,
(1) The short-circuit power dissipation
(2) The dynamic (switching) power dissipation and
(3) The leakage power dissipation.
If the system or chip includes circuits other than conventional CMOS gates
that have continuous current paths between the power supply and the
ground, a fourth (static) power component should also be considered

Short-circuit power dissipation
 CMOS Inverter
-if a CMOS inverter (or a logic gate) is driven with input voltage waveforms
with finite rise and fall times, both the nMOS and the pMOS transistors in
the circuit may conduct simultaneously for a short amount of time during
switching, forming a direct current path between the power supply and the
ground, as shown in Fig.

 Short-circuit current component is the current component which passes through both
the nMOS and the pMOS devices during switching. It does not contribute to the
charging of the capacitances in the circuit.
 This component is particularly powerful if the output load capacitance is small, and/or
if the input signals rise and fall times are large, as shown in Fig.
 The nMOS transistor in the circuit starts conducting when the rising input voltage
exceeds the threshold voltage VT,n.
 The pMOS transistor remains on until the input reaches the voltage level (VDD -
|VT,p|). Thus, there is a time window during which both transistors are turned on. As
the output capacitance is discharged through the nMOS transistor, the output voltage
starts to fall.
 The drain-to-source voltage drop of the pMOS transistor becomes nonzero, which
allows the pMOS transistor to conduct as well. The short circuit current is terminated
when the input voltage transition is completed and the pMOS transistor is turned off.
A similar event is responsible for the short- circuit current component during the
falling input transition, when the output voltage starts rising while both transistors are
on.

 For a simple analysis consider a symmetric CMOS inverter with k = kn = kp and VT =
VT,n = |VT,p|, and with a very small capacitive load. If the inverter is driven with an
input voltage waveform with equal rise and fall times (t = trise = tfall), it can be
derived that the time averaged short circuit current drawn from the power supply is
Hence, the short-circuit power dissipation becomes
The short-circuit power dissipation is linearly proportional to the input signal rise
and fall times, and also to the transconductance of the transistors. Hence, reducing
the input transition times will obviously decrease the short circuit current
component.

Now consider the same CMOS inverter with a larger output load capacitance and
smaller input transition times.
- During the rising input transition, the output voltage will effectively remain at VDD
until the input voltage completes its swing and the output will start to drop only
after the input has reached its final value.
- Although both the nMOS and the pMOS transistors are on simultaneously during
the transition, the pMOS transistor cannot conduct a significant amount of current
since the voltage drop between its source and drain terminals is approximately equal
to zero.
- Similarly, the output voltage will remain approximately equal to 0 V during a falling
input transition and it will start to rise only after the input voltage completes its swing.
Again, both transistors will be on simultaneously during the input voltage transition,
but the nMOS transistor will not be able to conduct a significant amount of current
since its drain-to-source voltage is approximately equal to zero.

 Note that the peak value of the supply current to charge up the output load
capacitance is larger in this case. The reason for this is that the pMOS transistor
remains in saturation during the entire input transition, as opposed to the previous
case where the transistor leaves the saturation region before the input transition is
completed.
- The short-circuit power dissipation can be reduced by making the output voltage
transition times larger and/or by making the input voltage transition times smaller. Yet
this goal should be balanced carefully against other performance goals such as
propagation delay, and the reduction of the short-circuit current should be considered
as one of the many design requirements that must satisfied by the designer.

Dynamic (Switching) Power Dissipation
• Switching Power Dissipation represents the power dissipation during a
switching event. This means that the output node voltage of a CMOS logic gate
makes a power consuming transition.
- In digital CMOS circuits, dynamic
power is dissipated when energy is drawn
from the power supply to charge up the
output node capacitance.
- During the charge-up phase, the output
node voltage typically makes a full
transition from 0 to VDD, and the energy
used for the transition is relatively
independent of the function performed by
the circuit.

The total capacitive load at the output of the NOR gate consists of
(1) The output capacitance of the gate itself
(2) The total interconnect capacitance, and
(3) The input capacitances of the driven gates.
Output capacitance:
The output capacitance of the gate consists mainly of the junction parasitic
capacitances, which are due to the drain diffusion regions of the MOS
transistors in the circuit.
The important feature to highlight here is that the amount of capacitance is
approximately a linear function of the junction area. So, the size of the total
drain diffusion area determines the amount of parasitic capacitance.

Total interconnect capacitance:
The interconnect lines between the gates contribute to the total interconnect capacitance.
In sub-micron technologies, the interconnect capacitance can become the dominant component,
compared to the transistor-related capacitances.
Input capacitances:
The input capacitances are mainly due
to gate oxide capacitances of the
transistors connected to the input
terminal. Again, the amount of the gate
oxide capacitance is determined
primarily by the gate area of each
transistor.
Generic representation of a CMOS logic gate

The average power dissipation of the CMOS logic gate, driven by a periodic input voltage
waveform with ideally zero rise- and fall-times, can be calculated from the energy required to
charge up the output node to VDD and charge down the total output load capacitance
to ground level.
Simplifying this integral gives the well-known expression for the average dynamic (switching)
power consumption in CMOS logic circuits.
• The average dynamic power dissipation is proportional to the
square of the power supply voltage; hence, any reduction of
VDD will significantly reduce the power consumption.
• Another way to limit the dynamic power dissipation of a
CMOS logic gate is to reduce the amount of switched
capacitance at the output.

Effect of reducing the power supply voltage VDD on switching power dissipation:
The reduction of power supply voltage significantly reduces the dynamic power
dissipation, the expected design trade-off is the increase of delay.
The propagation delay expressions for the CMOS inverter circuit is,
Assuming that the power supply voltage is being scaled down while all other
variables are kept constant, it can be seen that the propagation delay time will
increase.

If the circuit is always operated at the maximum frequency allowed by its
propagation delay, on the other hand, the number of switching events per unit time
(i.e., the operating frequency) will obviously drop as the propagation delay becomes
larger with the reduction of the power supply voltage.
The net result is that the dependence of switching power dissipation on the power
supply voltage becomes stronger than a simple quadratic relationship.
• The analysis of switching power dissipation presented above is based on the
assumption that the output node of a CMOS gate faces one power-consuming
transition (0-to-VDD transition) in each clock cycle.
• This assumption, however, is not always correct; the node transition rate can
be smaller than the clock rate, depending on the circuit topology, logic style
and the input signal statistics.

To better represent this behavior, The node transition factor αT is added, which is the
effective number of power-consuming voltage transitions experienced per clock cycle.
Then, the average switching power dissipation becomes
• There is a parasitic node capacitance associated with each internal node, these
internal transitions contribute to the overall power dissipation of the circuit.
• In fact, an internal node may face several transitions while the output node
voltage of the circuit remains unchanged, as illustrated in below Fig.

In the most general case, the internal node voltage transitions can also be
partial transitions, i.e., the node voltage swing may be only Vi which is
smaller than the full voltage swing of VDD. Taking this possibility into account,
the generalized expression for the average switching power dissipation can be
written as

Leakage Power Dissipation
The nMOS and pMOS transistors used in a CMOS logic gate generally have
nonzero reverse leakage and sub threshold currents.
In a CMOS VLSI chip containing a very large number of transistors, these currents
can contribute to the overall power dissipation even when the transistors are not
undergoing any switching event.
The magnitude of the leakage currents is determined mainly by the processing
parameters.
Two main leakage current components found in a MOSFET are
(1) Reverse diode leakage current
(2) Sub threshold leakage current

Reverse diode leakage current:
The reverse diode leakage occurs when the pn-junction between the drain and the
bulk of the transistor is reversely biased. The reverse-biased drain junction then conducts a
reverse saturation current which is eventually drawn from the power supply.

Reverse diode leakage current:
Consider a CMOS inverter with a high input voltage
NMOS ”ON” and PMOS “ OFF”
• There will be a reverse potential difference of VDD between its drain and
the n-well, causing a diode leakage through the drain junction.
• A similar situation can be observed when the input voltage is equal to zero, and the
output voltage is charged up to VDD through the pMOS transistor.
The magnitude of the reverse leakage current of a pn-junction is given by the
following expression

Subthreshold leakage current:
Subthreshold current- due to carrier diffusion between the source and the drain
region of the transistor in weak inversion
The sub threshold leakage current also occurs when there is no switching activity in the circuit,
and this component must be carefully considered for estimating the total power dissipation in the
stand-by operation mode.

Subthreshold leakage current:
• One relatively simple measure to limit the subthreshold current
component is to avoid very low threshold voltages, so that the VGS of
the nMOS transistor remains safely below VT,n
• when the input is logic zero, and the |VGS| of the pMOS transistor
remains safely below |VT,p| when the input is logic one.

GLITCH POWER DISSIPATION:
The glitching power dissipation occurs due to finite delay. This Power dissipated in
the intermediate transitions during the evaluation of the logic function of the circuit.
In multi-level logic circuits, the finite propagation delay from one logic block to the
next can cause spurious signal transitions, or glitches as a result of critical races or
dynamic hazards.

GLITCH POWER DISSIPATION:
Glitches occur primarily due to a mismatch or imbalance in the path lengths in
the logic network. Such a mismatch in path length results in a mismatch of signal
timing with respect to the primary inputs

Short-Channel Effects:
Short-Channel Devices:
A MOSFET device is considered to be short when the channel length is the same order
of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction. As the
channel length L is reduced to increase both the operation speed and the number of
components per chip, the so-called short-channel effects arise.
Short-Channel Effects
The short-channel effects are attributed to two physical phenomena:
1. The limitation imposed on electron drift characteristics in the channel,
2. The modification of the threshold voltage due to the shortening channel length.
In particular five different short-channel effects can be distinguished:
1. Drain-induced barrier lowering and punch through
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electron effect

Drain-induced barrier lowering :
The expressions for the drain and source junction widths are:
and
• There exists a potential barrier between source and drain which is to be lowered
by applying gate voltage. In short channel devices in addition to the gate voltage,
drain voltage also has a significant effect on reducing this barrier.
• As the source & drain get closer, they become electrostatically coupled, so that
the drain bias can affect the potential barrier to carrier flow at the source junction.
• As a result, sub threshold current increases.

Drain-induced barrier lowering and punch through:
As the drain depletion region continues to increase with the bias, it can actually interact with
the source to channel junction and hence lowers the potential barrier. This problem is known
as Drain Induced Barrier Lowering (DIBL).
• When the source junction barrier is reduced, electrons are easily injected into the
channel and the gate voltage has no longer any control over the drain current.
• In long channel devices, the source and drain are separated far enough that their
depletion regions have no effect on the potential or field pattern in most part of
the device.
• Hence, for such devices, the threshold voltage is virtually independent of the
channel length and drain bias. DIBL is enhanced at high drain voltages and
shorter channel lengths.

Punch through:
When the drain is at high enough voltage with respect to the source, the depletion
region around the drain may extend to the source, causing current to flow
irrespective of gate voltage (i.e. even if gate voltage is zero).
This is known as Subsurface Punch through as it takes place away from the gate
oxide and substrate interface. So when channel length L decreases (i.e. short channel
length case), punch through voltage rapidly decreases.
 Short-channel devices-separation
between the depletion region
boundaries decreases.

Surface scattering:
As the channel length becomes smaller due to the lateral extension of the depletion
layer into the channel region, the longitudinal electric field component εy increases,
and the surface mobility becomes field-dependent.
Since the carrier transport in a MOSFET is
confined within the narrow inversion layer,
and the surface scattering (that is the
collisions suffered by the electrons that are
accelerated toward the interface by εx)
causes reduction of the mobility, the
electrons move with great difficulty parallel
to the interface, so that the average surface
mobility, even for small values of εy, is
about half as much as that of the bulk
mobility.

Velocity saturation:
The performance short-channel devices are also affected by velocity saturation,
which reduces the transconductance in the saturation mode. At low εy, the electron
drift velocity vde in the channel varies linearly with the electric field intensity.
However, as εy increases above 104V/cm, the drift velocity tends to increase more
slowly, and approaches a saturation value of vde(sat)=107cm/s around εy =105 V/cm at
300 K.
Impact ionization:
Another undesirable short-channel effect, especially in NMOS, occurs due to the
high velocity of electrons in presence of high longitudinal fields that can generate
electron-hole (e-h) pairs by impact ionization, that is, by impacting on silicon atoms
and ionizing them.

Impact ionization:
It happens as follow: normally, most of the electrons are attracted by the drain, while
the holes enter the substrate to form part of the parasitic substrate current. Moreover,
the region between the source and the drain can act like the base of an npn transistor,
with the source playing the role of the emitter and the drain that of the collector.
The holes are collected by the source, and the corresponding hole current creates a voltage drop
in the substrate material of the order of 0.6V, the normally reversed-biased substrate-source pn
junction will conduct appreciably.
Then electrons can be injected from the source to the substrate, similar to the injection of
electrons from the emitter to the base. They can gain enough energy as they travel toward the
drain to create new electron hole pairs. The situation can worsen if some electrons generated
due to high fields escape the drain field to travel into the substrate, thereby
affecting other devices on a chip.

Hot electron effect:
Another problem, related to high electric fields, is caused by so-called hot electrons. These
high energy electrons can enter the oxide, where they can be trapped, giving rise to oxide
charging that can accumulate with time and degrade the device performance by increasing
VT and affect adversely the gate’s control on the drain current.

Hierarchy of Limits
Fundamental
Material
Systems
Device and Circuit

67
Fundamental Limits
• The limit from thermodynamic principles results
from the need to have, at any node with an equivalent
resistor R to the ground, the signal power Ps exceed
the available noise power Pavail
• The quantum theoretic limit on low power comes
from the Heisenberg uncertainty principle. In order to
be able to measure the effect of a switching transition
of duration Δt, it must involve an energy greater than
h/Δt:
• P ≧ h/ (Δt)2 where h is the Planck’s constant

68
• Finally the fundamental limit based on
electromagnetic theory results in the velocity
of propagation of a high-speed pulse on an
interconnect to be always less than the speed
of light in free space, c0:
• L/τ≦ c0 where L is the length of the
interconnect and τ is the interconnect transit
time

69
Material Limits
• The attributes of a semiconductor material that
determine the properties of a device built with
the material are
• Carrier mobility μ
• Carrier saturation velocity σs
• Self-ionizing electric field strength Ec
• Thermal conductivity K

71
System Limits
• The architecture of the chip
• The power-delay product of the CMOS
technology used to implement the chip
• The heat removal capacity of the chip package
• The clock frequency
• Its physical size

70
• Consider an SOI structure by surrounding the
above generic device in a hemispherical shell of
SiO2 of radius ri, indicating a two-order-of-
magnitude reduction in thermal conductivity
• The response time of the global interconnect
circuit is
τ= (2.3 Rtr + Rint) Cint where Rtr is the output
resistance of the driving transistor and Rint and
Cint are the total resistance and capacitance,
respectively, of the global interconnect.

Transistor and Gate Sizing
• At the circuit level, transistors are the basic building blocks and a
digital circuit can be viewed as a network of transistors with some
additional parasitic elements such as capacitors and resistors
• Transistor sizes are the most important factor affecting the quality
ie area, and power dissipation of a circuit
• Some studies assume that the sizing problem is a convex function
and linear programming can be used to solve the sizing problem
optimally
• Another problem encountered in cell based design is gate sizing
• The goal is to choose a set of gate sizes that best fits the design
constraints

Sizing an Inverter Chain
• The simplest transistor sizing problem is that of an inverter
chain
• The general design problem is to drive a large capacitive load
without excessive delay, area and power requirements
• A large inverter is required to drive the large capacitive load
at the final stage
Sizing an inverter chain

Sizing an Inverter Chain
• If the chain is too long, the signal delay will be too large due to
intrinsic delay of each inverter
• If the chain is too short, the output signal slope will be very weak
with long rise and fall times, which again causes long delay
• The challenge is to decide the length of the chain ie. How many
inverters, and the size of each inverter
Graph plot of inverter chain delay
and power dissipation

Transistor Sizing:
The sizing of the transistor can be done using RC delay approximation. The RC delay model
helps in delay estimation CMOS circuit. The RC delay model treats the non-linear transistor
current-voltage I-V and capacitor voltage C-V characteristics with their equivalent resistance
and capacitance model
This RC delay model approximates a transistor as a switch
with a series of resistance or effective resistance R (which
is the ratio of the average value of Vds to Ids). The size of
a unit transistor is approximated as 4/2 lambda. The RC
circuit equivalent models for the PMOS and NMOS
transistors are shown below.
Here the k width of both PMOS and NMOS transistors is
contacted to source S and drain D. Since the holes in
PMOS have lower mobility compared to electrons in the
NMOS transistors, the PMOS will have twice the
resistance of the NMOS.

Transistor Sizing:
The n-well is usually tied with the high voltage because the capacitors of PMOS are shown with
the VDD as their second terminal in the figure shown. Similarly in NMOS , the capacitors are
connected to ground because usually p-well will connected to lower supply.
1. The NMOS transistor which is having k times of width will have the resistance of R/k.
2. Similarly, A unit PMOS transistor which is having the k times of width will have the
resistance of 2R/k.
This is because of PMOS transistor will have greater resistance compared to the NMOS
transistor because its mobility is less. The value of R will be typically on the order of 10kohm
for a single transistor.

Transistor Sizing:
PMOS sizing:
for a unit PMOS transistor, the effective resistance with
the width k is given by 2R/k.
In this network, the path E-C-B is the longest path. So, we
can write the equation (2R/k) + (2R/k) + (2R/k) =R Where
R is the effective resistance. The equation gives the value
of k=6. Therefore, the k value transistors, E,C, and B will
be 6.
One more path D-C-B also contributes to the worst-case or
longest path, so the k value of the transistor D also
becomes 6. The transistor A is equivalent to two transistors
B and C. Therefore, we can write 2R/k =2 *2R/6. Since we
know the k values of B and C transistors.
Therefore, the k value of transistor A is 3.

Transistor Sizing:
NMOS sizing:
for a unit NMOS transistor, the effective resistance
with the width k is given by R/k.
In this network, the worst-case or the longest path can
be seen is with two transistors. (The paths A-B, A-C,
and D-E). So we can write the relation 2*R/k=R, so
the value of k of all the NMOS transistors will be 2
since all are in the longest path.
Exercise:
Realize Y= (D + A*(B +C))’ in CMOS and
Evaluate the sizing of the transistors.

Transistor and Gate Sizing for Dynamic Power Dissipation
• As seen in the previous graph, a large gate is required to drive a
large load with acceptable delay but requires more power
• This is similar to the classical delay area tradeoff problem
• If we are not allowed to restructure the transistor network, the
sizing for dynamic power reduction generally has the same goal as
the area reduction problem
• The basic rule is to use the smallest transistors or gates that satisfy
the delay constraints
• To reduce dynamic power, the gates that toggle with higher
frequency should be made smaller
• Although the basic rule sounds simple, the actual sizing problem is
very complicated

Gate sizing problem
• Consider a part of the circuit as shown above
• Suppose that the gates are not on the critical delay path and should be sized
down
• W can size down the first gate, the second gate or both, subject to the available
sizes in the cell library as long as the path delay is not violated
• If the path contains many gates, the optimization problem becomes very
complicated
• Stack time
– Used to express the timing constraints of the circuit
– It is the difference between the signal required time and signal arivela time at
the output of a gate

• A positive stack time mean that the signal arrived earlier than its
required time and the gate can be sized down
• The goal of gate sizing is to adjust the gate sizes such that the
stack time of each gate is as low as possible without any gate
having a negative stack i.e. timing violation
• The area minimum sizing problem has been a subject of research
in logic synthesis for dozen of years
• Today in top down cell based design environment gate sizing has
been much automated by the logic synthesis system

Transistor Sizing for Leakage Power Reduction
• An interesting problem occurs when the sizing goal is to reduce the
leakage power of a circuit
• The leakage current of a transistor increases with decreasing
threshold voltage and channel length
• In general, a lower threshold or shorter channel transistor can
provide more saturation current and thus offers a faster transistor
• The presents a tradeoff between leakage power and delay
• The leakage power of a digital circuit depends on the logic state of
a circuit
• Consider a simple two transistor inverter
• If the output of the inverter is at logic high, the leakage current of
the inverter is determined by the N- transistor that is turned off

• Conversely if the output is low, the leakage current depends on the
P- transistor
• In order to suppress the leakage current, we can increase the
threshold voltage or the channel length of the N- transistor
• However, by doing so we also increase the delay of the inverter
because the N- transistor now offers less saturation current when it
is turned ON
• If we are fortunate that the falling transition of the inverter is not
the critical delay, we can use skewed transistor sizing method to
reduce the leakage power without incurring any delay penalty

• The transistor sizing concept is illustrated below
Transistor sizing for leakage power reduction or speed increase

Equivalent Pin Ordering
• Most combinational digital logic gates have input pins that
logically equivalent
• Eg:AND, OR, XOR
• Such gates are use frequently because they are natural to the
human thinking process
• As for circuit implementation, the gates are robust and easy to
design
• Logically equivalent pins may not have identical circuit
characteristics, which means that the pins have different delay and
power consumption
• Such property can be exploited for low power design

Equivalent Pin Ordering
• Consider a CMOS NAND gate as shown below
• We examine the condition when the input A is at high logic and the
input B switches from logic low to high
• The difference in power dissipation varies depending on various
factors such as capacitances and transistor sizes
• To conserve power the inputs should be connected such that
transistors from input A to OUT occur more frequently than
transitions from input B to OUT. This low power technique is
known as pin ordering

Network Restructuring and Reorganization
• The pin reordering technique is a special case of more general
method called transistor restructuring
• In this method, we restructure the transistors of a
• combinational cell, based on signal probabilities, to achieve better power
efficiency within the allowable timing constraints Restructuring
– In CMOS logic design, there is a well
• Transistor Network known technique in which a Boolean function composed of
AND and OR operators is directly mapped to a complex transistor network that
implements the function
– The mapping steps are as follows:
1. Each variable in the Boolean function corresponds to a pair of P and N
transistors
2. For the N transistor network, an AND operator corresponds to a serial
connection and an OR operator corresponds to a parallel connection

3. For the P transistor network, the composition rule is inverted
4. An inverter is optionally added to the output of the complex gate
to maintain the proper polarity or to ensure signal strength
Network composition of CMOS complex logic gate Y =A( B + C )

Alternative circuit implementation
of Y =A( B + C )
Four different circuit implementation of Y =A( B + C )
 Power reduction up to 20% was reported using the
transistor network restructuring technique

Transistor Network Partitioning and Reorganization
• In this section, we look beyond a CMOS gate and consider a
transistor network
• We study the problem of partitioning and reorganizing the network
to explore the different power-area-delay trade off
• Network reorganization by definition is the task of composing
different transistor networks that can implement the same
functionality
• The figure below show two ways to implement a 4 input AND
operation with a serial chain limit of three

Gate Oxide Thickness:
EOT (Equivalent Oxide thickness):
An equivalent oxide thickness is distance, usually given in nanometre(nm) which indicate
how thick a silicon oxide film would need to be to produce the same effect as high as k
material being used. Device performance has typically been improved by reducing the
thickness of a Si- oxide insulating pad. There is a trade off between the oxide thickness and
threshold voltage. So we choose equivalent oxide thickness.

Low Power Design through Voltage Scaling :
The switching power dissipation in CMOS digital integrated circuits is a strong function of the
power supply voltage. Therefore, reduction of VDD emerges as a very effective means of limiting
the power consumption.
- DC- DC converters
and/or separate power
pins to achieve this goal.
- The savings in power
dissipation comes at a
significant cost in terms of
increased circuit delay.

Solution: If the threshold voltage is also scaled down, the negative effects of the
voltage scaling on delay can be compensated.
Reducing the threshold voltage from 0.8 to 0.2 V can improve the delay at VDD= 2
V by a factor of 2..
- Using low –VT transistors raises
significant concerns about noise margins
and subthreshold conduction.
- Leads to smaller noise margin
- For threshold voltages smaller than 0.2 V,
leakage due to sub-threshold conduction in
stand-by, i.e., when the gate is not
switching, may become a very significant
component of the overall power
consumption.

Using a low supply voltage (VDD) and a low threshold voltage (VT) in CMOS logic
circuits is an efficient method for reducing the overall power dissipation, while
maintaining high speed performance.
Variable-Threshold CMOS (VTCMOS) Circuits:
- Techniques which help in overcoming the
issues of leakage and stand-by power
dissipation: Variable –Threshold
CMOS(VTMOS) and Multiple Threshold
CMOS (MTCMOS)

Using a low supply voltage (VDD) and a low threshold voltage (VT) in CMOS logic circuits is an
efficient method for reducing the overall power dissipation, while maintaining high speed
performance.
-When the inverter circuit is operating in its active mode, the substrate bias voltage of the nMOS
transistor is VOn = 0 and the substrate bias voltage of the PMOS transistor is VBP = VDD.
Thus, the inverter transistors do not experience any back gate-bias effect.
-When the inverter circuit is in the stand-by mode, however, the substrate bias control circuit
generates a lower substrate bias voltage for the NMOS transistor and a higher substrate bias
voltage for the PMOS transistor.
-As a result, the magnitudes of the threshold voltages VTl and VT, both increase in the stand-by
mode, due to the back gate bias effect. Since the sub-threshold leakage current drops
exponentially with increasing threshold voltage, the leakage power dissipation in the stand-by
mode can be significantly reduced with this technique.

Multiple-Threshold CMOS (MTCMOS) Circuits:
Here, low-VT transistors are typically used to design the logic gates where switching speed is
essential, whereas high- VT transistors are used to effectively isolate the logic gates in stand-by and
to prevent leakage dissipation
-In the active mode, the high-VT transistors are
turned on and the logic gates consisting of low-
VT transistors can operate with low switching
power dissipation and small propagation delay.
-When the circuit is driven into stand-by mode,
on the other hand, the high-VT transistors are
turned off and the conduction paths for any
sub-threshold leakage currents that may
originate from the internal low-VT circuitry are
effectively cut off.

Scaling :
Scaling of a transistor means reducing the critical parameter of the device in accordance with a
given criterion in order to improve some performance features such as Speed, Application, Power
Dissipation, and so on while keeping the basic operational characteristics unchanged.
Advantages:
• Packaging Density
• Size Chip
• Multifunction of Chip
Types:
1. Constant Field Scaling or Full Scaling:
In this, all the parameter of the MOSFET is scaled to understand it in a better way we
will consider a case, suppose the scaling factor is “S” whose values greater than 1
(S>1) now consider all the parameters of MOSFET is scaled by scaling factor “S” then
its all parameter will get changed to a new value.
For example, if the original gate length is “L” then after scaling it will become L’ = L/S

Scaling :
2. Constant Voltage Scaling:
In this only, the physical parameters of the MOSFET are Scaled-down such as the Gate
length of the MOSFET is decreased, and this result In a Short Channel Effect which will
directly affect the Drain Current, therefore the drain Current is Inversely proportional to
gate length. And electrical Parameters are kept constant, such as the terminal voltage of
the MOSFET is kept constant.
3. Lateral Scaling:
In this type of scaling only the width of the gate channel is scaled. It’s commonly
called a gate shrink. This type of scaling is used only in specific applications. the
disadvantage associate with this type is the high electric field through the channel and
hence it also causes a short channel effect.

Scaling :

Technology & Device innovation :
Silicon On Insulator (SOI):
• This technology can improve delay and power through a 25% reduction in total
capacitance .
• Si layer on top on insulator layer to build active devices and circuits.
• The insulator layer is usually made of SiO2

Technology & Device innovation :
Advantages :

Degrees of Freedom
the three degrees of freedom inherent in the low-power design
space is:
Voltage
Physical Capacitance
Activity

Voltage:
With its quadratic relationship to power, voltage reduction offers the
most direct and dramatic means of minimizing energy consumption.
Without requiring any special circuits or technologies, a factor of two
reduction in supply voltage yields a factor of four decrease in energy.

ECE6003-Module_1.pptx electronics and communication

More Related Content

Similar to ECE6003-Module_1.pptx electronics and communication (20)

More from muskans14 (9)

Recently uploaded (20)

ECE6003-Module_1.pptx electronics and communication