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EDA for IC System Design,
Verification, and Testing
© 2006 by Taylor & Francis Group, LLC

Electronic Design Automation for
Integrated Circuits Handbook
Edited by
Louis Scheffer, Luciano Lavagno,
and Grant Martin
EDA for IC System Design, Verification,
and Testing
EDA for IC Implementation, Circuit Design, and
Process Technology

EDA for IC System Design,
Verification, and Testing
Edited by
Louis Scheffer
Cadence Design Systems
San Jose, California, U.S.A.
Luciano Lavagno
Cadence Berkeley Laboratories
Berkeley, California, U.S.A.
Grant Martin
Tensilica Inc.
Santa Clara, California, U.S.A.

Published in 2006 by
CRC Press
Taylor & Francis Group
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CRC Press is an imprint of Taylor & Francis Group
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International Standard Book Number-10: 0-8493-7923-7 (Hardcover)
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Library of Congress Cataloging-in-Publication Data
EDA for IC system design, verification, and testing / editors, Louis Scheffer, Luciano Lavagno, Grant
Martin.
p. cm. -- (Electronic design and automation for integrated circuits handbook)
Includes bibliographical references and index.
ISBN 0-8493-7923-7
1. Integrated circuits--Computer-aided design. 2. Integrated circuits--Verification--Data processing. I.
Title: Electronic design automation for integrated circuit system design, verification, and testing. II.
Scheffer, Louis. III. Lavagno, Luciano, 1959- IV. Martin, Grant (Grant Edmund) V. Series.
TK7874.E26 2005
621.3815--dc22 2005052924
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Acknowledgments
and Dedication for the
EDA Handbook
The editors would like to acknowledge the unsung heroes of EDA, those who have worked to advance the
field, in addition to advancing their own personal, corporate, or academic agendas. These are the men and
women who have played a variety of key roles — they run the smaller conferences, they edit technical
journals, and they serve on standards committees, just to name a few. These largely volunteer jobs do not
make anyone rich or famous despite the time and effort that goes into them, but they do contribute
mightily to the remarkable and sustained advancement of EDA. Our kudos to these folks, who do not get
the credit they deserve.
On a more personal note, Louis Scheffer would like to acknowledge the love, support, encouragement,
and help of his wife Lynde, his daughter Lucynda, and his son Loukos. Without them this project would
not have been possible.
Luciano Lavagno would like to thank his wife Paola and his daughter Alessandra Chiara for making his
life so wonderful.
Grant Martin would like to acknowledge, as always, the love and support of his wife, Margaret Steele,
and his two daughters, Jennifer and Fiona.
CRC_7923_Dedi.qxd 2/20/2006 2:50 PM Page v

Preface
Preface for Volume 1
Electronic Design Automation (EDA) is a spectacular success in the art of engineering. Over the last quar-
ter of a century, improved tools have raised designers’ productivity by a factor of more than a thousand.
Without EDA, Moore’s law would remain a useless curiosity. Not a single billion-transistor chip could be
designed or debugged without these sophisticated tools — without EDA we would have no laptops, cell
phones, video games, or any of the other electronic devices we take for granted.
Spurred on by the ability to build bigger chips, EDA developers have largely kept pace, and these enor-
mous chips can still be designed, debugged, and tested, even with decreasing time-to-market.
The story of EDA is much more complex than the progression of integrated circuit (IC) manufactur-
ing, which is based on simple physical scaling of critical dimensions. EDA, on the other hand, evolves by
a series of paradigm shifts. Every chapter in this book, all 49 of them, was just a gleam in some expert’s
eye just a few decades ago. Then it became a research topic, then an academic tool, and then the focus of
a start-up or two. Within a few years, it was supported by large commercial EDA vendors, and is now part
of the conventional wisdom. Although users always complain that today’s tools are not quite adequate for
today’s designs, the overall improvements in productivity have been remarkable. After all, in which other
field do people complain of only a 21% compound annual growth in productivity, sustained over three
decades, as did the International Technology Roadmap for Semiconductors in 1999?
And what is the future of EDA tools? As we look at the state of electronics and IC design in 2005–2006,
we see that we may soon enter a major period of change in the discipline. The classical scaling approach
to ICs, spanning multiple orders of magnitude in the size of devices over the last 40+ years, looks set to
last only a few more generations or process nodes (though this has been argued many times in the past,
and has invariably been proved to be too pessimistic a projection). Conventional transistors and wiring
may well be replaced by new nano- and biologically based technologies that we are currently only begin-
ning to experiment with. This profound change will surely have a considerable impact on the tools and
methodologies used to design ICs. Should we be spending our efforts looking at Computer Aided Design
(CAD) for these future technologies, or continue to improve the tools we currently use?
Upon further consideration, it is clear that the current EDA approaches have a lot of life left in them.
With at least a decade remaining in the evolution of current design approaches, and hundreds of thou-
sands or millions of designs left that must either craft new ICs or use programmable versions of them, it
is far too soon to forget about today’s EDA approaches. And even if the technology changes to radically
new forms and structures, many of today’s EDA concepts will be reused and built upon for design of
technologies well beyond the current scope and thinking.
CRC_7923_Preface.qxd 2/23/2006 3:21 PM Page vii

The field of EDA for ICs has grown well beyond the point where any single individual can master it all,
or even be aware of the progress on all fronts. Therefore, there is a pressing need to create a snapshot of
this extremely broad and diverse subject. Students need a way of learning about the many disciplines and
topics involved in the design tools in widespread use today. As design grows multi-disciplinary, electron-
ics designers and EDA tool developers need to broaden their scope. The methods used in one subtopic
may well have applicability to new topics as they arise. All of electronics design can utilize a comprehen-
sive reference work in this field.
With this in mind, we invited many experts from across all the disciplines involved in EDA to con-
tribute chapters summarizing and giving a comprehensive overview of their particular topic or field. As
might be appreciated, such chapters represent a snapshot of the state of the art in 2004–2005. However,
as surveys and overviews, they retain a lasting educational and reference value that will be useful to stu-
dents and practitioners for many years to come.
With a large number of topics to cover, we decided to split the Handbook into two volumes. Volume
One covers system-level design, micro-architectural design, and verification and test. Volume Two covers
the classical “RTL to GDS II” design flow, incorporating synthesis, placement and routing, along with
related topics; analog and mixed-signal design, physical verification, analysis and extraction, and tech-
nology CAD topics for IC design. These roughly correspond to the classical “front-end/back-end” split in
IC design, where the front-end (or logical design) focuses on making sure that the design does the right
thing, assuming it can be implemented, and the back-end (or physical design) concentrates on generat-
ing the detailed tooling required, while taking the logical function as given. Despite limitations, this split
has persisted through the years — a complete and correct logical design, independent of implementation,
remains an excellent handoff point between the two major portions of an IC design flow. Since IC design-
ers and EDA developers often concentrate on one side of this logical/physical split, this seemed to be a
good place to divide the book as well.
In particular, Volume One starts with a general introduction to the topic, and an overview of IC design
and EDA. System-level design incorporates many aspects — application-specific tools and methods, spe-
cial specification and modeling languages, integration concepts including the use of Intellectual Property
(IP), and performance evaluation methods; the modeling and choice of embedded processors and ways
to model software running on those processors; and high-level synthesis approaches. ICs that start at the
system level need to be refined into micro-architectural specifications, incorporating cycle-accurate mod-
eling, power estimation methods, and design planning. As designs are specified and refined, verification
plays a key role — and the handbook covers languages, simulation essentials, and special verification top-
ics such as transaction-level modeling, assertion-based verification, and the use of hardware acceleration
and emulation as well as emerging formal methods. Finally, making IC designs testable and thus cost-
effective to manufacture and package relies on a host of test methods and tools, both for digital and ana-
log and mixed-signal designs.
This handbook with its two constituent volumes is a valuable learning and reference work for every-
one involved and interested in learning about electronic design and its associated tools and methods. We
hope that all readers will find it of interest and that it will become a well-thumbed resource.
Louis Scheffer
Luciano Lavagno
Grant Martin
Preface
CRC_7923_Preface.qxd 2/23/2006 3:21 PM Page viii

Editors
Louis Scheffer
Louis Scheffer received the B.S. and M.S. degrees from Caltech in 1974 and 1975, and a Ph.D. from
Stanford in 1984. He worked at Hewlett Packard from 1975 to 1981 as a chip designer and CAD tool
developer. In 1981, he joined Valid Logic Systems, where he did hardware design, developed a schematic
editor, and built an IC layout, routing, and verification system. In 1991, Valid merged with Cadence, and
since then he has been working on place and route, floorplanning systems, and signal integrity issues.
His main interests are floorplanning and deep submicron effects. He has written many technical
papers, tutorials, invited talks, and panels, and has served the DAC, ICCAD, ISPD, SLIP, and TAU con-
ferences as a technical committee member. He is currently the general chair of TAU and ISPD, on the
steering committee of SLIP, and an associate editor of IEEE Transactions on CAD. He holds five patents
in the field of EDA, and has taught courses on CAD for electronics at Berkeley and Stanford. He is also
interested in SETI, and serves on the technical advisory board for the Allen Telescope Array at the SETI
institute, and is a co-author of the book SETI-2020, in addition to several technical articles in the field.
Luciano Lavagno
Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino
in 1993. He is a co-author of two books on asynchronous circuit design, of a book on hardware/software
co-design of embedded systems, and of over 160 scientific papers.
Between 1993 and 2000, he was the architect of the POLIS project, a cooperation between U.C.
Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a com-
plete hardware/software co-design environment for control-dominated embedded systems.
He is currently an Associate Professor with Politecnico di Torino, Italy and a research scientist with
Cadence Berkeley Laboratories. He serves on the technical committees of several international confer-
ences in his field (e.g., DAC, DATE, ICCAD, ICCD) and of various workshops and symposia. He has been
the technical program and tutorial chair of DAC, and the technical program and general chair of CODES.
He has been associate and guest editor of IEEE Transactions on CAD, IEEE Transactions on VLSI and
ACM Transactions on Embedded Computing Systems.
His research interests include the synthesis of asynchronous and low-power circuits, the concurrent
design of mixed hardware and software embedded systems, as well as compilation tools and architectural
design of dynamically reconfigurable processors.
CRC_7923_About Auth.qxd 2/20/2006 2:47 PM Page ix

Grant Martin
Grant Martin is a Chief Scientist at Tensilica, Inc. in Santa Clara, California. Before that, Grant worked
for Burroughs in Scotland for 6 years; Nortel/BNR in Canada for 10 years; and Cadence Design Systems
for 9 years, eventually becoming a Cadence Fellow in their Labs. He received his Bachelors and Masters
degrees in Mathematics (Combinatorics and Optimization) from the University of Waterloo, Canada, in
1977 and 1978.
Grant is a co-author of Surviving the SOC Revolution: A Guide to Platform-Based Design, 1999, and
System Design with SystemC, 2002, and a co-editor of the books Winning the SoC Revolution: Experiences
in Real Design, and UML for Real: Design of Embedded Real-Time Systems, June 2003, all published by
Springer (originally by Kluwer). In 2004, he co-wrote with Vladimir Nemudrov the first book on SoC
design published in Russian by Technosphera, Moscow. Recently, he co-edited Taxonomies for the
Development and Verification of Digital Systems (Springer, 2005), and UML for SoC Design (Springer, 2005).
He has also presented many papers, talks and tutorials, and participated in panels, at a number of
major conferences. He co-chaired the VSI Alliance Embedded Systems study group in the summer of
2001, and is currently co-chair of the DAC Technical Programme Committee for Methods for 2005 and
2006. His particular areas of interest include system-level design, IP-based design of system-on-chip, plat-
form-based design, and embedded software. He is a senior member of the IEEE.
Editors
CRC_7923_About Auth.qxd 2/20/2006 2:47 PM Page x

Contributors
Iuliana Bacivarov
SLS Group, TIMA Laboratory
Grenoble, France
Mike Bershteyn
Cadence Design Systems, Inc.
Cupertino, California
Shuvra Bhattacharyya
University of Maryland
College Park, Maryland
Joseph T. Buck
Synopsys, Inc.
Mountain View, California
Raul Camposano
Synopsys Inc.
Naehyuck Chang
Seoul National University
Seoul, South Korea
Kwang-Ting (Tim) Cheng
University of California
Santa Barbara, California
Alain Clouard
STMicroelectronics
Crolles, France
Marcello Coppola
STMicroelectronics
Grenoble, France
Robert Damiano
Synopsys Inc.
Hillsboro, Oregon
Marco Di Natale
Scuola Superiore S. Anna
Pisa, Italy
Nikil Dutt
Donald Bren School of Information and
Computer Sciences,
University of California, Irvine
Irvine, California
Stephen A. Edwards
Columbia University
New York, New York
Limor Fix
Design Technology, Intel
Pittsburgh, Pennsylvania
CRC_7923_LOC.qxd 2/20/2006 2:45 PM Page xi

Harry Foster
Jasper Design Automation
Frank Ghenassia
STMicroelectronics
Crolles, France
Miltos D. Grammatikakis
ISD S.A.
Athens, Greece
Rajesh Gupta
University of California, San Diego
San Diego, California
Sumit Gupta
Tensilica Inc.
Santa Clara, California
Ahmed Jerraya
SLS Group, TIMA Laboratory, INPG
Grenoble, France
Bozena Kaminska
Simon Fraser University and
Pultronics Incorporated
Burnaby, British Colombia,
Canada
Bernd Koenemann
Mentor Graphics, Inc.
San Jose, California
Luciano Lavagno
Berkeley, California
Steve Leibson
Tensilica, Inc.
Enrico Macii
Politecnico di Torino
Torino, Italy
Laurent Maillet-Contoz
STMicroelectronics
Crolles, France
Erich Marschner
Grant Martin
Tensilica Inc.
Ken McMillan
Renu Mehra
Synopsys, Inc.
Prabhat Mishra
University of Florida
Gainesville, Florida
Ralph H.J.M. Otten
Eindhoven University of Technology
Eindhoven, Netherlands
Massimo Poncino
Politecnico di Torino
Torino, Italy
John Sanguinetti
Forte Design Systems, Inc.
Louis Scheffer
CRC_7923_LOC.qxd 2/20/2006 2:45 PM Page xii

Sandeep Shukla
Virginia Tech
Blacksburg, Virginia
Gaurav Singh
Virginia Tech
Blacksburg, Virginia
Jean-Philippe Strassen
STMicroelectronics
Crolles, France
Vivek Tiwari
Intel Corp.
Ray Turner
Li-C. Wang
University of California
Santa Barbara, California
John Wilson
Mentor Graphics
Berkshire, United Kingdom
Wayne Wolf
Princeton University
Princeton, New Jersey
CRC_7923_LOC.qxd 2/20/2006 2:45 PM Page xiii

Contents
1 Overview
Luciano Lavagno, Grant Martin, and Louis Scheffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Introduction to Electronic Design Automation for Integrated Circuits . . . . . . . . . . . . . . . . . . . . 1-2
System Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Micro-Architecture Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Logical Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
RTL to GDS-II, or Synthesis, Place, and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Analog and Mixed-Signal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Physical Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Technology Computer-Aided Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2 The Integrated Circuit Design Process and Electronic Design Automation
Robert Damiano and Raul Camposano. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.4 Design for Manufacturing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
3 Tools and Methodologies for System-Level Design
Shuvra Bhattacharyya and Wayne Wolf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 Characteristics of Video Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.3 Other Application Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.4 Platform Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
CRC_7923_Contents.qxd 2/20/2006 2:46 PM Page xv
SECTION II System Level Design
SECTION I Introduction

3.5 Models of Computation and Tools for Model-Based Design . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
3.7 Hardware/Software Cosynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
4 System-Level Specification and Modeling Languages
Joseph T. Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.2 A Survey of Domain-Specific Languages and Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.3 Heterogeneous Platforms and Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
5 SoC Block-Based Design and IP Assembly
John Wilson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 The Economics of Reusable IP and Block-Based Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 Standard Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3 Use of Assertion-Based Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5.4 Use of IP Configurators and Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5 The Design Assembly and Verification Challenge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.6 The SPIRIT XML Databook Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
6 Performance Evaluation Methods for Multiprocessor System-on-Chip Design
Ahmed Jerraya and Iuliana Bacivarov . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 Overview of Performance Evaluation in the Context of System Design Flow . . . . . . . . . . . 6-2
6.3 MPSoC Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
7 System-Level Power Management
Naehyuck Chang, Enrico Macii, Massimo Poncino, and Vivek Tiwari. . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
7.2 Dynamic Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
7.3 Battery-Aware Dynamic Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.4 Software-Level Dynamic Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
8 Processor Modeling and Design Tools
Prabhat Mishra and Nikil Dutt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.2 Processor Modeling Using ADLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.3 ADL-Driven Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
8.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
9 Embedded Software Modeling and Design
Marco Di Natale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.2 Synchronous vs. Asynchronous Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.3 Synchronous Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13
9.4 Asynchronous Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
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9.5 Research on Models for Embedded Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-34
9.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40
10 Using Performance Metrics to Select Microprocessor Cores for IC Designs
Steve Leibson . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.2 The ISS as Benchmarking Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
10.3 Ideal Versus Practical Processor Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.4 Standard Benchmark Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
10.5 Prehistoric Performance Ratings: MIPS, MOPS, and MFLOPS . . . . . . . . . . . . . . . . . . . 10-5
10.6 Classic Processor Benchmarks (The Stone Age) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
10.7 Modern Processor Performance Benchmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.8 Configurable Processors and the Future of Processor-Core Benchmarks . . . . . . . . . . 10-22
10.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
11 Parallelizing High-Level Synthesis: A Code Transformational Approach
to High-Level Synthesis
Gaurav Singh, Sumit Gupta, Sandeep Shukla, and Rajesh Gupta . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11.2 Background and Survey of the State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.3 Parallelizing HLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
11.4 The SPARK PHLS Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
11.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
12 Cycle-Accurate System-Level Modeling and Performance Evaluation
Marcello Coppola and Miltos D. Grammatikakis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 System Modeling and Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.3 Back-Annotation of System-Level Modeling Objects . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.4 Automatic Extraction of Statistical Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.5 Open System-Level Modeling Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-16
13 Micro-Architectural Power Estimation and Optimization
Enrico Macii, Renu Mehra, and Massimo Poncino . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.3 Architectural Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.4 Micro-Architectural Power Modeling and Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
13.5 Micro-Architectural Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
14 Design Planning
Ralph H.J.M. Otten . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Floorplans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.3 Wireplans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.4 A Formal System For Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
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Micro-Architecture Design
SECTION III

15 Design and Verification Languages
Stephen A. Edwards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.3 Design Languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.4 Verification Languages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26
16 Digital Simulation
John Sanguinetti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Event- vs. Process-Oriented Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.3 Logic Simulation Methods and Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
16.4 Impact of Languages on Logic Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
16.5 Logic Simulation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
16.6 Impact of HVLs on Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
16.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
17 Using Transactional-Level Models in an SoC Design Flow
Alain Clouard, Frank Ghenassia, Laurent Maillet-Contoz, and Jean-Philippe Strassen . . . . . . . . 17-1
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1
17.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2
17.3 Overview of the System-to-RTL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4
17.4 TLM — A Complementary View for the Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
17.5 TLM Modeling Application Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
17.6 Example of a Multimedia Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
17.7 Design Flow Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
17.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17
18 Assertion-Based Verification
Erich Marschner and Harry Foster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1
18.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
18.3 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
19 Hardware Acceleration and Emulation
Ray Turner and Mike Bershteyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
19.2 Emulator Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4
19.3 Design Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9
19.4 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14
19.5 Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
19.6 The Value of In-Circuit Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.7 Considerations for Successful Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17
19.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20
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SECTION IV Logical Verification

20 Formal Property Verification
Limor Fix and Ken McMillan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1
20.2 Formal Property Verification Methods and Technologies . . . . . . . . . . . . . . . . . . . . . . . 20-4
20.3 Software Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8
20.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
21 Design-For-Test
Bernd Koenemann . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
21.2 The Objectives of Design-For-Test for Microelectronics Products . . . . . . . . . . . . . . . . 21-2
21.3 Overview of Chip-Level Design-For-Test Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
21.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33
22 Automatic Test Pattern Generation
Kwang-Ting (Tim) Cheng and Li-C. Wang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
22.2 Combinational ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
22.3 Sequential ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
22.4 ATPG and SAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13
22.5 Applications of ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20
22.6 High-Level ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25
23 Analog and Mixed Signal Test
Bozena Kaminska . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1
23.2 Analog Circuits and Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2
23.3 Testability Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4
23.4 Fault Modeling and Test Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5
23.5 Catastrophic Fault Modeling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6
23.6 Parametric Faults, Worst-Case Tolerance Analysis, and Test Generation . . . . . . . . . . . 23-6
23.7 Design for Test — An Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.8 Analog Test Bus Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7
23.9 Oscillation-Based DFT/BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8
23.10 PLL, VCO, and Jitter Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10
23.11 Review of Jitter Measurement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11
23.12 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22
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SECTION V Test

SECTION I
INTRODUCTION
CRC_7923_ch001.qxd 2/20/2006 2:35 PM Page 1

1
Overview
Integrated Circuits ............................................................ 1-2
Industry Conferences and Publications • Structure of the Book
• Digital
•
•
1-1
CRC_7923_ch001.qxd 2/20/2006 2:35 PM Page 1
Introduction to Electronic Design Automation for
A Brief History of Electronic Design Automation • Major
System Level Design .......................................................... 1-6
Bhattacharyya and Wolf
Tools and Methodologies for System-Level Design by
• System-Level Specification and
Modeling Languages by Buck • SoC Block-Based Design and
IP Assembly by Wilson • Performance Evaluation Methods
for Multiprocessor Systems-on-Chip Design by Bacivarov and
Poncino and Tiwari • Processor Modeling and Design Tools
by Mishra and Dutt • Embedded Software Modeling and
• Using Performance Metrics to Select
Design by di Natale
Jerraya • System-Level Power Management by Chang, Macii,
Microprocessor Cores for IC Designs by Leibson
Transformational Approach to High-Level Synthesis by Singh
• Parallelizing High-Level Synthesis: A Code
Gupta, Shukla, and Gupta
Micro-Architecture Design .............................................. 1-8
Evaluation by Coppola and Grammatikakis • Micro-
Cycle-Accurate System-Level Modeling and Performance
Architectural Power Estimation and Optimization by Macii,
Mehra, and Poncino • Design Planning by Otten
.......................................................... 1-8
Logical Verification
Design and Verification Languages by Edwards
• Using Transactional Level
Simulation by Sanguinetti
Models in a SoC Design Flow by Clouard, Ghenassia, Maillet-
Contoz, and Strassen • Assertion-Based Verification by Foster
• Hardware Acceleration and Emulation by
and Marschner
Bershteyn and Turner Formal Property Verification by Fix
and McMillan
Test .................................................................................... 1-9
Design-for-Test by Koenemann Automatic Test Pattern
Generation by Wang and Cheng • Analog and Mixed-Signal
RTL to GDS-II, or Synthesis, Place, and Route .............. 1-9
Design Flows by Hathaway, Stok, Chinnery, and Keutzer
Optimization from Circuit to Register Transfer Levels by
Test by Kaminska
• Logic Synthesis by Khatri and Shenoy • Power Analysis and
Monteiro, Patel, and Tiwari • Equivalence Checking by

•
Preparation by Schellenberg • Design for Manufacturability
in the Nanometer Era by Dragone, Guardiani, and Strojwas
• Design and Analysis of Power Supply Networks by Blaauw,
Pant, Chaudhry, and Panda • Noise Considerations in Digital
ICs by Kariat • Layout Extraction by Kao, Lo, Basel, Singh,
Spink, and Scheffer • Mixed-Signal Noise Coupling in
System-on-Chip Design: Modeling, Analysis, and Validation
by Vergese and Nagata
Technology Computer-Aided Design ............................ 1-12
Process Simulation by Johnson • Device Modeling — from
Physics to Electrical Parameter Extraction by Dutton, Choi,
and Kan • High-Accuracy Parasitic Extraction by Kamon and
Iverson
Introduction to Electronic Design Automation for Integrated
Circuits
Modern integrated circuits (ICs) are enormously complicated, often containing many millions of
devices. Design of these ICs would not be humanly possible without software (SW) assistance at every
stage of the process. The tools used for this task are collectively called electronic design automation
(EDA).
EDA tools span a very wide range, from purely logical tools that implement and verify functionality, to
purely physical tools that create the manufacturing data and verify that the design can be manufactured.
The next chapter, The IC Design Process and EDA, by Robert Damiano and Raul Camposano, discusses the
IC design process, its major stages and design flow, and how EDA tools fit into these processes and flows.
It particularly looks at interfaces between the major IC design stages and the kind of information —
abstractions upwards, and detailed design and verification information downwards — that must flow
between these stages.
A Brief History of Electronic Design Automation
This section contains a very brief summary of the origin and history of EDA for ICs. For each topic, the
title of the relevant chapter(s) is mentioned in italics.
1-2 EDA for IC Systems Design, Verification, and Testing
Luciano Lavagno
Grant Martin
Tensilica Inc.
Louis Scheffer
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Kuehlmann and Somenzi • Digital Layout — Placement by
Reda and Kahng • Static Timing Analysis by Sapatnekar
• Structured Digital Design by Mo and Brayton • Routing by
Scheffer • Exploring Challenges of Libraries for Electronic
Design by Hogan and Becker • Design Closure by Cohn and
Osler Tools for Chip-Package Codesign by Franzon
• Design Databases by Bales • FPGA Synthesis and Physical
Design by Betz and Hutton
Analog and Mixed-Signal Design .................................. 1-11
Level by Mantooth and Roychowdhury • Simulation and
Analog Simulation: Circuit Level and Behavioral
Modeling for Analog and Mixed-Signal Integrated
Analog ICs and Mixed-Signal SoCs: A Survey by
Circuits by Gielen and Philips • Layout Tools for
Rutenbar and Cohn
Design Rule Checking by Todd, Grodd, and Fetty •
Physical Verification ........................................................ 1-11
Resolution Enhancement Techniques and Mask Data

The need for tools became clear very soon after ICs were invented. Unlike a breadboard, ICs cannot be
modified easily after fabrication, so testing even a simple change involves weeks of delay (for new masks and
a new fabrication run) and considerable expense. Furthermore, the internal nodes of an IC are difficult to
probe because they are physically small and may be covered by other layers of the IC. Even if these problems
can be worked around, the internal nodes often have very high impedances and hence are difficult to meas-
ure without dramatically changing the performance. Therefore circuit simulators were crucial to IC design
almost as soon as ICs came into existence. These programs are covered in the chapter Analog Simulation:
Circuit Level and Behavioral Level, and appeared in the 1960s.
Next, as the circuits grew bigger, clerical help was required in producing the masks. At first there were
digitizing programs, where the designer still drew with colored pencils but the coordinates were trans-
ferred to the computer, written to magnetic tape, and then transferred to the mask making machines.
Soon, these early programs were enhanced into full-fledged layout editors. These programs were first
developed in the late 1960s and early 1970s. Analog designs in the modern era are still largely laid out
manually, with some tool assistance, as Layout Tools for Analog ICs and Mixed-Signal SoCs: A Survey will
attest, although some developments in more automated optimization have been occurring, along with
many experiments in more automated layout techniques.
As the circuits grew larger, getting the logic design correct became difficult, and Digital Simulation (i.e.,
logic simulation) was introduced into the IC design flow. Also, testing of the completed chip proved to be
difficult, since unlike circuit boards, internal nodes could not be observed or controlled through a “bed
of nails” fixture. Therefore automatic test pattern generation (ATPG) programs were developed that gen-
erate test vectors that only refer to the visible pins. Other programs that modified designs to make them
more controllable, observable, and testable were not far behind. These programs, covered in Design-for-
Test and Automatic Test Pattern Generation, were first available in the mid-1970s. Specialized Analog and
Mixed-Signal Test needs were met by special testers and tools.
As the number of design rules, number of layers, and chip sizes all continued to increase, it became
increasingly difficult to verify by hand that a layout met all the manufacturing rules, and to estimate the par-
asitics of the circuit. Therefore Design Rule Checking, and Layout Extraction programs were developed, start-
ing in the mid-1970s. As the processes became more complex, with more layers of interconnect, the original
analytic approximations to R, C, and L values became inadequate, and High-Accuracy Parasitic Extraction
programs were required to determine more accurate values, or at least calibrate the parameter extractors.
The next bottleneck was doing the detailed designing of each polygon. Placement and routing programs
allowed the user to specify only the gate-level netlist — the computer would then decide on the location
of the gates and the wires connecting them. Although some silicon efficiency was lost, productivity was
greatly improved, and IC design opened up to a wider audience of logic designers. The chapters Digital
Layout — Placement and Routing cover these programs, which became popular in the mid-1980s.
Even just the gate-level netlist soon proved to be of too much detail, and synthesis tools were devel-
oped to create such a netlist from a higher level specification, usually expressed in a hardware description
language (HDL). This is called Logic Synthesis and became available in the mid-1980s. In the last decade,
Power Analysis and Optimization from Circuit to Register Transfer Levels has become a major area of con-
cern and is becoming the number one optimization criterion for many designs, especially portable and
battery powered ones.
Around this time, the large collection of tools that need to be used to complete a single design became
a serious problem. Electronic design automation Design Databases were introduced to cope with this
problem. In addition, Design Flows began to become more and more elaborate in order to hook tools
together, as well as to develop and support both methodologies and use models for specific design groups,
companies, and application areas.
In the late 1990s, as the circuits continued to shrink, noise became a serious problem. Programs that
analyzed power and ground networks, cross-talk, and substrate noise in systematic ways became com-
mercially available. The chapters Design and Analysis of Power Supply Networks, Mixed-Signal Noise
Coupling in System-on-Chip Design: Modeling, Analysis and Validation, and Noise Considerations in Digital
ICs cover these topics.
Overview 1-3
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Gradually through the 1990s and early 2000s, chips and processes became sufficiently complex that the
designs that optimize yield were no longer only a minimization of size. Design for Manufacturability in
the Nanometer Era, otherwise known as “Design for Yield”, became a field of its own. Also in this time
frame, the size of the features on the chip became comparable to, or less than, the wavelength of the light
used to create them. To compensate for this as much as possible, the masks were no longer a direct copy
of what the designer intended. The creation of these more complex masks is covered in Resolution
Enhancement Techniques and Mask Data Preparation.
On a parallel track, developing the process itself was also a difficult problem. Process Simulation tools
were developed to predict the effects of changing various process parameters. The output from these pro-
grams, such as doping profiles, was useful to process engineers but too detailed for electrical analysis.
dict device performance from a physical description of devices was needed and developed. These models
were particularly useful when developing a new process.
One of the areas that developed very early in the design of electronic systems, at least in part, but which
is the least industrialized as a standard process, is that of system-level design. As the chapter on Using
Performance Metrics to Select Microprocessor Cores for IC Designs points out, one of the first instruction
set simulators appeared soon after the first digital computers did. However, until the present day, system-
level design has consisted mainly of a varying collection of tricks, techniques, and ad hoc modeling tools.
The logic simulation and synthesis processes introduced in the 1970s and 1980s, respectively, are, as
was discussed earlier, much more standardized. The front–end IC design flow would not have been pos-
sible to standardize without the introduction of standard HDLs. Out of a huge variety of HDLs intro-
duced from the 1960s to the 1980s, Verilog and VHDL have become the major Design and Verification
Languages. For a long time — till the mid to late 1990s, verification of digital design seemed stuck at stan-
dard digital simulation — although at least since the 1980s, a variety of Hardware Acceleration and
Emulation solutions have been available to designers. However, advances in verification languages and the
growth in design complexity have triggered interest in more advanced verification methods, and the last
decade has seen considerable interest in Using Transactional Level Models in a SoC Design Flow, Assertion-
based Verification, and Formal Property Verification. Equivalence Checking has been the formal technique
most tightly integrated into design flows, since it allows designs to be compared before and after various
optimizations and back-end-related modifications, such as scan insertion.
For many years, specific systems design domains have fostered their own application-specific Tools
and Methodologies for System-Level Design — especially in the areas of algorithm design from the late
1980s through to this day. The late 1990s saw the emergence of and competition between a number of
C/C⫹⫹-based System-Level Specification and Modeling Languages. With the possibility of now incorpo-
rating the major functional units of a design (processors, memories, digital and mixed-signal HW
blocks, peripheral interfaces, and complex hierarchical buses) all onto a single silicon substrate, the mid-
1990s to the present day have also seen the rise of the System-on-chip (SoC). It is thus that the area of
SoC Block-Based Design and IP Assembly has grown, in which the complexity possible with advanced
semiconductor processes is ameliorated to some extent via reuse of blocks of design. Concomitant with
the SoC approach has been the development, during the last decade, of Performance Evaluation Methods
for MPSoC Design, development of embedded processors through specialized Processor Modelling and
Design Tools, and gradual and still-forming links to Embedded Software Modelling and Design. The desire
to raise HW design productivity to higher levels has spawned considerable interest in (Parallelizing)
High Level Synthesis over the years. It is now seeing something of a resurgence driven by
C/C⫹⫹/SystemC as opposed to the first-generation high-level synthesis (HLS) tools driven by HDLs in
the mid-1990s.
After the system level of design, architects need to descend one level of abstraction to the micro-archi-
tectural level. Here, a variety of tools allow one to look at the three main performance criteria: timing
or delay (Cycle-accurate System-Level Modeling and Performance Evaluation), power (Micro-Architectural
Power Estimation and Optimization), and physical Design Planning.Micro-architects need to make trade-
offs between the timing, power, and cost/area attributes of complex ICs at this level.
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Another suite of tools (see Device Modeling — from Physics to Electrical Parameter Extraction) that pre-

The last several years have seen a considerable infilling of the design flow with a variety of comple-
mentary tools and methods. Formal verification of function is only possible if one is assured that the
timing is correct, and by keeping a lid on the amount of dynamic simulation required, especially at the
postsynthesis and postlayout gate levels, good Static Timing Analysis tools provide the assurance that
timing constraints are being met. It is also an underpinning to timing optimization of circuits and for
the design of newer mechanisms for manufacturing and yield. Standard cell-based placement and rout-
ing are not appropriate for Structured Digital Design of elements such as memories and register files,
leading to specialized tools. As design groups began to rely on foundries and application specific inte-
grated circuit (ASIC) vendors and as the IC design and manufacturing industry began to “de-vertical-
ize”, design libraries, covered in Exploring Challenges of Libraries for Electronic Design, became a domain
for special design flows and tools. It ensured the availability of a variety of high performance and low
power libraries for optimal design choices and allowed some portability of design across processes and
foundries. Tools for Chip-Package Codesign began to link more closely the design of IOs on chip, the
packages they fit into, and the boards on which they would be placed. For implementation “fabrics” such
as field-programmable gate arrays (FPGAs), specialized FPGA Synthesis and Physical Design Tools are
necessary to ensure good results. And a renewed emphasis on Design Closure allows a more holistic focus
on the simultaneous optimization of design timing, power, cost, reliability, and yield in the design
process.
Another area of growing but specialized interest in the analog design domain is the use of new and
higher level modeling methods and languages, which are covered in Simulation and Modeling for Analog
and Mixed-Signal Integrated Circuits.
A much more detailed overview of the history of EDA can be found in [1]. A historical survey of many
of the important papers from the International Conference on Computer-Aided Design (ICCAD) can be
found in [2].
Major Industry Conferences and Publications
The EDA community, formed in the early 1960s from tool developers working for major electronics
design companies such as IBM, AT&T Bell Labs, Burroughs, Honeywell, and others, has long valued
workshops, conferences, and symposia, in which practitioners, designers, and later, academic researchers,
could exchange ideas and practically demonstrate the techniques. The Design Automation Conference
(DAC) grew out of workshops, which started in the early 1960s, and although held in a number of U.S.
locations, has in recent years tended to stay on the west coast of the United States or a bit inland. It is the
largest combined EDA trade show and technical conference held annually anywhere in the world. In
Europe, a number of country-specific conferences held sporadically through the 1980s, and two compet-
ing ones held in the early 1990s, led to the creation of the consolidated Design Automation and Test in
Europe (DATE) conference, which started in the mid-1990s and has grown consistently in strength ever
since. Finally, the Asia-South Pacific DAC (ASP-DAC) started in the mid to late 1990s and completes the
trio of major EDA conferences spanning the most important electronics design communities in the
world.
Complementing the larger trade show/technical conferences has been ICCAD, which for over 20 years
has been held in San Jose, and has provided a more technical conference setting for the latest algorithmic
advances in EDA to be presented, attracting several hundred attendees. Various domain areas of EDA
knowledge have sparked a number of other workshops, symposia, and smaller conferences over the last
15 years, including the International Symposium on Physical Design (ISPD), International Symposium
on Quality in Electronic Design (ISQED), Forum on Design Languages in Europe (FDL), HDL and
Design and Verification conferences (HDLCon, DVCon), High-level Design, Verification and Test
(HLDVT), International Conference on Hardware–Software Codesign and System Synthesis
(CODES⫹ISSS), and many other gatherings. Of course, the area of Test has its own long-standing
International Test Conference (ITC); similarly, there are specialized conferences for FPGA design (e.g.,
Forum on Programmable Logic [FPL]) and a variety of conferences focusing on the most advanced IC
Overview 1-5
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designs such as the International Solid–State Circuits Conference (ISSCC) and its European counterpart
(ESSCC).
There are several technical societies with strong representation of design automation: one is the
Institute of Electrical and Electronics Engineers (IEEE, pronounced “eye-triple-ee”), and the other is the
Association for Computing Machinery (ACM).
Various IEEE and ACM transactions contain major work on algorithms and design techniques in print
— a more archival-oriented format than conference proceedings. Among these, the IEEE Transactions on
computer-aided design (CAD), the IEEE Transactions on VLSI systems, and the ACM Transactions on
Design Automation of Electronic Systems are notable. A more general readership magazine devoted to
Design and Test and EDA topics is IEEE Design and Test.
As might be expected, the EDA community has a strong online presence. All the conferences men-
tioned above have web pages describing locations, dates, manuscript submission and registration pro-
cedures, and often detailed descriptions of previous conferences. The journals above offer online
titles, abstracts, and full text. Both conference proceedings and journals are available. Most of the ref-
erences found in this volume, at least those published after 1988, can be found in at least one of these
libraries.
Structure of the Book
In the simplest case of digital design, EDA can be divided into system-level design, micro-architecture
design, logical verification, test, synthesis-place-and-route, and physical verification. System-level design
is the task of determining which components (bought and built, HW and SW) should comprise a system
that can do what one wants. Micro-architecture design fills out the descriptions of each of the blocks, and
sets the main parameters for their implementation. Logical verification verifies that the design does what
is intended. Test ensures that functional and nonfunctional chips can be told apart reliably, and inserts
testing circuitry if needed to ensure that this is the case. Synthesis, place, and route take the logical
description, and map it into increasingly detailed physical descriptions, until the design is in a form that
can be built with a given process. Physical verification checks that the design is manufacturable and will
be reliable. In general, each of these stages works with an increasingly detailed description of the design,
and may fail due to problems unforeseen at earlier stages. This makes the flow, or sequence of steps that
the users follow to finish their design, a crucial part of any EDA methodology.
Of course not all, or even most chips, are fully digital. Analog chips and chips with a mixture of ana-
log and digital signals (commonly called mixed-signal chips) require their own specialized tool sets.
All these tools must work on circuits and designs that are quite large, and do so in a reasonable amount
of time. In general, this cannot be done without models, or simplified descriptions of thebehavior of var-
ious chip elements. Creating these models is the province of Technology CAD (TCAD), which in general
treats relatively small problems in great physical detail, starting from very basic physics and building the
more efficient models needed by the tools that must handle higher data volumes.
The division of EDA into these sections is somewhat arbitrary, and below a brief description of each
of the chapters of the book is given.
System Level Design
Tools and Methodologies for System-Level Design by Bhattacharyya and Wolf
This chapter covers very high level system-level design approaches and associated tools such as Ptolemy,
the Mathworks tools, and many others, and uses video applications as a specific example illustrating how
these can be used.
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submission, refereeing, and publication. Online, the IEEE (http://ieee.org), ACM (http://acm.org), and
CiteSeer (http://citeseer.ist.psu.edu) offer extensive digital libraries, which allow searches through

System-Level Specification and Modeling Languages by Buck
This chapter discusses the major approaches to specify and model systems, and the languages and tools
in this domain. It includes issues of heterogeneous specifications, models of computation and linking
multidomain models, requirements on languages, and specialized tools and flows in this area.
SoC Block-Based Design and IP Assembly by Wilson
This chapter approaches system design with particular emphasis on SoC design via IP-based reuse and
block-based design. Methods of assembly and compositional design of systems are covered. Issues of IP
reuse as they are reflected in system-level design tools are also discussed.
Performance Evaluation Methods for Multiprocessor Systems-on-Chip Design
by Bacivarov and Jerraya
This chapter surveys the broad field of performance evaluation and sets it in the context of multi-proces-
sor systems-on-chip (MPSoC). Techniques for various types of blocks — HW, CPU, SW, and intercon-
nect — are included. A taxonomy of performance evaluation approaches is used to assess various tools
and methodologies.
System-Level Power Management by Chang, Macii, Poncino and Tiwari
This chapter discusses dynamic power management approaches, aimed at selectively stopping or slowing
down resources, whenever this is possible while still achieving the required level of system performance.
The techniques can be applied both to reduce power consumption, which has an impact on power dissi-
pation and power supply, and energy consumption, which improves battery life. They are generally driven
by the software layer, since it has the most precise picture about both the required quality of service and
the global state of the system.
Processor Modeling and Design Tools by Mishra and Dutt
This chapter covers state-of-the-art specification languages, tools, and methodologies for processor devel-
opment used in academia and industry. It includes specialized architecture description languages and the
tools that use them, with a number of examples.
Embedded Software Modeling and Design by di Natale
This chapter covers models and tools for embedded SW, including the relevant models of computation.
Practical approaches with languages such as unified modeling language (UML) and specification and
description language (SDL) are introduced and how these might link into design flows is discussed.
Using Performance Metrics to Select Microprocessor Cores for IC Designs by
Leibson
This chapter discusses the use of standard benchmarks, and instruction set simulators, to evaluate proces-
sor cores. These might be useful in nonembedded applications, but are especially relevant to the design
of embedded SoC devices where the processor cores may not yet be available in HW, or be based on user-
specified processor configuration and extension. Benchmarks drawn from relevant application domains
have become essential to core evaluation and their advantages greatly exceed that of the general-purpose
ones used in the past.
Overview 1-7
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Parallelizing High-Level Synthesis: A Code Transformational Approach to
High-Level Synthesis by Singh, Gupta, Shukla, and Gupta
This chapter surveys a number of approaches, algorithms, and tools for HLS from algorithmic or behav-
ioral descriptions, and focuses on some of the most recent developments in HLS. These include the use
of techniques drawn from the parallel compiler community.
Micro-Architecture Design
Cycle-Accurate System-Level Modeling and Performance Evaluation by
Coppola and Grammatikakis
This chapter discusses how to use system-level modeling approaches at the cycle-accurate micro-archi-
tectural level to do final design architecture iterations and ensure conformance to timing and perform-
ance specifications.
Micro-Architectural Power Estimation and Optimization by Macii, Mehra,
and Poncino
This chapter discusses the state of the art in estimating power at the micro-architectural level, consisting
of major design blocks such as data paths, memories, and interconnect. Ad hoc solutions for optimizing
both specific components and the whole design are surveyed.
Design Planning by Otten
This chapter discusses the topics of physical floor planning and its evolution over the years, from dealing
with rectangular blocks in slicing structures to more general mathematical techniques for optimizing
physical layout while meeting a variety of criteria, especially timing and other constraints.
Logical Verification
Design and Verification Languages by Edwards
This chapter discusses the two main HDLs in use — VHDL and Verilog, and how they meet the require-
ments for design and verification flows. More recent evolutions in languages, such as SystemC, System
Verilog, and verification languages such as OpenVera, e, and PSL are also described.
Digital Simulation by Sanguinetti
This chapter discusses logic simulation algorithms and tools, as these are still the primary tools used to
verify the logical or functional correctness of a design.
Using Transactional Level Models in a SoC Design Flow by Clouard, Ghenassia,
Maillet-Contoz, and Strassen
This chapter discusses a real design flow at a real IC design company to illustrate the building, deploy-
ment, and use of transactional-level models to simulate systems at a higher level of abstraction, with
much greater performance than at register transfer level (RTL), and to verify functional correctness and
validate system performance characteristics.
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Assertion-Based Verification by Foster and Marschner
This chapter introduces the relatively new topic of assertion-based verification, which is useful for captur-
ing design intent and reusing it in both dynamic and static verification methods. Assertion libraries such
as OVL and languages such as PSL and System Verilog assertions are used for illustrating the concepts.
Hardware Acceleration and Emulation by Bershteyn and Turner
This chapter discusses HW-based systems including FPGA, processor based accelerators/emulators, and
FPGA prototypes for accelerated verification. It compares the characteristics of each type of system and
typical use models.
Formal Property Verification by Fix and McMillan
This chapter discusses the concepts and theory behind formal property checking, including an overview
of property specification and a discussion of formal verification technologies and engines.
Test
Design-for-Test by Koenemann
This chapter discusses the wide variety of methods, techniques, and tools available to solve design-for-test
(DFT) problems. This is a huge area with a huge variety of techniques, many of which are implemented in
tools that dovetail with the capabilities of the physical test equipment. The chapter surveys the specialized
techniques required for effective DFT with special blocks such as memories as well as general logic cores.
Automatic Test Pattern Generation by Wang and Cheng
This chapter starts with the fundamentals of fault modeling and combinational ATPG concepts. It moves
on to gate-level sequential ATPG, and discusses satisfiability (SAT) methods for circuits. Moving on
beyond traditional fault modeling, it covers ATPG for cross talk faults, power supply noise, and applica-
tions beyond manufacturing test.
Analog and Mixed-Signal Test by Kaminska
This chapter first overviews the concepts behind analog testing, which include many characteristics of cir-
cuits that must be examined. The nature of analog faults is discussed and a variety of analog test equip-
ment and measurement techniques surveyed. The concepts behind analog built-in-self-test (BIST) are
reviewed and compared with the digital test.
RTL to GDS-II, or Synthesis, Place, and Route
Design Flows by Hathaway, Stok, Chinnery, and Keutzer
The RTL to GDSII flow has evolved considerably over the years, from point tools hooked loosely together,
to a more integrated set of tools for design closure. This chapter addresses the design flow challenges
based on the rising interconnect delays and new challenges to achieve closure.
Logic Synthesis by Khatri and Shenoy
This chapter provides an overview and survey of logic synthesis, which has since the early 1980s, grown
to be the vital center of the RTL to GDSII design flow for digital design.
Overview 1-9
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Power Analysis and Optimization from Circuit to Register Transfer Levels by
Monteiro, Patel, and Tiwari
Power has become one of the major challenges in modern IC design. This chapter provides an overview
of the most significant CAD techniques for low power, at several levels of abstraction.
Equivalence Checking by Kuehlmann and Somenzi
Equivalence checking can formally verify whether two design specifications are functionally equivalent.
The chapter defines the equivalence-checking problem, discusses the foundation for the technology, and
then discusses the algorithms for combinational and sequential equivalence checking.
Digital Layout — Placement by Reda and Kahng
Placement is one of the fundamental problems in automating digital IC layout. This chapter reviews the
history of placement algorithms, the criteria used to evaluate quality of results, many of the detailed algo-
rithms and approaches, and recent advances in the field.
Static Timing Analysis by Sapatnekar
This chapter overviews the most prominent techniques for static timing analysis. It then outlines issues
relating to statistical timing analysis, which is becoming increasingly important to handle process varia-
tions in advanced IC technologies.
Structured Digital Design by Mo and Brayton
This chapter covers the techniques for designing regular structures, including data paths, programable
logic arrays, and memories. It extends the discussion to include regular chip architectures such as gate
arrays and structured ASICs.
Routing by Scheffer
Routing continues from automatic placement as a key step in IC design. Routing creates all the wires nec-
essary to connect all the placed components while obeying the process design rules. This chapter discusses
various types of routers and the key algorithms.
Exploring Challenges of Libraries for Electronic Design by Hogan and Becker
This chapter discusses the factors that are most important and relevant for the design of libraries and IP,
including standard cell libraries, cores, both hard and soft, and the design and user requirements for the
same. It also places these factors in the overall design chain context.
Design Closure by Cohn and Osler
This chapter describes the common constraints in VLSI design, and how they are enforced through the
steps of a design flow that emphasizes design closure. A reference flow for ASIC is used and illustrated.
Future design closure issues are also discussed.
Tools for Chip-Package Codesign by Franzon
Chip-package co-design refers to design scenarios, in which the design of the chip impacts the package
design or vice versa. This chapter discusses the drivers for new tools, the major issues, including mixed-
signal needs, and the major design and modeling approaches.
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Design Databases by Bales
The design database is at the core of any EDA system. While it is possible to build a bad EDA tool or flow
on any database, it is impossible to build a good EDA tool or flow on a bad database. This chapter
describes the place of a design database in an integrated design system. It discusses databases used in the
past, those currently in use as well as emerging future databases.
FPGA Synthesis and Physical Design by Betz and Hutton
Programmable logic devices, both complex programmable logic devices (CPLDs) and FPGAs, have
evolved from implementing small glue-logic designs to large complete systems. The increased use of such
devices — they now are the majority of design starts — has resulted in significant research in CAD algo-
rithms and tools targeting programmable logic. This chapter gives an overview of relevant architectures,
CAD flows, and research.
Analog and Mixed-Signal Design
Analog Simulation: Circuit Level and Behavioral Level by Mantooth and
Roychowdhury
Circuit simulation has always been a crucial component of analog system design and is becoming even
more so today. In this chapter, we provide a quick tour of modern circuit simulation. This includes start-
ing on the ground floor with circuit equations, device models, circuit analysis, more advanced analysis
techniques motivated by RF circuits, new advances in circuit simulation using multitime techniques, and
statistical noise analysis.
Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits by
Gielen and Philips
This chapter provides an overview of the modeling and simulation methods that are needed to design and
embed analog and RF blocks in mixed-signal integrated systems (ASICs, SoCs, and SiPs). The role of
behavioral models and mixed-signal methods involving models at multiple hierarchical levels is covered.
The generation of performance models for analog circuit synthesis is also discussed.
Layout Tools for Analog ICs and Mixed-Signal SoCs: A Survey by Rutenbar
and Cohn
Layout for analog circuits has historically been a time-consuming, manual, trial-and-error task. In this
chapter, we cover the basic problems faced by those who need to create analog and mixed-signal layout,
and survey the evolution of design tools and geometric/electrical optimization algorithms that have been
directed at these problems.
Physical Verification
Design Rule Checking by Todd, Grodd, and Fetty
After the physical mask layout is created for a circuit for a specific design process, the layout is measured
by a set of geometric constraints or rules for that process. The main objective of design rule checking is
to achieve high overall yield and reliability. This chapter gives an overview of design rule checking (DRC)
concepts and then discusses the basic verification algorithms and approaches.
Overview 1-11
CRC_7923_ch001.qxd 2/20/2006 2:35 PM Page 11

Resolution Enhancement Techniques and Mask Data Preparation by
Schellenberg
With more advanced IC fabrication processes, new physical effects, which could be ignored in the past,
are being found to have a strong impact on the formation of features on the actual silicon wafer. It is now
essential to transform the final layout via new tools in order to allow the manufacturing equipment to
deliver the new devices with sufficient yield and reliability to be cost-effective. This chapter discusses the
compensation schemes and mask data conversion technologies now available to accomplish the new
design for manufacturability (DFM) goals.
Design for Manufacturability in the Nanometer Era by Dragone, Guardiani,
and Strojwas
Achieving high yielding designs in state-of-the-art IC process technology has become an extremely chal-
lenging task. Design for manufacturability includes many techniques to modify the design of ICs in order
to improve functional and parametric yield and reliability. This chapter discusses yield loss mechanisms
and fundamental yield modeling approaches. It then discusses techniques for functional yield maximiza-
tion and parametric yield optimization. Finally, DFM-aware design flows and the outlook for future DFM
techniques are discussed.
Design and Analysis of Power Supply Networks by Blaauw, Pant, Chaudhry,
and Panda
This chapter covers design methods, algorithms, tools for designing on-chip power grids, and networks.
It includes the analysis and optimization of effects such as voltage drop and electro-migration.
Noise Considerations in Digital ICs by Kariat
On-chip noise issues and impact on signal integrity and reliability are becoming a major source of prob-
lems for deep submicron ICs. Thus the methods and tools for analyzing and coping with them, which are
discussed in this chapter, have been gaining importance in recent years.
Layout Extraction by Kao, Lo, Basel, Singh, Spink, and Scheffer
Layout extraction is the translation of the topological layout back into the electrical circuit it is intended
to represent. This chapter discusses the distinction between designed and parasitic devices, and discusses
the three major parts of extraction: designed device extraction, interconnect extraction, and parasitic
device extraction.
Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis,
and Validation by Vergese and Nagata
This chapter describes the impact of noise coupling in mixed-signal ICs, and reviews techniques to
model, analyze, and validate it. Different modeling approaches and computer simulation methods are
presented, along with measurement techniques. Finally, the chapter reviews the application of substrate
noise analysis to placement and power distribution synthesis.
Technology Computer-Aided Design
Process Simulation by Johnson
Process simulation is the modeling of the fabrication of semiconductor devices such as transistors.
The ultimate goal is an accurate prediction of the active dopant distribution, the stress distribution,
CRC_7923_ch001.qxd 2/20/2006 2:35 PM Page 12

and the device geometry. This chapter discusses the history, requirements, and development of
process simulators.
Device Modeling — from Physics to Electrical Parameter Extraction by Dutton,
Choi, and Kan
Technology files and design rules are essential building blocks of the IC design process. Development of
these files and rules involves an iterative process that crosses the boundaries of technology and device
development, product design, and quality assurance. This chapter starts with the physical description of
IC devices and describes the evolution of TCAD tools.
High-Accuracy Parasitic Extraction by Kamon and Iverson
This chapter describes high-accuracy parasitic extraction methods using fast integral equation and ran-
dom walk-based approaches.
References
[1] A. Sangiovanni-Vincentelli, The tides of EDA, IEEE Des. Test Comput., 20, 59–75, 2003.
[2] A. Kuelhmann, Ed., 20 Years of ICCAD, Kluwer Academic Publishers (now Springer), Dordrecht,
2002.
Overview 1-13
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2
The Integrated Circuit
Design Process and
Electronic Design
Automation
2.1
2.2 Verification ........................................................................ 2-3
2.3 Implementation ................................................................ 2-5
2.4 Design for Manufacturing .............................................. 2-11
2.1 Introduction
In this chapter, we describe the design process, its major stages, and how electronic design automation
(EDA) tools fit into these processes. We also examine the interfaces between the major integrated circuit
(IC) design stages as well as the kind of information — both abstractions upwards, and detailed design
and verification information downward — that must flow between stages. We assume Complementary
Metal Oxide Semiconductor (CMOS) is the basis for all technologies.
We will illustrate with a continuing example. A company wishes to create a new system on chip (SoC). The
company assembles a product team, consisting of a project director, system architects, system verification engi-
neers, circuit designers (both digital and analog), circuit verification engineers, layout engineers, and manufac-
turing process engineers. The product team determines the target technology and geometry as well as the
fabrication facility or foundry. The system architects initially describe the system-level design (SLD) through a
transaction-levelspecificationinalanguagesuchasC⫹⫹,SystemC,orEsterel.Thesystemverificationengineers
determine the functional correctness of the SLD through simulation.The engineers validate the transaction pro-
cessing through simulation vectors. They monitor the results for errors. Eventually, these same engineers would
simulate the process with an identical set of vectors through the system implementation to see if the specifica-
tion and the implementation match. There is some ongoing research to check this equivalence formally.
The product team partitions the SLD into functional units and hands these units to the circuit design
teams. The circuit designers describe the functional intent through a high-level design language (HDL).
The most popular HDLs are Verilog and VHDL. SystemVerilog is a new language, adopted by the IEEE,
which contains design, testbench, and assertion syntax. These languages allow the circuit designers to
express the behavior of their design using high-level functions such as addition and multiplication. These
languages allow expression of the logic at the register transfer level (RTL), in the sense that an assignment
of registers expresses functionality. For the analog and analog mixed signal (AMS) parts of the design,
there are also high-level design languages such as Verilog-AMS and VHDL-AMS. Most commonly, circuit
2-1
Robert Damiano
Synopsys Inc.
Hillsboro, Oregon
Raul Camposano
Synopsys Inc.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 1
Introduction ...................................................................... 2-1

designers use Simulation Program with Integrated Circuit Emphasis (SPICE) transistor models and
netlists to describe analog components. However, high-level languages provide an easier interface
between analog and digital segments of the design and they allow writing higher-level behavior of the
analog parts. Although the high-level approaches are useful as simulation model interfaces, there remains
no clear method of synthesizing transistors from them. Therefore, transistor circuit designers usually
depend on schematic capture tools to enter their data.
The design team must consider functional correctness, implementation closure (reaching the priori-
tized goals of the design), design cost, and manufacturability of a design. The product team takes into
account risks and time to market as well as choosing the methodology. Anticipated sales volume can
reflect directly on methodology; whether it is better to create a fully custom design, semicustom design,
use standard cells , gate arrays, or a field programmable gate array (FPGA). Higher volume mitigates the
higher cost of fully custom or semicustom design, while time to market might suggest using an FPGA
methodology. If implementation closure for power and speed is tantamount, then an FPGA methodol-
ogy might be a poor choice. Semicustom designs, depending on the required volume, can range from
microprocessor central processor units (CPUs), digital signal processors (DSPs), application-specific
standard parts (ASSP) or application-specific integrated circuits (ASIC). In addition, for semicustom
designs, the company needs to decide whether to allow the foundry to implement the layout, or whether
the design team should use customer owned tools (COT). We will assume that our product team chooses
semicustom COT designs. We will mention FPGA and fully custom methodologies only in comparison.
In order to reduce cost, the product team may decide that the design warrants reuse of intellectual
property (IP). Intellectual property reuse directly addresses the increasing complexity of design as
opposed to feature geometry size. Reuse also focuses on attaining the goals of functional correctness. One
analysis estimates that it takes 2000 engineering years and 1 trillion simulation vectors to verify 25 mil-
lion lines of RTL code. Therefore, verified IP reuse reduces cost and time to market. Moreover, IP blocks
themselves have become larger and more complex. For example, the 1176JZ-S ARM core is 24 times larger
than the older 7TDI-S ARM core. The USB 2.0 Host is 23 times larger than the Universal Serial Bus (USB)
1.1 Device. PCI Express is 7.5 times larger than PCI v 1.1.
Another important trend is that SoC-embedded memories are an increasingly large part of the SoC
real estate. While in 1999, 20% of a 180-nm SoC was embedded memory, roadmaps project that by 2005,
embedded memory will consume 71% of a 90-nm SoC. These same roadmaps indicate that by 2014,
embedded memory will grow to 94% of a 35-nm SoC.
Systems on chips typically contain one or more CPUs or DSPs (or both), cache, a large amount of
embedded memory and many off-the-shelf components such as USB, Universal Asynchronous Receiver-
differentiating part of the SoC contains the new designed circuits in the product.
The traditional semicustom IC design flow typically comprises up to 50 steps. On the digital side of
design, the main steps are functional verification, logical synthesis, design planning, physical implemen-
tation which includes clock-tree synthesis, placement and routing, extraction, design rules checking
(DRC) and layout versus schematic checking (LVS), static timing analysis, insertion of test structures, and
test pattern generation. For analog designs, the major steps are as follows: schematic entry, SPICE simu-
lation, layout, layout extraction, DRC, and LVS. SPICE simulations can include DC, AC, and transient
analysis, as well as noise, sensitivity, and distortion analysis. Analysis and implementation of corrective
procedures for the manufacturing process such as mask synthesis and yield analysis, are critical at smaller
geometries. In order to verify an SoC system where many components reuse IP, the IP provider may sup-
ply verification IP, monitors, and checkers needed by system verification.
There are three basic areas where EDA tools assist the design team. Given a design, the first is verifica-
tion of functional correctness. The second deals with implementation of the design. The last area deals
with analysis and corrective procedures so that the design meets all manufacturability specifications.
Verification, layout, and process engineers on the circuit design team essentially own these three steps.
SPICE reportedly is an acronym for Simulation Program with Integrated Circuit Emphasis
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 2
Transmitter (UART), Serial Advanced Technology Attachment (SATA), and Ethernet (cf. Figure 2.1). The

2.2 Verification
The design team attempts to verify that the design under test (DUT) functions correctly. For RTL designs,
verification engineers rely highly on simulation at the cycle level. After layout, EDA tools, such as equiva-
lence checking, can determine whether the implementation matches the RTL functionality. After layout, the
design team must check that there are no problem delay paths.A static timing analysis tool can facilitate this.
The team also needs to examine the circuit for noise and delay due to parasitics. In addition, the design must
obey physical rules for wire spacing, width, and enclosure as well as various electrical rules. Finally, the
design team needs to simulate and check the average and transient power. For transistor circuits, the design
team uses SPICE circuit simulation or fast SPICE to determine correct functionality, noise, and power.
meets the design intent. The verification engineers apply a set of vectors, called a testbench, to the design
through an event-driven simulator, and compare the results to a set of expected outputs. The quality of
the verification depends on the quality of the testbench. Many design teams create their testbench by sup-
plying a list of the vectors, a technique called directed test. For a directed test to be effective, the design
team must know beforehand what vectors might uncover bugs. This is extremely difficult since complex
sequences of vectors are necessary to find some corner case errors. Therefore, many verification engineers
create testbenches that supply stimulus through random vectors with biased inputs, such as the clock or
reset signal. The biasing increases or decreases the probability of a signal going high or low. While a purely
random testbench is easy to create, it suffers from the fact that vectors may be illegal as stimulus. For bet-
ter precision and wider coverage, the verification engineer may choose to write a constrained random
testbench. Here, the design team supplies random input vectors that obey a set of constraints.
The verification engineer checks that the simulated behavior does not have any discrepancies from the
expected behavior. If the engineer discovers a discrepancy, then the circuit designer modifies the HDL and
the verification engineer resimulates the DUT. Since exhaustive simulation is usually impossible, the
design team needs a metric to determine quality. One such metric is coverage. Coverage analysis consid-
ers how well the test cases stimulate the design. The design team might measure coverage in terms of
number of lines of RTL code exercised, whether the test cases take each leg of each decision, or how many
“reachable” states encountered.
Another important technique is for the circuit designer to add assertions within the HDL. These asser-
tions monitor whether internal behavior of the circuit is acting properly. Some designers embed tens of
thousands of assertions into their HDL. Languages like SystemVerilog have extensive assertion syntax based
The Integrated Circuit Design Process and Electronic Design Automation 2-3
Processors
(CPUs, DSPs,..)+
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FIGURE 2.1. SoC with IP.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 3
We first look at digital verification (cf. Figure 2.2). RTL simulation verifies that the DUT behavior

on linear temporal logic. Even for languages without the benefit of assertion syntax, tool-providers supply
an application program interface (API), which allows the design team to build and attach its own monitors.
The verification engineer needs to run a large amount of simulation, which would be impractical if not
for compute farms. Here, the company may deploy thousands of machines, 24/7, to enable the designer
to get billions of cycles a day; sometimes the machines may run as many as 200 billion cycles a day. Best
design practices typically create a highly productive computing environment. One way to increase
throughput is to run a cycle simulation by taking a subset of the chosen verification language which is
both synchronous and has a set of registers with clear clock cycles. This type of simulation assumes a uni-
formity of events and typically uses a time wheel with gates scheduled in a breadth first manner.
Another way to tackle the large number of simulation vectors during system verification is through
emulation or hardware acceleration. These techniques use specially configured hardware to run the sim-
ulation. In the case of hardware acceleration, the company can purchase special-purpose hardware, while
in the case of emulation the verification engineer uses specially configured FPGA technology. In both
cases, the system verification engineer must synthesize the design and testbench down to a gate-level
model. Tools are available to synthesize and schedule gates for the hardware accelerator. In the case of an
FPGA emulation system, tools can map and partition the gates for the hardware.
Of course, since simulation uses vectors, it is usually a less than exhaustive approach. The verification
engineer can make the process complete by using assertions and formal property checking. Here, the engi-
neer tries to prove that an assertion is true or to produce a counterexample. The trade-off is simple.
Simulation is fast but by definition incomplete, while formal property checking is complete but may be very
slow. Usually, the verification engineer runs constrained random simulation to unearth errors early in the
verification process. The engineer applies property checking to corner case situations that can be extremely
hard for the testbench to find. The combination of simulation and formal property checking is very power-
ful. The two can even be intermixed, by allowing simulation to proceed for a set number of cycles and then
exhaustively looking for an error for a different number of cycles. In a recent design, by using this hybrid
approach , a verification engineer found an error 21,000 clock cycles from an initial state. Typically, formal
verification works well on specific functional units of the design. Between the units, the system engineers
use an “assume/guarantee” methodology to establish block pre- and postconditions for system correctness.
During the implementation flow, the verification engineer applies equivalence checking to determine
whether the DUT preserves functional behavior. Note that functional behavior is different from func-
tional intent. The verification engineer needs RTL verification to compare functional behavior with func-
tional intent. Equivalence checking is usually very fast and is a formal verification technology, which is
exhaustive in its analysis. Formal methods do not use vectors.
For transistor-level circuits, such as analog, memory, and radio frequency (RF), the event-driven verifi-
Testbench infrastructure
Classes Scenarios
Constrained random
Simulations
Assertions
Properties
Constraints
Coverage
metrics
Functional
Code
Feedback
Formal verification
Topology checks
Formal property
Equivalence
checking
FIGURE 2.2. Digital Simulation/Formal Verification.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 4
cation techniques suggested above do not suffice (cf. Figure 2.3). The design team needs to compute signals

accurately through SPICE circuit simulation. SPICE simulation is very time consuming because the algo-
rithm solves a system of differential equations. One way to get around this cost is to select only a subset of
transistors, perform an extraction of the parasitics, and then simulate the subset with SPICE. This reduction
gives very accurate results for the subset, but even so, the throughput is still rather low. Another approach is
to perform a fast SPICE simulation. This last SPICE approach trades some accuracy for a significant increase
in throughput. The design team can also perform design space exploration by simulating various constraint
values on key goals such as gain or phase margin to find relatively optimal design parameters. The team ana-
lyzes the multiple-circuit solutions and considers the cost trade-offs.A new generation of tools performs this
“design exploration” in an automatic manner. Mixed-level simulation typically combines RTL, gate and
transistor parts of the design and uses a communication back-plane to run the various simulations and
share input and output values.
Finally, for many SoCs, both hardware and software comprise the real system. System verification engi-
neers may run a hardware–software co-simulation before handing the design to a foundry. All simulation
system components mentioned can be part of this co-simulation. In early design stages, when the hard-
ware is not ready, the software can simulate (“execute”) an instruction set model (ISM), a virtual proto-
type (model), or an early hardware prototype typically implemented in FPGAs.
2.3 Implementation
This brings us to the next stage of the design process, the implementation and layout of the digital design.
Circuit designers implement analog designs by hand. Field programmable gate array technologies usually
have a single basic combinational cell, which can form a variety of functions by constraining inputs. Layout
and process tools are usually proprietary to the FPGA family and manufacturer. For semicustom design, the
manufacturer supplies a precharacterized cell library, either standard cell or gate array. In fact, for a given
technology, the foundry may supply several libraries, differing in power, timing, or yield. The company
decides on one or more of these as the target technology. One twist on the semicustom methodology is
structured ASIC. Here, a foundry supplies preplaced memories, pad-rings and power grids as well as some-
times preplaced gate array logic, similar to the methodology employed by FPGA families. The company can
use semicustom techniques for the remaining combinational and sequential logic.The goal is to reduce non-
recurring expenses by limiting the number of mask-sets needed and by simplifying physical design.
By way of contrast, in a fully custom methodology, one tries to gain performance and limit power con-
sumption by designing much of the circuit as transistors. The circuit designers keep a corresponding RTL
Accuracy
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FIGURE 2.3. Transistor simulation with parasitics.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 5
© 2006 by Taylor Francis Group, LLC

design. The verification engineer simulates the RTL and extracts a netlist from the transistor description.
Equivalence checking compares the extracted netlist to the RTL. The circuit designer manually places and
routes the transistor-level designs. Complex high-speed designs, such as microprocessors, sometimes use
full custom methodology, but the design costs are very high. The company assumes that the high volume
will amortize the increased cost. Fully custom designs consider implementation closure for power and
speed as most important. At the other end of the spectrum, FPGA designs focus on design cost and time
to market. Semicustom methodology tries to balance the goals of timing and power closure with design
In the semicustom implementation flow, one first attempts to synthesize the RTL design into a mapped
netlist. The circuit designers supply their RTL circuit along with timing constraints. The timing con-
straints consist of signal arrival and slew (transition) times at the inputs, and required times and loads
(capacitances) at the outputs. The circuit designer identifies clocks as well as any false or multiple-cycle
paths. The technology library is usually a file that contains a description of the function of each cell along
with delay, power, and area information. Either the cell description contains the pin-to-pin delay repre-
sented as look-up table functions of input slew, output load, and other physical parameters such as volt-
age and temperature, or as polynomial functions that best fit the parameter data. For example, foundries
provide cell libraries in Liberty or OLA (Open Library Application Programming Interface) formats. The
foundry also provides a wire delay model, derived statistically from previous designs. The wire delay
model correlates the number of sinks of a net to capacitance and delay.
Several substages comprise the operation of a synthesis tool. First, the synthesis tool compiles the RTL
into technology-independent cells and then optimizes the netlist for area, power, and delay. The tool
maps the netlist into a technology. Sometimes, synthesis finds complex functions such as multipliers and
adders in parameterized (area/timing) reuse libraries. For example, the tool might select a Booth multi-
plier from the reuse library to improve timing. For semicustom designs, the foundry provides a standard
cell or gate array library, which describes each functional member. In contrast, the FPGA supplier
describes a basic combinational cell from which the technology mapping matches functional behavior of
subsections of the design. To provide correct functionality, the tool may set several pins on the complex
gates to constants. A post-process might combine these functions for timing, power, or area.
A final substage tries to analyze the circuit and performs local optimizations that help the design meet its
timing, area and power goals. Note that due to finite number of power levels of any one cell, there are limits
to the amount of capacitance that functional cell types can drive without the use of buffers. Similar restric-
tions apply to input slew (transition delay). The layout engineer can direct the synthesis tool by enhancing or
omitting any of these stages through scripted commands. Of course, the output must be a mapped netlist.
To get better timing results, foundries continue to increase the number of power variations for some
cell types. One limitation to timing analysis early in the flow is that the wire delay models are statisti-
cal estimates of the real design. Frequently, these wire delays can differ significantly from those found
after routing. One interesting approach to synthesis is to extend each cell of the technology library so
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FIGURE 2.4. Multi-objective implementation convergence.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 6
cost (cf. Figure 2.4).

that it has an infinite or continuous variation of power. This approach, called gain-based synthesis,
attempts to minimize the issue of inaccurate wire delay by assuming cells can drive any wire capaci-
tance through appropriate power level selection. In theory, there is minimal perturbation to the natu-
ral delay (or gain) of the cell. This technique makes assumptions such as that the delay of a signal is a
function of capacitance. This is not true for long wires where resistance of the signal becomes a factor.
In addition, the basic approach needs to include modifications for slew (transition delay).
To allow detection of manufacturing faults, the design team may add extra test generation circuitry.
Design for test (DFT) is the name given to the process of adding this extra logic (cf. Figure 2.5).
Sometimes, the foundry supplies special registers, called logic-sensitive scan devices. At other times, the
test tool adds extra logic called Joint Test Action Group (JTAG) boundary scan logic that feeds the regis-
ters. Later in the implementation process, the design team will generate data called scan vectors that test
equipment uses to detect manufacturing faults. Subsequently, tools will transfer these data to automatic
test equipment (ATE), which perform the chip tests.
As designs have become larger, so has the amount of test data. The economics of the scan vector pro-
duction with minimal cost and design impact leads to data compression techniques. One of most widely
used techniques is deterministic logic built in self-test(BIST). Here, a test tool adds extra logic on top of
the DFT to generate scan vectors dynamically.
Before continuing the layout, the engineer needs new sets of rules, dealing with the legal placement and
routing of the netlist. These libraries, in various exchange formats, e.g., LEF for logic, DEF for design and
PDEF for physical design, provide the layout engineer physical directions and constraints. Unlike the
technology rules for synthesis, these rules are typically model-dependent. For example, there may be
information supplied by the circuit designer about the placement of macros such as memories. The rout-
ing tool views these macros as blockages. The rules also contain information from the foundry.
Even if the synthesis tool preserved the original hierarchy of the design, the next stages of implemen-
tation need to view the design as flat. The design-planning step first flattens the logic and then partitions
the flat netlist as to assist placement and routing;—in fact, in the past, design planning was sometimes
known as floor planning. A commonly used technique is for the design team to provide a utilization ratio
to the design planner. The utilization ratio is the percentage of chip area used by the cells as opposed to
the nets. If the estimate is too high, then routing congestion may become a problem. If the estimate is too
low, then the layout could waste area. The design-planning tool takes the locations of hard macros into
account. These macros are hard in the sense that they are rectangular with a fixed length, fixed width, and
sometimes a fixed location on the chip. The design-planning tool also tries to use the logical hierarchy of
the design as a guide to the partitioning. The tool creates, places and routes a set of macros that have fixed
lengths, widths, and locations. The tool calculates timing constraints for each macro and routes the power
Design for testability
ATPG
SoC level BIST
Integration with ATE
FIGURE 2.5. Design for test.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 7

and ground grids. The power and ground grids are usually on the chip’s top levels of metal and then dis-
tributed to the lower levels. The design team can override these defaults and indicate which metal layers
should contain these grids. Sometimes design planning precedes synthesis. In these cases, the tool parti-
tions the RTL design and automatically characterizes each of the macros with timing constraints.
After design planning, the layout engineer runs the physical implementation tools on each macro. First,
the placer assigns physical locations to each gate of the macro. The placer typically moves gates while min-
imizing some cost, e.g., wire length or timing. Legalization follows the coarse placement to make sure the
placed objects fit physical design rules. At the end of placement, the layout engineer may run some more
synthesis, like re-sizing of gates. One of the major improvements to placement over the last decade is the
emergence of physical synthesis. In physical synthesis, the tool interleaves synthesis and placement. Recall
that previously, logic synthesis used statistical wire capacitance. Once the tool places the gates, it can per-
form a global route and get capacitances that are more accurate for the wires, based on actual placed loca-
tions. The physical synthesis tool iterates this step and provides better timing and power estimates.
Next, the layout engineer runs a tool that buffers and routes the clock tree. Clock-tree synthesis
attempts to minimize the delay while assuring that skew, that is the variation in signal transport time
from the clock to its corresponding registers, is close to zero.
Routing the remaining nets comes after clock-tree synthesis. Routing starts with a global analysis called
global route. Global route creates coarse routes for each signal and its outputs. Using the global routes as
a guide, a detailed routing scheme, such as a maze channel or switchbox, performs the actual routing. As
with the placement, the tool performs a final legalization to assure that the design obeys physical rules.
One of the major obstacles to routing is signal congestion. Congestion occurs when there are too many
wires competing for a limited amount of chip wire resource. Remember that the design team gave the
design planner a utilization ratio in the hope of avoiding this problem.
Both global routing and detailed routing take the multilayers of the chip into consideration. For exam-
ple, the router assumes that the gates are on the polysilicon layer, while the wires connect the gates
through vias on 3–8 layers of metal. Horizontal or vertical line segments comprise the routes, but some
recent work allows 45° lines for some foundries. As with placement, there may be some resynthesis, such
as gate resizing, at the end of the detailed routing stage.
Once the router finishes, an extraction tool derives the capacitances, resistances, and inductances. In a
two-dimensional (2-D) parasitic extraction, the extraction tool ignores 3-D details and assumes that each
chip level is uniform in one direction. This produces only approximate results. In the case of the much
slower 3-D parasitic extraction, the tool uses 3-D field solvers to derive very accurate results. A 2½-D
extraction tool compromises between speed and accuracy. By using multiple passes, it can access some of
the 3-D features. The extraction tool places its results in a standard parasitic exchange format file (SPEF).
During the implementation process, the verification engineer continues to monitor behavioral consis-
tency through equivalence checking and using LVS comparison. The layout engineer analyzes timing and
signal integrity issues through timing analysis tools, and uses their results to drive implementation deci-
sions. At the end of the layout, the design team has accurate resistances, capacitances, and inductances for
the layout. The system engineer uses a sign-off timing analysis tool to determine if the layout meets tim-
ing goals. The layout engineer needs to run a DRC on the layout to check for violations.
Both the Graphic Data System II (GDSII) and the Open Artwork System Interchange Standard
(OASIS) are databases for shape information to store a layout. While the older GDSII was the database of
choice for shape information, there is a clear movement to replace it by the newer, more efficient OASIS
database. The LVS tool checks for any inconsistencies in this translation.
What makes the implementation process so difficult is that multiple objectives need consideration. For
example, area, timing, power, reliability, test, and yield goals might and usually cause conflict with each
other. The product team must prioritize these objectives and check for implementation closure.
Timing closure—that is meeting all timing requirements—by itself is becoming increasingly difficult and
offers some profound challenges. As process geometry decrease, the significant delay shifts from the cells to
the wires. Since a synthesis tool needs timing analysis as a guide and routing of the wires does not occur until
after synthesis, we have a chicken and egg problem. In addition, the thresholds for noise sensitivity also
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 8

shrink with smaller geometries. This along with increased coupling capacitances, increased current densi-
ties and sensitivity to inductance, make problems like crosstalk and voltage (IR) drop increasingly familiar.
Since most timing analysis deals with worst-case behavior, statistical variation and its effect on yield add
to the puzzle. Typically timing analysis computes its cell delay as function of input slew (transition delay)
and output load (output capacitance or RC). If we add the effects of voltage and temperature variations as
well as circuit metal densities, timing analysis gets to be very complex. Moreover, worst-case behavior may
not correlate well with what occurs empirically when the foundry produces the chips. To get a better pre-
dictor of parametric yield, some layout engineers use statistical timing analysis. Here, rather than use sin-
gle numbers (worst case, best case, corner case, nominal) for the delay-equation inputs, the timing analysis
tool selects probability distributions representing input slew, output load, temperature, and voltage among
others. The delay itself becomes a probability distribution. The goal is to compute the timing more accu-
rately in order to create circuits with smaller area and lower power but with similar timing yield.
Reliability is also an important issue with smaller geometries. Signal integrity deals with analyzing
what were secondary effects in larger geometries. These effects can produce erratic behavior for chips
manufactured in smaller geometries. Issues such as crosstalk, IR drop, and electromigration are factors
that the design team must consider in order to produce circuits that perform correctly.
Crosstalk noise can occur when two wires are close to each other (cf. Figure 2.6). One wire, the aggressor,
switches while the victim signal is in a quiet state or making an opposite transition. In this case, the aggres-
sor can force the victim to glitch. This can cause a functional failure or can simply consume additional
power. Gate switching draws current from the power and ground grids. That current, together with the wire
resistance in the grids, can cause significant fluctuations in the power and ground voltages supplied to gates.
This problem, called IR drop, can lead to unpredictable functional errors.Very high frequencies can produce
high current densities in signals and power lines, which can lead to the migration of metal ions. This power
electromigration can lead to open or shorted circuits and subsequent signal failure.
Power considerations are equally complex. As the size of designs grow and geometries shrink, power
increases. This can cause problems for batteries in wireless and hand-held devices, and thermal
management in microprocessor, graphic and networking applications. Power consumption falls into two
One easy way to reduce dynamic power is to decrease voltage. However, decreased voltage leads to smaller
noise margins and less speed.
Smaller
geometry
Crosstalk noise
Crosstalk slow-down
Delta delay
No crosstalk
Cg
Crosstalk speed-up
Delta delay
Cc
Cg
Cg
Aggressor
Victim
FIGURE 2.6. Crosstalk.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 9
areas: dynamic power (cf. Figure 2.7), the power consumed when devices switch value; and leakage power
with increased capacitance and voltage. Therefore, as designs become larger, dynamic power increases.
(cf. Figure 2.8), the power leaked through the transistor. Dynamic power consumption grows directly

A series of novel design and transistor innovations can reduce the power consumption. These include
operand isolation, clock gating, and voltage-islands. Timing and power considerations are very often in
conflict with each other, so the design team must employ these remedies carefully.
A design can have part of its logic clock-gated by using logic to enable the bank of registers. The logic
driven by the registers is quiescent until the clock-gated logic enables the registers. Latches at the input
can isolate parts of a design that implement operations (e.g. an arithmetic logic unit (ALU)), when results
are unnecessary for correct functionality, thus preventing unnecessary switching. Voltage-islands help
resolve the timing vs. power conflicts. If part of a design is timing critical, a higher voltage can reduce the
delay. By partitioning the design into voltage-islands, one can use lower voltage in all but the most tim-
ing-critical parts of the design. An interesting further development is dynamic voltage/frequency scaling,
which consists of scaling the supply voltage and the speed during operation to save power or increase per-
formance temporarily.
Timing

signal
integrity
Extraction
ATPG
physical verification
Synthesis
Power
Test
Datapath
Design planning
RTL clock-gating
G_CLK
Register
bank
Latch
EN
CLK
D_IN D_OUT
V1
V3
V2
Voltage islands
Multi-voltage
V1, V2
V1, V4
V3
Multi-supply
f = ab + c (b + d)
f
d
b
b
a
c
f = b(a + c) + cd
f
a
c
c
d
b
Gate-level optimization
Physical
implementation
FIGURE 2.7. Dynamic power management.
Timing
and
signal
integrity
Timing
and
signal
integrity
Extraction
ATPG
Physical verification
Physical
implementation
Synthesis
Synthesis
Power
Test
Datapath
Power gating
D Q
CLK Sleep Wake-up
Multi-threshold
Delay
Leakage
current
Design planning
Design planning
FIGURE 2.8. Static power management (leakage).
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 10

The automatic generation of manufacturing fault detection tests was one of the first EDA tools. When
a chip fails, the foundry wants to know why. Test tools produce scan vectors that can identify various
manufacturing faults within the hardware. The design team translates the test vectors to standard test
data format and the foundry can inject these inputs into the failed chip through automated test equip-
ment (ATE). Remember that the design team added extra logic to the netlist before design planning, so
that test equipment could quickly insert the scan vectors, including set values for registers, into the chip.
The most common check is for stuck at 0 or stuck at 1 faults where the circuit has an open or short at a
particular cell. It is not surprising that smaller geometries call for more fault detection tests. An integra-
tion of static timing analysis with transition/path delay fault automatic test pattern generation (ATPG)
can help, for example, to detect contact defects; while extraction information and bridging fault ATPG
can detect metal defects.
Finally, the design team should consider yield goals. Manufacturing becomes more difficult as geometries
shrink. For example, thermal stress may create voids in vias. One technique to get around this problem is to
minimize the vias inserted during routing, and for those inserted, to create redundant vias. Via doubling,
which converts a single via into multiple vias, can reduce resistance and produce better yield. Yield analysis
can also suggest wire spreading during routing to reduce cross talk and increase yield. Manufacturers also
add a variety of manufacturing process rules needed to guarantee good yield. These rules involve antenna
checking and repair through diode insertion as well as metal fill needed to produce uniform metal densities
necessary for copper wiring chemical–mechanical polishing (CMP). Antenna repair has little to do with
what we typically view as antennas. During the ion-etching process, charge collects on the wires connected
to the polysilicon gates. These charges can damage the gates. The layout tool can connect small diodes to the
interconnect wires as a discharge path.
Even with all the available commercial tools, there are times when layout engineers want to create their
own tool for analysis or small implementation changes. This is analogous to the need for an API in veri-
fication. Scripting language and C-language-based APIs for design databases such as MilkyWay and
OpenAccess are available. These databases supply the user with an avenue to both the design and rules.
The engineer can directly change and analyze the layout.
2.4 Design for Manufacturing
One of the newest areas for EDA tools is design for manufacturing. As in other areas, the driving force of
the complexity is the shrinking of geometries. After the design team translates their design to shapes, the
foundry must transfer those shapes to a set of masks. Electron beam (laser) equipment then creates the
physical masks for each layer of the chip from the mask information. For each layer of the chip, the foundry
applies photoresistive material, and then transfers the mask structures by the stepper optical equipment
onto the chip. Finally, the foundry etches the correct shapes by removing the excess photoresist material.
Since the stepper uses light for printing, it is important that the wavelength is small enough to transcribe
the features accurately. When the chip’s feature size was 250 nm, we could use lithography equipment that
produced light at a wavelength of 248 nm. New lithography equipment that produces light of lower wave-
length needs significant innovation and can be very expensive. When the feature geometry gets significantly
smaller than the wavelength, the detail of the reticles (fine lines and wires), transferred to the chip from the
mask can be lost. Electronic design automation tools can analyze and correct this transfer operation with-
This process uses resolution enhancement techniques and methods to provide dimensional accuracy.
One mask synthesis technique is optimal proximity correction (OPC). This process takes the reticles in the
GDSII or OASIS databases and modifies them by adding new lines and wires, so that even if the geometry is
smaller than the wavelength, optical equipment adequately preserves the details. This technique successfully
transfers geometric features of down to one-half of the wavelength of the light used. Of course given a fixed
wavelength, there are limits beyond which the geometric feature size is too small for even these tricks.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 11
out new equipment, by modifying the shapes data— a process known as mask, synthesis (cf. Figure 2.9).

For geometries of 90 nm and below, the lithography EDA tools combine OPC with other mask syn-
thesis approaches such as phase shift mask (PSM), off-axis illumination and assist features (AF). For
example, PSM is a technique where the optical equipment images dark features at critical dimensions
with 0° illumination on one side and 180° illumination on the other side. There are additional manufac-
turing process rules needed such as minimal spacing and cyclic conflict avoidance, to avoid situations
where the tool cannot map the phase.
In summary, lithography tools proceed through PSM, OPC, and AF to enhance resolution and make
the mask more resistive to process variations. The process engineer can perform a verification of silicon
vs. layout and a check of lithography rule compliance. If either fails, the engineer must investigate and
correct, sometimes manually. If both succeed, another EDA tool “fractures” the design, subdividing the
shapes into rectangles (trapezoids), which can be fed to the mask writing equipment. The engineer can
then transfer the final shapes file to a database, such as the manufacturing-electron-beam-exposure sys-
tem (MEBES). Foundry equipment uses the MEBES database (or other proprietary formats) to create the
physical masks. The process engineer can also run a“virtual”stepper tool to pre-analyze the various stages
of the stepper operation. After the foundry manufactures the masks, a mask inspection and repair step
ensures that they conform to manufacturing standards.
team would like to correlate some of the activities during route with actual yield. Problems with CMP, via
voids and cross talk can cause chips to unexpectedly fail. EDA routing tools offer some solutions in the
form of metal fill, via doubling and wire spacing. Library providers are starting to develop libraries for
higher yields that take into account several yield failure mechanisms. There are tools that attempt to cor-
relate these solutions with yield. Statistical timing analysis can correlate timing constraints to parametric
circuit yield.
Finally, the process engineer can use tools to predict the behavior of transistor devices or processes.
Technology computer aided design (TCAD) deals with the modeling and simulation of physical manu-
facturing process and devices. Engineers can model and simulate individual steps in the fabrication
process. Likewise, the engineer can model and simulate devices, parasitics or electrical/thermal proper-
ties, therefore providing insights into their electrical, magnetic or optical properties.
For example, because of packing density, foundries may switch isolation technology for an IC from the
local oxidation of silicon model toward the shallow trench isolation (STI) model. Under this model, the
Mask inspection
and repair
OPC
Mask layout verification
(MRC, LRC / SiVL)
Fracturing, mask writing
Mask OK?
Mask OK?
Yes
No
Wafer lithography and process
PSM
Mask OK?
Yes
No
t
Correct
FIGURE 2.9. Subwavelength: from layout to masks.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 12
Another area of design for manufacturing analysis is prediction of yield (cf. Figure 2.10). The design

process engineer can analyze breakdown stress, electrical behavior such as leakage, or material vs. process
dependencies. Technology computer aided design tools can simulate STI effects, extract interconnect par-
asitics, such as diffusion distance, and determine SPICE parameters.
References
[1] M. Smith, Application Specific Integrated Circuits, Addison-Wesley, Reading, MA, 1997.
[2] A. Kuehlmann, The Best of ICCAD, Kluwer Academic Publishers, Dordrecht, 2003.
[3] D. Thomas and P. Moorby, The Verilog Hardware Description Language, Kluwer Academic
Publishers, Dordrecht, 1996.
[4] D. Pellerin and D. Taylor, VHDL Made Easy, Pearson Education, Upper Saddle River, N.J., 1996.
[5] S. Sutherland, S. Davidson, and P. Flake, SystemVerilog For Design: A Guide to Using SystemVerilog
for Hardware Design and Modeling, Kluwer Academic Publishers, Dordrecht, 2004.
[6] T. Groetker, S. Liao, G. Martin, and S. Swan, System Design with SystemC, Kluwer Academic
[7] G. Peterson, P. Ashenden, and D. Teegarden, The System Designer’s Guide to VHDL-AMS, Morgan
Kaufman Publishers, San Francisco, CA, 2002.
[8] K. Kundert and O. Zinke, The Designer’s Guide to Verilog-AMS, Kluwer Academic Publishers,
Dordrecht, 2004.
[9] M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Kluwer
Academic Publishers, Dordrecht, 1998.
[10] J. Bergeron, Writing Testbenches, Kluwer Academic Publishers, Dordrecht, 2003.
[11] E. Clarke, O. Grumberg, and D. Peled, Model Checking, The MIT Press, Cambridge, MA, 1999.
[12] S. Huang and K. Cheng, Formal Equivalence Checking and Design Debugging, Kluwer Academic
[13] R. Baker, H. Li, and D Boyce, CMOS Circuit Design, Layout, and Simulation, Series on
Microelectronic Systems, IEEE Press, New York, 1998.
[14] L. Pillage, R. Rohrer, and C. Visweswariah, Electronic Circuit and System Simulation Methods,
McGraw-Hill, New York, 1995.
[15] J. Elliott, Understanding Behavioral Synthesis: A Practical Guide to High-Level Design, Kluwer
Academic Publishers, Dordrecht, 2000.
[16] S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis, McGraw-Hill, New York, 1994.
[17] G. DeMicheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, 1994.
[18] I. Sutherland, R. Sproull, and D. Harris, Logical Effort: Defining Fast CMOS Circuits, Academic
Press, New York, 1999.
Timing-driven
wire spreading
• Reduces peak
wiring density
– Less crosstalk
– Better yield
Before After
5 tracks
30 tracks
10 tracks
Global routing
13 tracks
17 tracks
15 tracks
Global routing
Via doubling
• Convert a single via
into multiple vias
after routing
– Less resistance
– Better yield
FIGURE 2.10. Yield enhancement features in routing.
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 13

[19] N. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers,
Dordrecht, 1999.
[20] F. Nekoogar, Timing Verification of Application-Specific Integrated Circuits (ASICs), Prentice-Hall
PTR, Englewood Cliffs, NJ, 1999.
[21] K. Roy and S. Prasad, Low Power CMOS VLSI: Circuit Design, Wiley, New York, 2000.
[22] C-K.Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis, Wiley, New York,
2000.
[23] W. Dally and J. Poulton, Digital Systems Engineering, Cambridge University Press, Cambridge, 1998.
[24] M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, Wiley,
New York, 1995.
[25] A. Wong, Resolution Enhancement Techniques in Optical Lithography, SPIE Press, Bellingham,
WA, 2001.
[26]
CRC_7923_ch002.qxd 1/16/2006 3:51 PM Page 14
International Technology Roadmap for Semiconductors (ITRS), 2004, URL: http://public.itrs.net/.

SECTION II
SYSTEM LEVEL DESIGN
CRC_7923_ch003.qxd 1/20/2006 11:38 AM Page 1

3
Tools and
Methodologies for
System-Level Design
Field-Programmable Gate Arrays
3.5
Dataflow Models • Dataflow Modeling for Video Processing
• Control Flow • Ptolemy • Compaan • CoWare • Cocentric
System Studio • Handel-C • Simulink • Prospects for Future
Development of Tools
3.6 Simulation ...................................................................... 3-13
3.7
3.1 Introduction
System-level design has long been the province of board designers, but levels of integration have increased
to the point that chip designers must concern themselves about system-level design issues. Because chip
design is a less forgiving design medium — design cycles are longer and mistakes are harder to correct —
system-on-chip (SoC) designers need a more extensive tool suite than may be used by board designers.
System-level design is less amenable to synthesis than are logic or physical design. As a result, system-
level tools concentrate on modeling, simulation, design space exploration, and design verification. The
goal of modeling is to correctly capture the system’s operational semantics, which helps with both imple-
mentation and verification. The study of models of computation provides a framework for the descrip-
tion of digital systems. Not only do we need to understand a particular style of computation such as
dataflow, but we also need to understand how different models of communication can reliably commu-
nicate with each other. Design space exploration tools, such as hardware/software codesign, develop can-
didate designs to understand trade-offs. Simulation can be used not only to verify functional correctness
but also to supply performance and power/energy information for design analysis.
3-1
Shuvra Bhattacharyya
University of Maryland
College Park, Maryland
Wayne Wolf
Princeton University
Princeton, New Jersey
CRC_7923_ch003.qxd 1/20/2006 11:38 AM Page 1
3.1 Introduction ...................................................................... 3-1
3.2 Characteristics of Video Applications .............................. 3-2
3.3 Other Application Domains ............................................ 3-3
3.4 Platform Characteristics .................................................. 3-3
• Platform
Custom System-on-Chip Architectures
Models of Computation and Tools
for Model-Based Design .................................................. 3-6
3.8 Summary ........................................................................ 3-16
Hardware/Software Cosynthesis .................................... 3-15

We will use video applications as examples in this chapter. Video is a leading-edge application that
illustrates many important aspects of system-level design. Although some of this information is clearly
specific to video, many of the lessons translate to other domains.
The next two sections briefly introduce video applications and some SoC architecture that may be the
targets of system-level design tools. We will then study models of computation and languages for system-
level modeling. Following this, we will survey simulation technique. We will close with a discussion of
hardware/software codesign.
3.2 Characteristics of Video Applications
The primary use of SoCs for multimedia today is for video encoding — both compression and decom-
pression. In this section, we review the basic characteristics of video compression algorithms and the
implications for video SoC design.
Video compression standards enable video devices to inter-operate. The two major lines of video com-
pression standards are MPEG and H.26x. The MPEG standards concentrate on broadcast applications,
which allow for a more expensive compressor on the transmitter side in exchange for a simpler receiver.
The H.26x standards were developed with videoconferencing in mind, in which both sides must encode
and decode. The advanced video codec (AVC) standard, also known as H.264, was formed by the conflu-
ence of the H.26x and MPEG efforts.
Modern video compression systems combine lossy and lossless encoding methods to reduce the size of
a video stream. Lossy methods throw away information as a result of which the uncompressed video
stream is not a perfect reconstruction of the original; lossless methods do allow the information provided
to them to be perfectly reconstructed. Most modern standards use three major mechanisms:
● The discrete cosine transform (DCT) together with quantization
● Motion estimation and compensation
● Huffman-style encoding
The first two are lossy while the third is lossless. These three methods leverage different aspects of the
video stream’s characteristics to encode it more efficiently.
The combination of DCT and quantization was originally developed for still images and is used in
video to compress single frames. The DCT is a frequency transform that turns a set of pixels into a set
of coefficients for the spatial frequencies that form the components of the image represented by the pix-
els. The DCT is preferred over other transforms because a two-dimensional (2D) DCT can be computed
using two one-dimemsional (1D) DCTs, making it more efficient. In most standards, the DCT is per-
formed on an 8 ⫻ 8 block of pixels. The DCT does not by itself lossily compress the image; rather, the
quantization phase can more easily pick out information to acknowledge the structure of the DCT.
Quantization throws out fine details in the block of pixels, which correspond to the high-frequency
coefficients in the DCT. The number of coefficients set to zero is determined by the level of compres-
sion desired.
Motion estimation and compensation exploit the relationships between frames provided by moving
objects. A reference frame is used to encode later frames through a motion vector, which describes the
motion of a macroblock of pixels (16 ⫻ 16 in many standards). The block is copied from the reference
frame into the new position described by the motion vector. The motion vector is much smaller than the
block it represents. Two-dimensional correlation is used to determine the position of the macroblock’s
position in the new frame; several positions in a search area are tested using 2D correlation. An error sig-
nal encodes the difference between the predicted and the actual frames; the receiver uses that signal to
improve the predicted picture.
MPEG distinguishes several types of frames: I (inter) frames, which are not motion-compensated; P
(predicted) frames, which have been predicted from earlier frames; and B (bidirectional) frames, which
have been predicted from both earlier and later frames.
CRC_7923_ch003.qxd 1/20/2006 11:38 AM Page 2

The results of these lossy compression phases are assembled into a bit stream and compressed by using
lossless compression such as Huffman encoding. This process reduces the size of the representation with-
out further compromising image quality.
It should be clear that video compression systems are actually heterogeneous collections of algorithms.
We believe that this is true of other applications of SoCs as well. A video platform must run several algo-
rithms; those algorithms perform very different types of operations, imposing very different require-
ments on the architecture.
This has two implications for tools: first, we need a wide variety of tools to support the design of these
applications; second, the various models of computation and algorithmic styles used in different parts of
an application must at some point be made to communicate to create the complete system.
Several studies of multimedia performance on programmable processors have remarked on the signif-
icant number of branches in multimedia code. These observations contradict the popular notion of video
as regular operations on streaming data. Fritts and Wolf [1] measured the characteristics of the
MediaBench benchmarks.
They used path ratio to measure the percentage of instructions in a loop body that were actually exe-
cuted. They found that the average path ratio of the MediaBench suite was 78%, which indicates that a
significant number of loops exercise data-dependent behavior. Talla et al. [2] found that most of the avail-
able parallelism in multimedia benchmarks came from inter-iteration parallelism.
3.3 Other Application Domains
Video and multimedia are not the only application domains for SoCs. Communications and networking
are the other areas in which SoCs provide cost/performance benefits. In all these domains, the SoC must
be able to handle multiple simultaneous processes. However, the characteristics of those processes do
vary. Networking, for example, requires a lot of packet-independent operations. While some networking
tasks do require correlating multiple packets, the basic work is packet independent. The large extent of
parallelism in packet-level processing can be exploited in the micro-architecture. In the communications
world, SoCs are used today primarily for baseband processing, but we should expect SoCs to take over
more traditional high-frequency radio functions over time. Since radio functions can operate at very high
frequencies, the platform must be carefully designed to support these high rates while providing adequate
programmability of radio functions. We should expect highly heterogeneous architectures for high-fre-
quency radio operations.
3.4 Platform Characteristics
Many SoCs are heterogeneous multiprocessors and the architectures designed for multimedia applica-
tions are no exceptions. In this section, we review several SoCs, including some general-purpose SoC
architectures as well as several designed specifically for multimedia applications.
Two very different types of hardware platforms have emerged for large-scale applications. On the one
hand, many custom SoCs have been designed for various applications. These custom SoCs are customized
by loading software onto them for execution. On the other hand, platform field-programmable gate arrays
(FPGAs) provide FPGA fabrics along with CPUs and other components; the design can be customized by
programming the FPGA as well as the processor(s). These two styles of architecture represent different
approaches for SoC architecture and they require very different sorts of tools: custom SoCs require large-
scale software support, while platform FPGAs are well suited to hardware/software codesign.
3.4.1 Custom System-on-Chip Architectures
support. Viper is an instance of the Philips NexperiaTM
architecture, which is a platform for multimedia
applications.
Tools and Methodologies for System-Level Design 3-3
CRC_7923_ch003.qxd 1/20/2006 11:38 AM Page 3
The Viper chip [3], shown in Figure 3.1, was designed for high-definition video decoding and set-top box

Exploring the Variety of Random
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M. des Boys et tenait sous ses yeux doux M. Hervart fasciné.
En s'asseyant à la table de jeu, il eut aussitôt conscience de cette
fascination qui, jusqu'alors, s'était exercée à son insu. Il se souvenait
maintenant que, chaque fois que le sort le mettait en face de Rose,
un très grand plaisir le grisait. C'était une possession, comme en
éprouvent, au théâtre, certains spectateurs enivrés par la
comédienne de leurs rêves. Il se rendait compte aussi que son

plaisir, à peu près inconscient, devait se traduire par de fervents
regards....
«Son cœur, peu à peu, a répondu à la passion mystérieuse de mes
yeux.... Ils sont doux aussi, mes yeux, je le sais; ils sont mon
attrait.... Quant à mon extase, elle s'explique très bien, car Rose, un
peu dure de profil, est, de face, presque divine. Son nez, trop long,
rentre, un ovale parfait se dessine, le sourire semble le mouvement
naturel de cette bouche un peu large et les yeux, enfin, un peu
enfoncés, s'avancent, à la lumière des lampes, comme des fleurs....
Souvent je suis resté en pareille extase devant ma belle image de la
Vénus du Titien; il est vrai qu'elle montre aussi d'autres beautés,
mais sa figure et ses yeux, surtout, sont d'adorables pièces....»
—Ne vous faites pas de signes!
Cette observation, motivée par un échange de sourires trop
accentués, amusa beaucoup Rose, car elle pensait en ce moment
fort peu à son jeu.
Elle courba innocemment la tète sous la parole paternelle.
Ils jouèrent très mal et perdirent beaucoup de fiches.
Au retirage des places, ils furent séparés, mais pour être mieux unis,
et leurs genoux bientôt se touchèrent sous la table. La partie, dans
ces conditions, devenait exquise. Par contraste, Rose s'ingénia à
battre son ami, cependant que sa jambe innocente le cajolait tout
bas. La vie lui paraissait très agréable.
Elle s'endormit tard, un peu fiévreuse, rêvant à cette journée où elle
avait si allègrement gagné le sommet de ses désirs. Elle était aimée:
c'était le bonheur. Pas un instant, elle ne se demanda si elle aimait
elle-même. Elle n'avait sur l'état de son cœur aucun doute.
Les réflexions de M. Hervart étaient assez différentes, et d'ailleurs
d'une confusion extrême. Les femmes sont tout entières au présent;
les hommes, moins bien organisés peut être, vivent surtout dans
l'avenir. M. Hervart faisait donc des projets. Il s'endormit au milieu

de ses desseins, fatigué de ne pouvoir en dresser aucun selon une
perspective logique.
IV
Quand il descendit, le matin, d'assez bonne heure, M. des Boys,
invisible d'ordinaire jusqu'au déjeuner, se promenait avec sa fille. Il
faisait de grands gestes. M. Hervart eut peur.
Mais il ne s'agissait pas de lui. M. des Boys traçait une longue allée
serpentine, déterminait les courbes. Ayant consulté M. Hervart, qui
s'empressa d'accepter, il décida que l'on commencerait dès
aujourd'hui la visite des châteaux.
En même temps, il fît requérir des journaliers pour le lendemain,
puis il écrivit à Lanfranc, l'architecte de Martinvast, un ami qu'il avait
perdu de vue depuis bien des années. Il demeurait à Saint-Lô, étant
le constructeur officiel des bâtiments administratifs. M. Hervart le
connaissait également.
M. des Boys, cependant, oubliait sa peinture. Il resta dehors presque
toute la matinée.
Rose s'ennuyait. Elle avait compté refaire la promenade de la veille,
parmi les houx, les ronces, les fougères et les digitales. Cette
promenade, elle se la rêvait pour tous les jours de sa vie, croyant la
retrouver éternellement pareille, aussi émouvante, aussi nouvelle.
Quoiqu'il fût content de cette diversion, M. Hervart ne pouvait
s'empêcher d'éprouver quelques regrets. La main de Rose manquait
à la sienne.
Ils se trouvèrent seuls, un instant, le long de la terrasse
abandonnée, à l'endroit même où la crise avait commencé.
Vite, ils se prirent les mains et Rose tendit sa joue. M. Hervart, cette
fois, n'essaya pas de conquérir un baiser meilleur. Ce n'était pas le

moment. Peut-être n'y pensa-t-il pas. Rose fut déçue. M. Hervart
s'en aperçut. Alors il porta à ses lèvres les mains de la jeune fille. Il
aimait cette caresse, ayant pour la main un culte particulier. Il
exprima tout haut sa pensée secrète disant:
—Comment n'ai-je pas déjà baisé vos mains?
Contente, mais non émue, Rose se borna à sourire. Puis, soudain, à
une idée qui lui traversa la tête, le sourire se mua en un rire excessif,
mais qui semblait quand même nuancé de confusion. Calmée un
peu, elle demanda.
—Je voudrais savoir ... savoir ... eh bien, oui, votre nom, là?
M. Hervart, interloqué, ne comprenait pas.
—Mon nom?... Mais.... Ah! celui qui ... l'autre?...
Il hésitait. Ce nom, qu'il n'avait presque pas entendu prononcer
depuis la mort de sa mère, lui était si peu familier qu'il ressentait
une gêne à en proférer les syllabes. Il signait Hervart, tout court.
Tous ses amis l'appelaient ainsi, aucun ne l'avant connu dans
l'intimité de la famille, et ses maîtresses, elles-mêmes, n'en avaient
jamais murmuré d'autre, les femmes d'ailleurs se servant plus
volontiers d'appellations qui conviennent à toutes les têtes, telles
que mon gros loup, mon chat bleu, ou mon lapin blanc. M. Hervart,
qui était maigre, avait surtout été appelé mon gros loup.
Il dit enfin:
—Xavier.
Rose parut satisfaite.
Elle recommença à manger des mûres, comme la veille. Comme la
veille, M. Hervart ouvrit sa loupe; il comptait les points noirs qui
ornaient le dos rouge d'une bête à bon dieu, coccinella
septempunctata, et il n'en trouvait que six.
Rose mit dans la paume de sa petite main, déjà toute marbrée de
violet, une belle mûre toute noire, et la tendit à M. Hervart. Comme

il ne levait pas la tête, un œil clos, l'autre absorbé, elle dit d'une voix
douce, mais sans apprêt, d'une voix délicieusement naturelle.
—Xavier?
M. Hervart ressentit une grande émotion. Il regarda Rose avec des
yeux surpris et troublés. Elle tendait toujours sa main. Il mangea la
mûre dans un baiser, puis il répéta plusieurs fois de suite:
—Rose, Rose....
—Comme vous êtes pâle! dit-elle, également émue.
Elle recula d'un pas, s'appuya au mur. M. Hervart avança d'un pas.
Ils se retrouvèrent les yeux dans les yeux. Rose attendait, très
sérieuse. M. Hervart dit:
—Rose, je vous aime.
Elle se cacha la figure dans ses mains. M. Hervart n'osait plus ni
parler, ni remuer. Il regardait les mains qui cachaient la figure de
Rose.
Quand elle se découvrit, ses yeux étaient humides, son visage grave.
Elle ne dit rien, alla cueillir une mûre, comme s'il ne s'était rien
passé. Mais, au lieu de la manger, elle la jeta, et, au lieu de revenir
vers M. Hervart, elle s'éloigna.
M. Hervart se sentait glacé. Il la regarda, immobile et triste,
rassembler les plis de sa robe et assurer son chapeau.
Arrivée aux lilas qui allaient la cacher, Rose s'arrêta, se retourna
franchement, envoya un baiser, puis, prenant son élan, disparut vers
la maison.
La scène avait duré deux ou trois minutes: dans ce bref intervalle,
M. Hervart avait beaucoup vécu. C'était l'instant le plus émouvant de
sa vie; du moins n'avait-il pas alors le souvenir d'en avoir connu un
pareil. En entendant proférer ce nom, Xavier, presque aboli de sa
mémoire, un cortège de charmantes heures anciennes était entré
dans son cœur, celles des tendresses maternelles, celles des
premiers aveux, celles des premières caresses. Il se retrouvait au

début de la vie et aussi incapable qu'à vingt ans de réflexions
moroses.
Son allure changea tout à coup. Il grimpa sur la terrasse, à la force
des poignets, s'assit sur le rebord, parmi les herbes sèches, alluma
une cigarette et regarda les choses, en ne pensant à rien.
V
Leur rapide intimité ne laissa pas que de faire quelques progrès
pendant les jours suivants. Le matin, M. des Boys ne quittait pas les
ouvriers qui traçaient les allées nouvelles et, à chaque instant, il
appelait sa fille ou M. Hervart, sollicitant leur approbation.
L'après-midi, on allait regarder quelque château des environs.
Ils virent Martinvast, tours, chapelle, arceaux gothiques,
ingénieusement plies à recouvrir, sans dommage pour leurs lignes, le
frêle luxe moderne. Tourlaville, moins ancien, avait l'air plus vétuste,
sous sa robe de lierre. M. Hervart aima la grande tour octogone, la
hardiesse des toits incurvés.
Ils virent Pepinvast, tout ajouré, tout en clochetons, tout fleuri de
trèfles et d'épis. Ils virent Chiflevast, janus, gothique d'un côté, et
Louis XIV de l'autre.
Nacqueville a des parties vieilles; le principal corps semble
contemporain de Richelieu, l'ensemble est grand. C'est, par
excellence, le château français, celui que les générations ont
maintenu vivant, sans rien cacher de ses origines lointaines.
Le Vast, qui semble tout moderne, plaît par la fraîcheur du site, les
cascades où s'amuse la Saire. C'était plus humain que les vastes
merveilles qu'ils avaient admirées sans envie. Ici, on laissait se jouer
le désir.
—Pourtant, dit M. Hervart, cela a trop l'air d'un grand chalet.

M. des Boys résolut d'établir une cascade à Robinvast. Il regrettait
de ne disposer que d'un ruisseau.
Ils revinrent par La Pernelle, d'où l'œil voit se dérouler tout l'est de
la Hague, depuis Gatte-ville jusqu'à Saint-Marcouf, vaste manteau
d'émeraude que la mer, au loin, borde d'un ruban bleu.
On s'arrêta. Rose cueillit des bruyères dont s'emplirent les bras
heureux de M. Hervart. La vivacité de l'air animait ses joues et ses
yeux. Ils échangeaient des propos aimables.
—N'est-ce pas qu'il est beau, mon pays?
Un nuage cacha le soleil. Les teintes s'apalirent; on vit une ombre
marcher sur la mer, éteignant son éclat, peu à peu; mais au sud,
vers les îles Saint-Marcouf, elle brillait encore.
—Une pensée triste vient de passer sur le front de la mer, dit M.
Hervart, mais voyez....
Tout, à l'instant, redevenait radieux.
Rose envoya des baisers dans l'espace.
Il fallut reprendre le chemin de Saint-Vast, où l'on avait loué la
voiture. De là, par le petit chemin de fer qui longe un instant la mer,
avant de courir sous les pommiers, ils arrivèrent à Valognes.
Le dîner, à l'hôtel Saint-Michel, ne fut ennuyeux que pour M. des
Boys, qui commençait à déplorer la longueur de cette excursion. Que
de belles architectures, pourtant, à visiter encore, Fontenay,
Flamanville. Mais cela représentait de petits voyages.
—Nous verrons encore, dit-il, Barnavast, Richemont, l'Ermitage et
Pannelier. Cela peut se faire en une après-midi.
Ils ne purent rentrer à Robinvast que fort tard. L'obscurité toléra
dans la voiture quelques privautés: la jambe de M. Hervart chercha
celle de Rose et la trouva; leurs mains aussi se rencontrèrent un
instant, sous prétexte de maintenir en équilibre les bruyères que
Rose tenait sur ses genoux.

Mme
de Boys les attendait, un peu inquiète. Elle embrassa sa fille
avec frénésie. Rose se mit à rire, tout à fait énervée, voulut boire,
puis, ayant bu, voulut manger.
—C'est cela, dit M. Hervart, nous allons souper.
Il se reprit:
—C'est pour rire, je n'ai nullement faim.
Mais cette idée amusa Rose, qui apporta dans le salon toutes sortes
de choses, jusqu'à une bouteille de cidre mousseux, trouvée dans un
placard.
—Hervart a vingt-cinq ans, dit M. des Boys, qui voyait son ami aider
Rose dans ses préparatifs. Bonsoir, moi je vais me coucher.
—A vingt-cinq ans, dit Hervart, on ne sait que faire de la vie. On a
tous les atouts dans son jeu. On jette ses cartes au hasard, et on
perd.
—Il parle de jouer, maintenant? dit M. des Boys, qui fermait les
yeux. Rose se mit à rire aux éclats.
—Vous montez vraiment? dit Mme
des Boys, l'air fatigué. Il faut donc
que je reste.
Mais bientôt, elle s'ennuya. Il était minuit et demi. Elle essaya
d'emmener sa fille.
—Encore dix minutes, maman.
—Eh bien, je vous laisse. Je t'attends dans dix minutes.
M. Hervart se leva.
—Je vous donne dix minutes. Restez. Soyez indulgent pour cette
fillette. Le grand air lui a monté à la tête.
M. Hervart était gêné. Huit jours plus tôt, ce tête-à-tête lui eut paru
la chose la plus innocente et peut-être la plus ennuyeuse.
«Je ne sais vraiment pas ce qui va se passer. Il faut que je sois
sérieux, froid, que je prenne l'air fatigué, l'air vieux....»

Dès qu'elle entendit sa mère marcher au-dessus du salon, Rose vint
s'asseoir près de M. Hervart, mit les mains sur le bras de son
fauteuil. Il la regarda. Il y avait quelque chose de fou dans ses yeux.
Il se tourna tout à fait, posa ses mains sur les mains de la jeune fille.
Les mains remuèrent, prirent les siennes, les serrant très
doucement. Sans avoir eu le temps d'y penser, ils se réveillèrent, une
seconde plus tard, lèvres contre lèvres. Ce baiser épuisa leur
émotion. Ils reculèrent tous les deux du même mouvement, mais
sans cesser de se regarder.
Il la trouvait décidément très jolie. Elle le trouvait admirable,
songeant:
«Je lui appartiens. Je lui ai donné mes lèvres. Je suis à lui. Que va-t-
il faire? Que vas-tu faire?...»
M. Hervart se demandait précisément ce qu'il fallait faire.
«Quelles sont les caresses possibles et dont elle ne se fâchera pas?
J'ai envie de reprendre ses lèvres.... Ses yeux? Son cou? Quel est le
poète italien qui a dit: «Baisez les bras, baisez le cou, baisez les
seins de votre amie, ils ne vous rendront pas vos baisers. Les lèvres
seules....» Mais il faut parler. Naturellement, il faut dire: «Je vous
aime!» Mais je ne l'aime pas. Si je l'aimais, j'aurais dit: «Je t'aime!»
et je l'aurais dit sans y penser, sans le savoir.»
—Rose, je vous aime!
Elle ferma les yeux, posa sa tête sur le bras du fauteuil, car elle était
assise sur une chaise basse.
C'est l'oreille qui se présentait. M. Hervart baisa l'oreille, lentement,
à petits coups, comme un gourmand qui savoure un coquillage
délicat.
«Elle se laisse faire. C'est amusant.»
Il fit le tour de l'oreille, s'arrêta à l'œil, qui était clos.
«Que c'est doux, la paupière!»

Il redescendit le long du nez, atteignit le coin de la bouche, où il
goûta un grand plaisir. Un peu chatouillée, elle souriait.
Quand elle fut bien embrassée sur le côté droit, elle présenta le côté
gauche, puis elle offrit ses lèvres franchement, reçut un baiser
passionné, le rendit de tout son cœur et se leva.
Elle souriait sans embarras. Elle était heureuse et très peu troublée.
«C'est fait, se disait-elle, je suis mariée.»
VI
Les allées se dessinaient. L'une, d'un bel ovale, entourait, devant la
maison, une pelouse qui, pour le moment, ressemblait à un coin de
mauvais herbage, avec toutes sortes de fleurs dans l'herbe inégale,
des renoncules, des pâquerettes, des gentianes roses, des
centaurées; il y avait aussi du jonc, des orties, de la ciguë et des
angéliques, qui ressemblaient à de grandes filles maigres coiffées
d'un chapeau blanc.
Maître Encoignard, le jardinier de Valognes, considérait cette
sauvagerie d'un œil triste:
—Il faudra la charrue, monsieur des Boys, tout au moins la houe.
Puis nous tamiserons la terre remuée, nous égaliserons en bombant
légèrement, et nous sèmerons du ray-grass. En deux ans vous aurez
là un tapis de velours vert.
Lorgnant le paysage, il continuait:
—Des tilleuls! Il vous faudra ici un segoya et, là, un araucaria. Que
vois-je? Un pommier, Cela n'est pas convenable. Nous ôterons cela
pour y mettre un magnolia grandiflora. Un jardin anglais, vous
voulez un jardin anglais, n'est-ce pas? ne doit contenir que des
plantes exotiques. Des lilas, des rosiers? Pourquoi pas des boules de
neige? Ah! voici un houx panaché. Nous pouvons l'utiliser, peut-être.

—Je ne veux pas, dit Rose, qui s'était approchée, que l'on touche à
mes arbres.
—Elle a raison, dit M. des Boys.
—Arracher des lilas, reprit Rose, arracher des rosiers!...
—Mais, Mademoiselle, je vous mettrai à la place des fleurs plus
belles.
—Les plus belles fleurs sont celles que j'aime le plus.
Elle cueillit une rose rouge et la porta à ses lèvres, la baisant comme
une chose sacrée et adorée.
M. des Boys regardait sa fille avec étonnement.
—Eh bien, monsieur Encoignard, il faudra faire ce qu'elle veut.
Hervart, qu'en pensez-vous?
—Je pense qu'il faut peigner la nature le moins possible. Je pense
aussi qu'il faut aimer les plantes du pays où l'on vit. Elles seules
s'harmonisent avec le ciel, avec les cultures, avec la couleur des
rivières, des chemins et des toits.
—C'est juste, dit M. des Boys.
—Xavier, je vous aime, murmura Rose, en prenant le bras de M.
Hervart.
On continua l'inspection du jardin et il fut décidé que la collaboration
de maître Encoignard erait réduite aux soins ordinaires d'un jardinier
sage et docile. On admit quelques plantes nouvelles, à condition que
les anciennes seraient respectées.
M. Hervart, qui s'était levé de bonne heure, se promenait depuis
longtemps déjà. Il avait passé une partie de la nuit à réfléchir. Les
femmes qu'il avait aimées, ou connues, s'étaient présentées à lui
dans leurs attitudes préférées et leurs gestes habituels. Celle-ci, un
corps charmant, se dévêtait sitôt entrée, comme une folle, en
excitant son amant à une pareille et prompte nudité. Une autre
semblait au contraire n'être venue que pour une visite amicale, et il

fallait de réelles diplomaties pour obtenir d'elle ce qu'elle désirait très
fort pourtant, au fond de son cœur. Entre ces deux-là, beaucoup de
nuances se disposaient. La plupart aimaient à se livrer peu à peu, à
jouer longuement avec leur pudeur et avec leur désir, à contempler
la lutte des deux bêtes divines. M. Hervart croyait connaître assez
bien les femmes; il savait que celle qui se laisse toucher se laissera
prendre toute.
«Une femme, songeait-il, qui aurait été aussi familière que Rose, et
même beaucoup moins, serait femme donnée. Peut-être me ferait-
elle attendre encore quelques jours, en maîtrisant son feu, jusqu'à
l'heure propice des abandons complets, mais elle m'appartiendrait,
laisserait ses yeux l'avouer, ses lèvres le dire. Il me semble même
qu'une telle femme serait disposée à provoquer la venue de l'heure
agréable, si je n'avais pas l'adresse de la préparer moi-même. Rose,
étant une jeune fille et n'ayant que des pressentiments confus, ne
sait comment hâter notre bonheur, sans quoi elle le hâterait, c'est
évident. Elle est donc à moi. Je suis le maître de son heure et de la
mienne. La question que j'ai à résoudre est donc celle-ci: vais-je
continuer de respirer la fleur sur le rosier, ou vais-je la cueillir?»
Cette métaphore lui parut d'une poésie un peu molle.
Alors il employa en lui-même, sans toutefois les formuler, même à
mi-voix, des termes plus nets.
«Eh bien, si je la prends, je la garderai. Je n'avais jamais songea me
marier, mais il ne faut pas résister à sa vie. C'est peut-être le
bonheur. Voudrais-je mettre dans ma vieillesse ce regret: le bonheur
a passé à côté de moi en souriant à mon désir, et mes yeux sont
restés mornes et ma bouche est restée muette? Le bonheur, le
bonheur? Est-ce bien certain? Le bonheur est toujours incertain. Le
malheur aussi, d'ailleurs. Et il se forme, par l'amalgame de ces deux
éléments, un mélange fade.»
Cette idée banale l'occupa un instant. Toutes les joies sont
passagères et ensuite on se retrouve dans l'état neutre.

«Neutre, ou au-dessous du neutre. Une femme de ce tempérament?
Eh! je puis encore la dompter! Soit, mais dans dix ans, quand elle en
aura trente? Ah! d'ici là!»
M. des Boys emmena Encoignard dans son bureau. Restés seuls,
Rose et M. Hervart eurent bientôt disparu derrière les massifs,
bientôt franchi le ruisseau. Ils couraient presque.
—Nous voilà chez nous, dit Rose, et, de l'air le plus calme, elle offrit
ses lèvres à M. Hervart.
«Elle est déjà conjugale,» se disait-il.
Cependant, ce baiser le troubla, d'autant plus que Rose, pour
remercier sans doute M. Hervart d'avoir défendu son vieux jardin,
laissa longtemps sa bouche unie à celle de son ami. Comme elle
perdait haleine, ses seins remuèrent sous le léger corsage blanc. Il
était bien tentant d'y porter la main. M. Hervart osa, et son geste fut
accueilli sans indignation. Ils se regardèrent, désirant parler, mais ne
trouvèrent pas de paroles. Alors leurs bouches se joignirent encore.
M. Hervart pressait doucement le sein de Rose et une petite main
serrait son autre main. Le moment était périlleux. M. Hervart le
sentit et voulut mettre fin à ce contact. Mais la petite main serra plus
étroitement sa main, cependant qu'un genou, s'ouvrant d'un
mouvement légèrement convulsif, venait battre sa jambe. L'arc, à ce
contact, se détendit. Les mains retombèrent, les lèvres se
déjoignirent et, pour la première fois après un baiser, Rose ferma les
yeux.
M. Hervart sentit une douleur à la nuque.
Il se souvint alors d'une saison d'amour platonique qu'il avait passée
à Versailles avec une femme vertueuse, et il eut peur, car cette
passion à baisers légers et à serrements de mains l'avait plus ravagé
que les plus violents excès.
«Que vais-je devenir? Car maintenant, c'est du platonisme aigu,
avec ses manifestations les plus décisives. Tout ou rien! Autrement,
je suis perdu.»

Il regarda Rose, en croyant prendre un air glacé, mais les yeux
complices le regardaient si doucement!
Ses pensées se firent confuses. Il avait envie de se coucher dans
l'herbe et de dormir. Il le dit.
—Eh bien, couchez-vous et dormez. Je veillerai votre sommeil.
J'écarterai les mouches de vos yeux et de vos lèvres. Je vous
éventerai avec cette fougère et j'essuierai de mon mouchoir la sueur
de votre front.
Elle parlait d'un ton de câlinerie passionnée. C'était une musique. M.
Hervart se réveilla et dit des paroles d'amour.
«Je vous aime, Rose. Le contact de vos lèvres a rafraîchi mon sang
et réjoui mon cœur. Quand j'ai posé ma main sur votre poitrine, il
m'a semblé que j'étreignais un trésor. J'étais riche. Mais, dis, mon
enfant aimée, ce trésor, tu me l'as donné et tu ne me le reprendras
pas?...»
M. Hervart haletait. Rose, en remuant la tête, disait: «Non, je ne le
reprendrai pas», et même, pour prouver sa véracité, elle tendit sa
gorge vers M. Hervart, qui effleura d'un baiser léger l'étoffe tendue.
Voyant le peu d'empressement de son amant, Rose, sans en
soupçonner le mystère, devina un mystère.
«L'amour, sans doute, veut des repos. Nous allons nous promener et
je lui parlerai des fleurs et des insectes. Nous ferons peut-être bien
aussi de retourner au jardin, car si on avait l'idée de venir nous
chercher, ce serait très ennuyeux.»
Ils se levèrent et firent le tour du bois, pour regagner ensuite la
maison.
M. Hervart était distrait.
Il tenait dans sa main la main de son amie, mais il oubliait de la
serrer. Pourtant ses pensées étaient des pensées d'amour. Il
regardait autour de lui, semblait chercher quelque chose.
—«Que cherchez-vous? Dites-le-moi, je chercherai aussi.»

M. Hervart cherchait un lit. Il inspectait les mousses et les feuilles
sèches, examinait les berceaux, les abris, les retraites.
Il avait honte de sa quête.
«Mais, songeait-il, il le faut. Je l'aime, et ces jeux innocents sont trop
pernicieux. M'en aller? C'est me condamner à une solitude désolée
ou à des consolations amères. L'épouser? Soit, mais ce n'est pas
demain, et nous sommes trop frémissants pour être patients. Et
puis, retrouverions-nous les moments qu'un désir secret nous
ménage? Et si, fiancés, le sentimentalisme traditionnel allait nous
soumettre à son protocole? Non, enfants de cette terre qui nous
prépare son sein, soyons des paysans. Comme eux, aimons d'abord,
au hasard des sentiers et, sûrs du consentement de notre chair, nous
prendrons à témoin les hommes.»
Il cherchait toujours, et il trouvait, mais quand il avait trouvé, il
cherchait encore, car il avait honte de sa lâcheté.
«Et, se répondait-il, s'il faut être lâche pour être heureux? Quoi, je
me soumettrais aux préjugés, au moment que la vie envoie sous
mes lèvres une vierge qui les ignore? J'aurai le courage de ma
lâcheté.»
Peu à peu, il regarda d'un œil plus distrait les tapis de feuilles. Son
imagination revenait avec complaisance aux délices de la minute
précédente, et il souhaita appuyer encore une fois sa main
tremblante sur le sein gonflé de Rose, cependant qu'il boirait son
haleine et sa salive.
«Car tel est l'amour que de nos muqueuses il coule une manne plus
douce et plus nourrissante que le lait des mamelles maternelles!»
M. Hervart retrouvait tout son aplomb. Il conclut:
«Bien curieuse aventure et qui augmente le trésor de ma science et
celui de mes plaisirs.»
Rose, sentant la pression de ses doigts, osa enfin le regarder. Il
souriait. Elle fut contente.

—Vous ne me quitterez pas? dit-elle. Promettez-le-moi. Quand nous
serons mariés, nous demeurerons où vous voudrez, mais, d'ici là, je
vous veux près de moi, dans ma maison, dans mon jardin, dans mes
bois, dans mes champs, sur nos roules. Comprenez-vous?
—Enfant, je vous aime et je comprends que vous m'aimez aussi....
—Pourquoi aussi? C'est moi qui ai aimé la première; je ne veux pas
de ce mot; il exprime une sorte d'imitation.
—C'est vrai, dit M. Hervart, notre tendresse réciproque fut
simultanée. Mais il est toujours convenu que c'est l'homme qui aime
le premier et que la femme ne fait que consentir à ses désirs.
—Que pouvez-vous désirer que je ne désire moi-même?
«Son innocence est délicieuse», pensa M. Hervart.
Il reprit:
—Mais je désire peut-être plus d'intimité encore, un abandon entier,
Rose....
—Eh bien, ne suis-je pas tout entière à vous? Mais je vous veux en
échange, Xavier, je vous veux aussi tout entier.
M. Hervart ne sut que dire. Il devenait timide. Une si charmante
naïveté le troublait plus que les images mêmes de la volupté.
«Elle ne savait pas, pensait-il. Elle n'a même pas rêvé. Quelle
chasteté! Quelle grâce!»
Il répondit:
—Je vous appartiens, Rose, de tout mon cœur....
—Vous étiez distrait, il y a un instant?
—Les premiers mouvements de mon bonheur....
—Oh! Vous avez eu bien des bonheurs, depuis que vous existez,
Xavier, vous en avez donné, vous en avez reçu....
—J'ai vécu, dit M. Hervart.

—Oui, et moi je suis une jeune fille de vingt ans.
—Avoir vingt ans!
—Si vous aviez vingt ans, je ne vous aimerais pas.
M. Hervart ne répondit que par un sourire qu'il fit le plus jeune
possible, le plus délicat. Il savait bien ce qu'il aurait voulu dire, mais
il sentait qu'il ne le dirait pas. D'ailleurs, il se demandait si Rose et
lui-même parlaient la même langue.
«Cette conversation doit être absurde. Je lui dis que je désire qu'elle
m'abandonne son corps, et elle me répond sans doute qu'elle m'a
donné son cœur. Evidemment, elle n'a aucune idée de ce qui
pourrait se passer entre nous.... Ces menues privautés, qu'est-ce
que cela pour elle? Des marques d'affection.... Pourtant, n'y avait-il
pas de la volupté dans ses gestes, dans ses baisers, dans ses yeux?
Son corps n'a-t-il pas tremblé sous mes lèvres impérieuses? Oui, elle
connaît l'amour! Quel enfantillage! Pourtant, avec beaucoup
d'adresse....»
—Ne croyez pas, Rose, que j'aie encore jamais eu l'occasion de
donner mon cœur. Cela n'arrive pas toujours, au cours d'une vie,
cela; et quand cela arrive, cela n'arrive qu'une fois.... Un homme a
bien des aventures qui n'engagent pas sa volonté.... L'homme est un
animal, en même temps qu'il est un homme....
—Et la femme?
—Il est convenu, dit M. Hervart, que la femme est un ange.
Rose, à ce propos, se mit à rire, avec beaucoup d'innocence,
semblait-il, puis elle dit:
—Je n'ai pas la prétention d'être un ange.
Cela ne m'amuserait pas d'ailleurs. Les anges, mon père les met
dans ses tableaux. Moi j'aime mieux être une femme. Est-ce que
vous aimeriez un ange?
M. Hervart riait aussi. Il expliqua cependant que les jeunes filles
avaient droit à ce titre délicieux d'anges, à cause de leur

innocence....
—Quand on aime, est-on encore innocent?
—On ne l'est pas longtemps, si on l'est encore.
Ils ne purent en dire davantage. Ils étaient revenus près du
ruisseau, et ils apercevaient M. des Boys qui montrait son domaine à
deux messieurs inconnus, dont l'un semblait de son âge, dont l'autre
était un homme d'une trentaine d'années.
VII
M. Hervart reconnut bientôt dans l'un des visiteurs son ami
d'autrefois, l'architecte Lanfranc. Il apprit ensuite que le jeune
homme était le neveu, l'élève et le successeur probable de Lanfranc.
Enfin, il fut informé que les deux architectes étaient installés au
vieux château de Barnavast, dont ils avaient entrepris la restauration
pour le compte de Mme
Suif, veuve du célèbre Suif, l'homme qui avait
donné un si bel essor à la statuaire sulpicienne. Lanfranc, qui avait
rejointoyé et enluminé toutes les églises de la basse Normandie, se
fournissait depuis vingt ans chez Suif, et sa veuve l'avait toujours
apprécié. De là cette entreprise de Barnavast, qui allait achever sa
fortune et lui permettre de regagner Paris et d'arriver à l'Institut.
Dès qu'on se fut assis à l'ombre des marronniers sur le banc et les
chaises rustiques, Lanfranc commença l'histoire de Mme
Suif, que
tout le monde connaissait. Rose y fut attentive. Dès que Lanfranc
pouvait réunir un auditoire bienveillant, il racontait l'histoire de Mme
Suif, qui était un peu la sienne. Mme
Suif avait été sa maîtresse, puis
il s'était marié, puis il avait renoué avec elle, enfin, la tiédeur venue,
était resté son ami.
—Ah! si je n'avais pas eu l'enfantillage de faire un mariage d'amour,
j'épouserais aujourd'hui les millions de Mme
Suif, car Mme
Suif serait

reconnaissante au monsieur qui la débarrasserait de son nom.
Comment voulez-vous que je divorce, moi, architecte des églises et
des châteaux? Enfin, elle consentira peut-être à s'appeler Mme
Léonor Varin. Elle ne regarde pas mon neveu sans complaisance.
—Moi, je n'en veux pas! dit Léonor, en rougissant.
Rose l'avait regardé, et il s'était soudain senti tout honteux de sa
cupidité secrète.
Léonor, qui avait près de trente ans, paraissait de loin plus âgé et de
près plus jeune. C'est qu'il était grand et un peu massif, lent en ses
mouvements. De près, on était surpris de la douceur sentimentale
de ses yeux, de la grâce juvénile d'une barbe qui semblait encore
naissante, de la gaucherie de ses gestes, et, s'il parlait, de la timidité
brusque de son langage, car il ne pouvait guère ouvrir la bouche
sans rougir. Il est vrai que, l'instant d'après, il fronçait les sourcils et
prenait, par tout son visage contracté, un air dur. Là dedans, les
yeux restaient toujours bleus et doux. Léonor était énigmatique pour
tout le monde et aussi pour lui-même. Il aimait à réfléchir et quand il
songeait à l'amour, c'était pour constater que son idéal flottait entre
le rêve et la débauche, entre le bonheur de baiser à genoux une
main gantée et le plaisir de s'alanguir entre les chairs complaisantes
de plusieurs odalisques. Il ne se doutait pas un instant qu'il était
pareil à presque tous les hommes. Il avait peur de lui-même, et
c'était du mépris, quand il se surprenait à songer avec trop de
complaisance aux millions de Mme
Suif, à ces millions qui pourraient
satisfaire immédiatement ses vices, et, plus tard, ses aspirations
sentimentales.
A son tour il regarda Rose, mais Rose ne baissa pas les yeux.
Pendant cela, M. Hervart s'ennuyait.
—Mme
Suif, dit Lanfranc, est encore très bien. Ainsi, tenez....
—Rose, mon enfant, interrompit M. des Boys, ta mère a peut-être
besoin de toi.

—Oh! je suis bien certaine que non. Ma mère trouverait que je la
dérange.
—Votre père a raison, Rose, dit M. Hervart heureux d'essayer de son
autorité.
La jeune fille n'osa pas résister au désir de son ami, mais en se
levant elle était de mauvaise humeur:
«Déjà mon maître! Déjà! Moi, cela m'amusait d'écouter ce M.
Lanfranc....»
Elle n'osait ajouter: «... et de regarder ce M. Léonor, et d'être
regardée par lui, et encore plus, peut-être, d'entendre parler de Mme
Suif.»
«Qu'allait-il dire? Oh! je veux savoir!»
Elle entra dans la maison, ressortit par une autre porte et revint se
cacher dans un massif, d'où les voix lui parvenaient assez bien.
—Ce ne sont pas seulement ses épaules, continuait M. Lanfranc, qui
sont encore très tentantes. Sa poitrine, à quarante-cinq ans, est
encore ferme et d'une bonne ligne, ses hanches ne sont pas
excessives.... L'ensemble a un peu d'ampleur, mais, à l'Ecole, on en
ferait encore une Junon fort honorable. J'en ai vu de pires sur la
table à modèles....
—Souvent, dit M. Hervart, le temps a une clémence évangélique. Il
pardonne aux femmes qui ont beaucoup aimé....
—Et qui aiment encore, dit Lanfranc
—Quel meilleur exercice que l'amour? dit Léonor. Quel sport plus
apte à conserver, aux membres leur souplesse?
M. Hervart considéra surpris ce jeune homme terne qui venait de
montrer de l'esprit. Jaloux de briller aussi, il répliqua:
—Ils n'ont pas osé mettre cela dans leurs manuels d'hygiène.
Pourtant, quel joli chapitre à rédiger, dans le goût du premier
empire: «L'Amour conservateur de la beauté.»

—Un joli sujet aussi pour les prix de Rome, dit Lanfranc.
—Sérieusement, intervint M. des Boys, je crois que c'est la chasteté
qui racornit si promptement les femmes honnêtes....
—Oh! celles-là, dit Lanfranc, ce sont des reproductrices. Quand elles
ont fait leurs enfants, et il faut que cela soit de vingt à trente, leur
rôle est fini.
—Il leur reste, dit M. des Boys, à façonner les philtres qui
entretiennent notre jeunesse.
On lui jeta des regards interrogatifs, cependant qu'il riait d'un rire
luxurieux.
—Vous verrez, ou plutôt vous goûterez, et vous comprendrez. Je
vous souhaite à tous une magicienne comme Mme
des Boys.
—C'est vrai, dit M. Hervart, qui comprit enfin, elle a le génie de la
cuisine. Les dîners qu'elle a surveillés sont des magistères.
—Tu t'en apercevras, quand tu seras de retour à Paris.
—Oui, car ici je prends mes vacances, dit M. Hervart, heureux de
cette marque de confiance.
Il ajouta même, pour prévenir mieux encore les soupçons possibles:
—Les vacances de l'amour ne vont pas sans quelque mélancolie.
Rose s'était amusée beaucoup, mais depuis que son père avait pris
la parole, elle n'écoutait plus. Léonor, satisfait d'avoir eu de l'esprit,
et daignant de n'en plus retrouver, s'était levé et se promenait dans
le jardin. Rose le regardait. La vue de ce jeune animal l'intéressait. Il
était sorti de cette tête de si curieuses paroles sur l'amour! Ainsi
l'amour était un exercice comme le tennis, la bicyclette ou
l'équitation! L'amour était un sport! Quelle révélation! Et les images
les plus singulières se formaient dans son esprit, cependant qu'elle
suivait des yeux la silhouette maintenant lointaine du jeune homme
ingénieux et décisif.

«Comment joue-t-on à l'amour, au vrai amour? Xavier ne m'apprend
rien. Il sait tout pourtant, il en sait sans doute bien plus encore que
ce Léonor, mais il se garde bien de m'instruire, me traite comme une
petite fille, tout en se moquant de mon innocence. Oh! sa moquerie
est bien douce, car il m'aime beaucoup, mais il abuse tout de même
un peu de sa supériorité. Un sport, un sport....»
Elle sortit du massif d'arbres verts et alla s'asseoir sur un vieux banc
de pierre, dans un coin à l'écart, mais d'où elle pouvait surveiller, par
des coulées entre les arbres, tout ce qui se passait aux alentours.
Elle aimait ce coin où elle avait rêvé d'entières matinées, avant
l'arrivée de M. Hervart. Elle riait maintenant de la puérilité de ces
rêves.
«Il me semblait, songeait-elle, que les branches allaient s'écarter,
laissant paraître un jeune cavalier beau comme le jour.... Sans rien
dire il poussait son cheval jusque près de moi, se penchait,
m'enlevait, me couchait sur sa selle, et nous partions. C'était un
galop fou, interminable, où je finissais par m'endormir, et, en effet,
je me réveillais comme d'un sommeil, et pourtant je n'avais pas
dormi. Il ne se passait rien qu'une chevauchée muette dans l'air
bleu, et pourtant, en revenant à moi, j'étais lasse.... Que de fois j'ai
fait ce rêve, que de fois j'ai vu les touffes des lilas se tasser pour
faire place à mon beau cavalier et à son cheval noir.... Le cheval était
toujours noir. Je me souviens peu de la figure du Persée qui me
délivrait, pour quelques heures, de l'esclavage de mon ennui.... Un
sport? Mais c'était un sport, cela! Que faisait-il de son Andromède,
mon Persée? Je n'ai jamais pu le savoir. Que font les Persées de
leurs Andromèdes?»
A cette question, l'infatigable imagination de Rose faisait, pour la
centième fois, des réponses nouvelles. Tout le possible se déroulait
devant ses yeux ou s'enroulait autour de son corps. Non seulement
elle se donnait toute comme la pâte se donne aux mains agiles et
violentes du pétrisseur, mais elle devenait aussi la boulangère affolée
du pain mâle. L'imagination d'une jeune fille qui sait et ne sait pas ce
qu'elle désire est d'une fécondité arétine. Aucun mouvement ne lui

semble extraordinaire, ni aucune attitude ne lui semble impudique,
ni aucun geste ne lui semble discourtois. Elle est prête à tout et tout
lui semblera normal. Son appel au mâle est un appel à la science.
Elle veut savoir. Si elle savait, elle n'imaginerait plus. Les femmes ne
rêvent qu'à l'acte qui les a satisfaites. Les jeunes filles rêvent à tous
les actes possibles et tous la satisferaient également. La perversion
d'une jeune fille est la preuve même de son innocence; mais celles
qui accepteraient tous les gestes savent pourtant, d'instinct, se
révolter contre celui qui féconde: les plus folles sont les plus sages.
En tout ce que Rose s'imaginait depuis quelque temps, elle mettait la
complicité de M. Hervart. Et même au moment où elle guettait le
retour de Léonor, c'était à M. Hervart qu'elle pensait vraiment.
Léonor n'allait sans doute être qu'un excitant pour son cœur et pour
ses nerfs, une musique, un accompagnement. Le surcroît de désirs
que la venue du jeune homme avait éveillé en elle, M. Hervart en
profitait. Elle murmura plusieurs fois:
«Xavier, Xavier....»
Xavier, cependant, se félicitait de l'intervention paternelle qui avait
épargné à Rose les propos hardis de M. Lanfranc. L'architecte sans
doute eût adouci son langage, mais est-il bien utile qu'une jeune fille
apprenne l'usage que les femmes font du mariage? Il se sentait
devenir de l'école d'Arnolphe. Il dit:
—Mon cher Lanfranc, surveillez un peu votre langage, à table. Nous
avons ici une jeune fille, ne l'oubliez pas.
—Oui, ajouta M. des Boys, je l'ai renvoyée d'ici, mais cela serait
difficile pendant le déjeuner.
—Les jeunes filles, dit Lanfranc, cela ne comprend rien.
—Cela devine, dit M. Hervart.
M. des Boys, sans opinion sur la perspicacité virginale, désirait se
conformer à l'usage et ne faire entendre à sa fille que des propos
choisis.

—Alors, profitons, pendant que nous sommes seuls, reprit Lanfranc,
dont les yeux d'un bleu vif égayaient la face tannée. Les jeunes filles
comprennent peu et les femmes, guère davantage. Avez-vous
rencontré dans votre vie beaucoup de femmes vraiment curieuses
des choses de la chair, vous, Hervart? Dites? N'ont-elles pas toujours
l'air de remplir une tâche? Maîtresses, elles travaillent à l'heure.
Epouses, ce sont des fonctionnaires....
M. des Boys s'égaya. Sa femme était bien un fonctionnaire et même
à la retraite, et sa maîtresse, qui d'ailleurs l'excitait peu, répondait
assez à la définition de Lanfranc. Il allait la voir huit ou dix fois par
an, avec l'astuce d'avoir toujours l'air de se laisser emmener à
Cherbourg par complaisance.
Quelques jours plus tôt, M. Hervart eût protesté. Oui, il avait connu
plus d'une femme voluptueuse. Celles que l'on connaît sont même
généralement des voluptueuses, sans quoi elles seraient restées
dans le cercle de la famille; mais encore faut-il savoir faire chanter
ces violons de bonne volonté.
«Moi, eût-il répondu, je suis un archet magique. Je n'ai jamais
rencontré ni un violon tout à fait insonore ni une femme absolument
froide. J'en ai toujours tiré un air, des plaintes, une chanson, et
toutes m'ont donné le baiser de paix, le baiser de joie. Une ou deux
fois, je crus être amoureux. Cela me rendit timide et mon archet fit
quelques fausses notes. Une autre fois, ce fut un amour réciproque,
et l'archet et le violon étaient si bien d'accord que l'harmonie
jaillissait au seul toucher des cordes. Les phrases voluptueuses
n'avaient presque ni commencement ni fin. C'était un jeu continu
avec des douceurs et des forces. J'avais autant de bonheur à
regarder son épaule nue qu'à m'exalter dans ses bras et souvent la
vue de son chapeau, de sa robe et de ses plumes, au tournant de la
rue, m'éleva au rang d'un dieu. Un hommage adorable montait de
cette créature vers mon cœur L'amour, c'est une religion
mutuelle....»
Il dit tout haut, rentrant dans la conversation qui avait dévié encore
une fois vers les mérites administratifs de Mme
des Boys:

—On rencontre des femmes diverses. La meilleure ne vaut pas le
rêve que l'on s'en faisait.
«Jolie banalité. Que va-t-il répondre à cela?»
—Je ne rêve pas, moi, dit Lanfranc, je cherche. Mais je ne trouve
guère. Les aventures m'ont toujours déçu. Aussi, je ne veux plus
aimer qu'à Paris. Là, on trouve d'agréables romans qui n'ont qu'un
seul chapitre, le dernier.
—Votre opinion sur les femmes ne m'étonne plus.
—Mais, dit M. des Boys, son opinion est assez raisonnable. Vous
parlez comme si vous aviez toujours vingt-cinq ans, Hervart.
Il rougit un peu:
—Moi! Ah! Dieu merci, j'en ai quarante. Et, poussé par l'à-propos, il
ajouta en disant:
—Vous êtes jaloux de ma liberté, mais je crains bien de la perdre.
Par ces paroles, il posait sa résolution.
—Vous pensez à vous marier? demanda Lanfranc.
—Peut-être.
—Mme
Suif vous irait très bien, Léonor fait le difficile....
Agacé par tant de vulgarité, M. Hervart se leva à son tour, entra
dans le jardin: Rose et Léonor se promenaient ensemble.
VIII
Rose avait manœuvré de façon à se trouver sur le chemin du jeune
homme. Ne pas la voir, c'était la fuir. La voir, c'était la saluer. Ainsi
était-il arrivé. Au salut, Rose avait répondu par une parole de
bienvenue, puis on avait passé au château de Barnavast, enfin à Mme
Suif. Mais Léonor était discret et vague, si bien qu'à une question de

Rose la conversation tourna vers les banalités sentimentales.
Cependant, pour Rose, il n'y avait encore rien de banal au monde.
—Elle semble bien âgée, pour se remarier? demanda-t-elle.
—Oh! Mme
Suif est de celles dont le cœur est toujours jeune.
—Ah! Il y a donc des cœurs qui vieillissent moins vite que les autres?
—Il y en a qui ne vieillissent jamais, Mademoiselle, comme il y en a
qui n'ont jamais été jeunes.
—Pourtant, je vois de grandes différences, autour de moi, dans les
sentiments des jeunes et des vieilles personnes.
—Connaissez-vous beaucoup de monde?
—Non, très peu, au contraire, mais j'ai toujours vu un certain accord
entre les cœurs et les visages.
—Sans doute, mais la vérité générale, quoique représentant la
moyenne des vérités particulières, n'est presque jamais conforme à
une vérité particulière, prise au hasard....
Rose regarda Léonor avec un mélange d'admiration et de honte. Elle
ne comprenait pas. Léonor s'en aperçut et reprit:
—Je veux dire qu'en toutes choses il y a des exceptions. Je veux dire
aussi qu'il y a des règles qui comportent un grand nombre
d'exceptions. Il arrive même dans la vie, comme dans la grammaire,
que les cas exceptionnels soient plus nombreux que les cas
réguliers.... Comprenez-vous?
—Oh! très bien.
—Ce qui n'empêche, acheva-t-il, en scandant ses mots, que la règle,
n'aurait-elle que deux cas normaux à opposer à dix exceptions, la
règle est la règle.
Ce ton doctoral plaisait à Rose. M. Hervart, depuis quelque temps,
était toujours de son avis.
—Mais à quoi, reprit-elle, reconnaît-on la règle?

—La règle, dit Léonor, satisfait la raison. Rose le regarda, inquiète,
puis, feignant d'avoir compris, fît un signe d'assentiment.
—Les femmes, reprit Léonor, n'entendent pas cela très bien. Cela ne
les contente pas. Elles ne cèdent qu'au sentiment. Les hommes
aussi, du reste, mais ils ne l'avouent pas. Aussi les femmes, que l'on
accuse d'hypocrisie et de vanité, en ont-elles moins que les hommes,
peut-être.... Enfin la règle est la règle. La règle voudrait que
Marguerite renonçât....
—Oui ça, Marguerite?
—Mme
Suif.
—Vous la connaissez beaucoup?
—Ne suis-je pas, répondit Léonor en souriant, le neveu et le
lieutenant de son architecte? La règle, donc, voudrait que Marguerite
renonçât à l'amour; et la règle veut que vous, Mademoiselle, vous y
pensiez.
—La règle est la règle, dit sentencieusement Rose, en réprimant les
éclats d'un rire qui s'épanouit en silence dans son cœur.
«Elle n'est pas bête, la règle, songeait-elle. Je ne demande qu'à lui
obéir, et je crois que nous serons toujours d'accord....»
A ce moment, M. Hervart se trouva devant eux, au détour d'une
allée. Rose l'accueillit par un sourire heureux, un sourire d'une
délicieuse franchise.
«Allons, se dit M. Hervart, il n'est pas encore mon rival. Mon rôle, en
ce moment, est de faire l'homme sûr de lui-même, l'homme qui
possède, qui domine, le seigneur au-dessus de toutes les
contingences....»
Et il parla de sou séjour à Robinvast, du plaisir qu'il prenait au milieu
de cette nature riche et désordonnée.
—Mais, dit-il, vous venez y mettre de l'ordre. Vous allez blanchir ces
murs, gratter ces mousses et ces lierres, éclaircir ces masses

sombres, enfin donner à M. des Boys un joli château tout neuf, avec
un délicieux parc également tout neuf....
—Touchera mes lierres! s'écria Rose indignée.
—Et pourquoi cela? dit Léonor. Les lierres ne sont-ils pas la gloire
des murailles de Tourlaville? Les lierres, mais c'est la seule beauté
architecturale qu'on ne puisse acheter. A Barnavast, qui est à l'état
de ruine, nous les respectons, chaque fois que le mur peut se
consolider par l'intérieur. Restaurer, pour moi, c'est rendre au
monument l'aspect que les siècles lui auraient donné si on avait
veillé à son entretien. Restaurer, ce n'est pas remettre à neuf; ce
n'est pas donner à un vieillard les cheveux, la barbe, le teint et les
dents d'un jeune homme; c'est relever un mourant et lui donner la
santé et la beauté de son âge.
—Oh! que je suis contente de vous entendre parler ainsi, dit Rose.
J'espère que M. Lanfranc a vos idées?
—M. Lanfranc est tout à fait converti à mes idées.
—Mon père ne fera rien sans me consulter, mais je serai plus sûre de
vaincre, si vous êtes mon allié.
—Je serai votre allié.
—Votre méthode est sage, dit M. Hervart. Vous savez que je
conserve la sculpture grecque au Louvre? Je suis entré dans cette
nécropole au moment où le vieux système des restaurations
commençait d'être abandonné. Un oscillait entre deux méthodes:
refaire ou ne rien faire. La seconde a prévalu. Vous avez donc pu
constater que nos marbres peuvent se répartir en deux groupes:
ceux qui n'ont d'antique que le nom, et ceux qui n'ont d'antique que
la matière. Autrefois, quand on avait trouvé un buste, on lui refaisait
une tête, des bras, des jambes et l'on écrivait au-dessous de la
chose: Restauré en Artemis, restauré en Minerve, restauré en
Nymphe chasseresse, selon le caprice du plâtrier ou les indications
d'un archéologue endormi. Je crois surtout que l'on comblait ainsi
des lacunes. Si le système avait continué d'être suivi, nous aurions
sans doute, à cette heure, un Olympe complet, tandis qu'il y a

encore bien des places vides dans l'assemblée de nos dieux. Depuis
que l'on a pris le parti de ne rien faire, les galeries se sont enrichies
de curieux débris anatomiques, jambes et mains qui ressemblent à
ces ex-voto que l'on voyait en effet pendus dans les sanctuaires
grecs, têtes qui, toutes pareilles à celle d'Orphée, semblent avoir
roulé à l'heure des orages, parmi les galets de la mer indignée,
bustes troués comme ayant servi de cible à des soldats ivres. Bref, il
n'entre plus chez nous que des morceaux d'un grand intérêt
archéologique, mais d'une valeur d'art à peu près nulle. Une
méthode intermédiaire n'aurait-elle pas été préférable?
Intermédiaire, c'est-à-dire intelligente. L'intelligence, n'est-ce point
l'art de concilier les idées et d'obtenir une harmonie? Une tète
d'Aphrodite au nez cassé n'est plus une tête d'Aphrodite. Il me faut
de la beauté et on me donne une pièce d'archives. Que l'on refasse
le nez, si l'on veut que j'admire, et si l'on ne veut pas refaire le nez,
que l'on sépare le Louvre en deux musées, le musée esthétique et le
musée archéologique.
Ayant fini do parler, il regarda Rose, d'abord, témoignant ainsi qu'il
avait besoin, avant tout, de son approbation. La figure de Rose
s'éclaira de bonheur. Ses yeux répondirent.
«Mon ami, je vous admire. Vous êtes un dieu.»
Ces mouvements furent compris par Léonor, qui cherchait depuis
quelques instants à deviner quels étaient les rapports de Rose et de
Hervart.
«Ils s'aiment, se dit-il, et lui il a le génie de l'amour. Moi, j'ai vingt-
huit ans. C'est ma seule supériorité sur lui. Encore est-elle fort
illusoire, car seules les femmes, mises au courant de la vie par
l'expérience ou les confidences, font quelque attention à l'âge des
hommes. Une femme a l'âge de sa figure. Un homme a l'âge de ses
organes. Or l'état des organes se lit dans les yeux. Un homme a
l'âge de ses yeux. Hervart a de beaux yeux bleus, doux et vifs,
ardents. Mais que m'importe? Je ne désire point les bonnes grâces
de cette innocente.»

En même temps qu'il songeait ainsi, il avait répondu à M. Hervart:
—Je suis bien de votre avis. On tend trop aujourd'hui à confondre ce
qui est curieux ou rare ou ancien, avec ce qui est beau. On a
remplacé le sens esthétique par le respect.
—Cela était peut-être inévitable, dit M. Hervart. Cela convient, en
tout cas, à une démocratie. On n'a pas le temps d'apprendre à
admirer, on peut très vite apprendre à respecter. L'intelligence est
docile. La sensibilité est rebelle.
—Est-ce qu'il n'y a pas, demanda Rose, des admirations spontanées?
—Oui, dit Léonor, il y a l'amour.
—Alors, admirer, c'est aimer?
—Quand ou admire, si on n'aime pas encore, on est bien près
d'aimer.
—Et aimer, c'est admirer?
—Pas toujours.
—L'amour, dit M. Hervart, est compatible avec presque tous les
autres sentiments, et même avec la haine.
—Oui, reprit Léonor, en apparence. Car il y a bien des sortes
d'amour. Celui qui lutte avec la haine ne sera jamais qu'un amour
d'intérêt ou de sensualité.
—On ne sait jamais. Je tiens que l'amour, de même qu'il est prêt à
toutes les métamorphoses, peut dévorer tous les autres sentiments
et s'installer à leur place. Il vient, il s'en va, sans que l'on puisse
comprendre le mécanisme de ses voyages. Il dure deux heures ou
toute la vie....
—Vous confondez les genres, dit Léonor. D'ailleurs, pour s'entendre,
il faut laisser aux mots leur sens traditionnel, avec toutes ses
nuances. L'amour est au fond de tous les sentiments comme
négation ou comme affirmation: on peut dire cela, et quand on a dit
cela, on n'a rien dit. Croyez-vous que cela soit en vain que l'usage

verbal emploie les mots de passion, caprice, inclination, goût,
curiosité, sympathie et tant d'autres? Il faudrait plutôt, je crois, créer
des nuances nouvelles que de s'ingénier à fondre en une seule teinte
toutes les couleurs et toutes les nuances de la sensation et du
sentiment.
Pareille à un musicien de village qui entendrait discuter contrepoint
ou orchestration, Rose écoutait, un peu inquiète, un peu colère, et
pourtant charmée. On parlait de ce qui lui remplissait le cœur, de ce
qui tendait ses nerfs; elle ne comprenait pas, elle sentait. Elle aurait
voulu comprendre.
«Xavier m'expliquera tout cela. J'ai l'air d'une sotte au milieu de ces
discours où je ne puis placer un mot.»
Elle feignit de désirer une rose trop haute pour sa main. M. Hervart
se précipita, atteignit la fleur, se mit à dépouiller la branche de ses
épines, de son excès de bois et de feuilles.
—Ce n'est pas celle que je voulais, dit Rose.
M. Hervart recommença, cependant que la jeune fille jouissait
extrêmement d'avoir, par un caprice, interrompu une conversation
sérieuse.
Léonor les considérait avec une certaine ironie. Rose s'en aperçut, se
sentit rougir et disparut.
M. Hervart et Léonor continuèrent leur promenade et leur causerie,
mais ils ne parlèrent plus de l'amour.
IX
L'heure du déjeuner fut agréable pour Rose. Les regards, les désirs,
les propos venaient vers elle. M. Lanfranc galantisait sans indécence.
Elle riait, puis, soudain sérieuse, acceptait quelque contact avec les
gestes de son voisin, M. Hervart. Léonor ne se permit que des

phrases brèves, qui voulaient résumer les discours plus ingénus des
convives. L'œil de cette jeune fille, qu'il croyait dédaigner, le
surexcitait; mais à force de vouloir paraître un homme supérieur, il
parut un homme désagréable. Rose en eut peur.
«Qu'il est sec! songeait-elle. Comment parler, comment jouer avec
un homme si sûr de ses mouvements? Il gagnerait toujours.»
Plusieurs fois, avec une inconscience innocente, elle regarda
tendrement M. Hervart.
«Comme j'ai bien choisi! Voici un homme plus jeune que mon ami,
plus près de moi, et chacun de ses gestes, chacune de ses paroles
me rapproche encore de Xavier. Je sens bien qu'il en sera toujours
ainsi. Qui pourrait lutter avec lui? Xavier, je l'aime!»
En se penchant pour atteindre une carafe, elle murmura dans la
figure de M. Hervart:
—Xavier, je t'aime!
M. Hervart feignit de s'étrangler. Sa rougeur fut mise sur le compte
d'un noyau de cerise, et Lanfranc imagina quelques pauvres facéties.
Comme le déjeuner s'achevait, elle dit avec une franchise perverse:
—M. Hervart, voulez-vous venir avec moi, voir s'il ne manque rien là-
bas?
—J'ai fait servir le café dans le haut du jardin, dit Mme
des Boys.
Lanfranc vanta cet usage campagnard.
Sitôt que les massifs les dissimulèrent, Rose, sans mot dire, prit M.
Hervart par les épaules et lui offrit ses lèvres. Ce fut un long baiser.
Xavier serrait la jeune fille dans ses bras et lentement, avec une
tendresse où il y avait beaucoup de science, il aspirait son âme, son
haleine et aussi un peu de salive.
Quand il releva la tête, à bout de respiration, il était confus:
«J'ai donné un baiser d'amant et on me demandait un baiser
d'amoureux. Que va-t-elle penser de moi?»

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