Essentials of jitter part 1 The Time Interval Error: TIE

Essential Principles of Jitter, or Jitter 101
1
1
Introduction to Jitter: The Time Interval Error: TIE
2
Jitter Synthesis: The Jitter Components
3
Jitter Analysis Extrapolation and Decomposition
Teledyne LeCroy Signal Integrity Academy

Jitter is confusing

A lot of different terms used seemingly at random

Not a lot of formal training available

Sometimes a high math barrier

Wide spectrum of expertise in the industry

A lot of information publically available

Not all of it accurate

Not all of it understandable

Who do you believe?

In practice, definition is also variable

Many myths and myth-conceptions

Our goal: a little smoothing on a noisy subject
2
Random Jitter - Rj
Total Jitter - Tj
Deterministic Jitter - Dj
Data Dependent Jitter - DDj
Intersymbol interference - ISI
Duty Cycle Distortion - DCD
Periodic Jitter - Pj
Bounded Uncorrelated Jitter - BUJ
Unbounded Jitter
Correlated Jitter
Uncorrelated Jitter
Dual-Dirac Model
Jitter PDF
Bathtub curve
Jitter Spectrum
Jitter Track
Jitter Histogram
Jitter CDF
Jitter Transfer Function
PLL Transfer Function

Why Care about Jitter?
The goal of a serial data channel design:
Transmit data from TX to RX without (many) bit errors
… Jitter is one of the major root causes of bit errors
3
Source: PCI Express 2.0 Electrical Overview Presentation (w/revised text)
A typical channel consists
of multiple structures and jitter sources

Bit is hi, but, latched as “0”
Jitter  Bit Errors

Timing jitter causes edges to arrive early/late compared to an expected arrival time
Wrong edge timing  Incorrect latching  Bit error
Example: When latching edge at time of vertical cursor, bit level = 0
4
Latch (strobe) time
Crossing
detection level
Edge is too late!

Jitter is at the Core of Many Specs

Electrical specs include budget & limits… USB30: Teledyne LeCroy Signal Integrity Academy 5
Typical RX mask (PCIe)
Total jitter ~ 60% UI

Definition of Timing Jitter

Measurement-based definition:
Timing jitter is measured by the Time Interval Error (TIE)

TIE results can be a histogrammed, tracked, FFT’d, separated, decomposed, averaged, etc, etc, etc.

Extract various “figures of merit” about the TIE
Teledyne LeCroy Signal Integrity Academy 6

Everything about jitter starts with the TIE
Measured Arrival Time of an edge
– Expected Arrival Time for the edge
= Time Interval Error for the edge
TIE describes how early or late an edge arrives compared to its expected arrival time
Multi-step process to make the measurement
Signal is late
ref
data
Interpolate
early late
TIE value

The easy part: Determination of Measured (or simulated) Arrival Times

What gets done on a real-time digital oscilloscope:

Determine the crossing times
8
Edge arrival time
Next Step: find the expected arrival time
Sample points
Interpolated

The Hard Part: Determination of Expected Arrival Times

Two scenarios relating to signaling methods:
1.
(easy) A reference clock and/or strobe is transmitted

e.g., DDR, clock/strobe signal latches bit
2.
(hard) No clock signal is transmitted

e.g., USB: clock and data recovery circuit needed
How does a musician extract the “beat” from a symphony?

Determination of Expected Arrival Times Scenario 2: Data only, no reference clock signal
Software Clock Data Recovery (CDR) Steps:
Step 1: Determine underlying bit rate and phase
Step 2: Determine expected arrival times

Software CDR Algorithm method 2a, Determine the bit rate (clock) from edge arrival times

Bit rate is determined by analysis of edge time intervals

Example algorithm:
Take successive rising edges (gets around duty cycle variation) and histogram the delta-T
Analyze to determine first-pass bit rate
Plot edge time vs. cumulative # UI’s
Find slope
UI = average interval /# of bits
Synthesize a clock at ½ the data rate
11
Histogram of time between successive rising edges
200 ps
400 ps
600 ps
800 ps
2 UI
4 UI
6 UI
8 UI

Software CDR Algorithm method 2b, Phase Locked Loop (PLL)

Start with a rough guess of the bit rate

Adjust the clock frequency and phase to minimize the TIE of the entire waveform

Corrects for low-frequency jitter or “wander” in underlying clock

Oscilloscopes let you select from various PLL types

The PLL

The SW CDR locally corrects for some clock drift

Oscilloscope software emulates the PLL in a receiver

Use a PLL that best matches your receiver
Output frequency of PLL IS the recovered clock, used as the new reference for “expected” arrival time
How the PLL works

Variation of TIE: The TIE Track Waveform

Measure TIE values, one for each edge, over time

Plot TIE over time, called the TIE Track (jitter)

Create a waveform out of the TIE measurements (interpolate as continuous signal)

Shows how the TIE values change in the same time base as the source signal.

This is the data set to be used for all jitter analysis

Pk-Pk, sdev, histogram analysis
Interpolate
early late
TIE value

Analysis of the TIE Track Waveform (it is the jitter)
Teal is the data signal, 1 usec/div
Yellow is the TIE track, 1.84 psec/div, vertical scale, 1 usec/div time base
3 psec
jitter
10 Gbps, UI = 100 psec, jitter pk-pk ~ 3% of period
Interpolate
early late
TIE value
1 usec/div

PLL tracks out LF Jitter, or “Wander”

Data signal with low frequency jitter
Goal of the PLL is to track out low-frequency jitter
The jitter that remains is what’s important
Using PLL to recover clock:
1 usec/div

Data Mining the TIE Track Waveform (Jitter Analysis)

Look at TIE measurements in different ways:

Your scope may/may have the TIE measurement standard

Could depend on SW optioning

TIE extraction is performed “under the hood”
17
Statistical analysis
Pk-pk, SDEV, max, min
Histogram analysis
Are there multiple peaks? Skew?
Shape gives insight into jitter sources
Frequency analysis
Peaks & harmonics
Time-domain analysis
Lets you see the modulation scheme
Additional tools
Eye diagrams, Crosstalk Eye, ISI Plot, DDJ Plot & histogram

Four General Patterns from Different Causes of Jitter seen in the Histograms of the TIE
18
Periodic Jitter
Intersymbol Interference
Duty Cycle Distortion
Random Jitter

Alan Blankman Product Manager, High Speed Serial Data Products, Teledyne LeCroy

Session 1 Summary

Measuring jitter is important

Jitter causes bit errors, and bit errors are bad

Specifications define jitter budget & methodology

At its core, jitter is the TIE Track: the variation in TIE over time
TIE = Measured Arrival time – Expected Arrival time

Many ways of turning complex TIE Track Waveforms into meaningful figures of merit (FoM)

The Teaser: Session 2 Jitter Synthesis: The Components of Jitter Open for registration: http://teledynelecroy.com/events

Clock signals vs. data signals:

different signals, different analysis requirements

Types of jitter on NRZ serial data waveforms

Descriptions and demonstrations

Intro to the Dual-Dirac jitter model

For More Information
Slides can be downloaded here: www.beTheSignal.com
Coming soon:
Teledyne LeCroy Signal Integrity Academy - Online video training
Published by Prentice Hall, 2009
22
@beTheSignal

Q&A

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
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
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Essentials of jitter part 1 The Time Interval Error: TIE

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Essentials of jitter part 1 The Time Interval Error: TIE