The document presents a thesis on implementing and optimizing cache-aware time-skewing algorithms for FDTD kernels to reduce cache misses and processor idle time. The main goals were to generate and validate 1D and 2D FDTD codes, analyze data dependencies and loop iterations, find optimal tiling and skewing, and measure improvements in cache profiling and execution time from applying these optimizations. The results demonstrated enhancements over naive FDTD implementations and validated the effectiveness of the proposed cache-aware algorithms and time-skewing techniques.