Lecture 12 (adc) rv01

Lecture 12
Analog to Digital Converters

2
Analog to Digital Converters
 What is an ADC?
 Output vs. input
 Input range
 Single-ended vs. differential inputs
 Output coding: unipolar vs. bipolar
 Recap: C8051F020 analog peripherals
 12-bit ADC (ADC0)
 Starting ADC0 conversions
 Data word conversion map (12-bit)
 Programming ADC0
 Detecting ADC0 end-of-conversion
 SAR0 conversion clock frequency
 ADC0 programming example—polling method
 ADC0 programming example—interrupt method
 Appendix: 8-bit ADC (ADC1)

3
What is an ADC?
 ADC is the acronym for analog-to-digital converter
 An ADC takes an analog voltage at its input and produces a
digital number representing that voltage at its output
Analog Input (V)
DigitalOutput(codes)
0
Full-
Scale
0
(2N
)-1
ADC Transfer
Function

4
Output vs. Input
 The output of an ADC is different from the input in two distinct ways:
1. The input signal to the ADC is a continuous voltage, while the ADC output
has been quantized to discrete steps that are represented as digital codes
2. The input signal is continuous in time, while the output is a series of
discrete-time points
Time
Magnitude
Continuous-time signal
Discrete-time, quantized data

5
ADC—Input Range
 An ADC’s input range is defined by the reference voltage
(VREF) provided to the ADC
 The power supplies to the ADC are also important in
determining the absolute input voltage
 In most ADC architectures, input voltages outside the supply rails
cannot be measured and may cause damage to the device

6
ADC—Single-Ended
 A “single-ended” ADC is one where a single input voltage is measured
with respect to ground (AIN–GND).
 Most single-ended ADCs have an input range from 0V to VREF
 Common Problem: Input circuitry’s maximum output higher than VREF
ADC
V+
VREF
AIN
Reference
Voltage
Ground-
Referenced
Input Signal
Digital Output

7
ADC—Single-Ended Supply Measurement
 One example of a single-ended voltage measurement is monitoring the
supply to the system—the supply is divided down to within the input
range of the ADC using a resistive divider
ADC
V+
VREF
AIN
Digital Output
V+
R
R
+
-
½ V+

8
ADC—Differential
 For a differential ADC, the difference in voltage between two pins is
measured (AIN+ - AIN-)
 The input range of a differential converter is –VREF to +VREF, or twice the
range of a single-ended converter
 Common Problem: Input circuitry designed to go below ground when supply
to ADC is only positive
ADC
V+
VREF
AIN+
Reference
Voltage
Differential
Input Signal
Digital Output
AIN-

9
ADC—Differential
ADC
V+
VREF
AIN+ Digital Output
AIN-
1V 2V
-1V
+
-
 A “negative” differential measurement does not require a negative input
voltage
 If the difference between AIN+ and AIN- is negative, a negative output
will be produced
 If AIN+ = 1 V and AIN- = 2 V, the input to the ADC is
(AIN+ - AIN-) = (1 V – 2 V) = -1 V

10
ADC—Differential Bridge Measurement
 An example of a differential input signal is a bridge measurement
(such as a load cell)
 The voltage of interest is the difference across the bridge
ADC
V+
VREF
AIN+ Digital Output
AIN-
V+

11
ADC—Output Coding
 The output code range of an ADC is 2N
, where N is the number of bits in
the output word
 The digital output from an ADC represents the voltage present at the
input, as a fraction of the reference voltage. With a single-ended
converter whose input range is 0 V to VREF
Output = (VIN / VREF) x 2N
; N = number of bits in output word
 To calculate the input voltage from the output code:
VIN = VREF x (Output / 2N
); N = number of bits in output word
 The term “LSB” is commonly used to refer to the amount of input voltage
required to produce a single-code change at the output
 One LSB = input voltage range/output code range
 Example: For a single-ended 12-bit ADC using a 2.4 V reference,
one LSB = (VREF / 212
) = (2.4 V / 4096) = 0.59 mV

12
ADC—Unipolar Output Coding
 Unipolar output coding is used when the input signal to the
ADC is positive
 For a single-ended converter, output coding is normally
unipolar
 Unsigned binary encoding is used to represent unipolar
output
Input Voltage Output Code (12-bit)
>= VREF 4095 (0x0FFF)*
VREF – 1 LSB 4095 (0x0FFF)
½ VREF 2048 (0x0800)
¼ VREF 1024 (0x0400)
0 V 0 (0x0000)
* Output of ADC is saturated

13
ADC—Bipolar Output Coding
 Bipolar output coding is used when the input to the converter can be
positive or negative, as with a differential converter
 For a differential converter, the input range is doubled, which also
doubles the size of the LSB
 2’s-complement binary encoding is typically used to represent bipolar
output
Input Voltage Output Code
(12-bit, sign extended)
>= VREF 2047 (0x07FF)*
VREF – 1 LSB 2047 (0x07FF)
½ VREF 1024 (0x0400)
0 V 0 (0x0000)
- ½ VREF -1024 (0xFC00)
-VREF -2048 (0xF800)
< -VREF -2048 (0xF800)*
*Output of ADC is saturated

14
Recap—C8051F020 Analog Peripherals
 C8051F020 contains the following analog peripherals:
 One 8-bit and one 12-bit analog-to-digital converters (ADC)
 Two 12-bit digital-to-analog converters (DAC)
 Programmable gain amplifiers (PGAs)
 Analog multiplexer (8-channel and 9-channel)
 Two analog comparators
 Precision voltage reference
 Temperature sensor

16
12-Bit ADC (ADC0)
 The ADC0 subsystem consists of:
 9-channel, configurable analog multiplexer (AMUX0)
 8 channels for external input
• Single-ended inputs
• Differential input pairs
 9th channel for on-chip temperature measurement
 Programmable gain amplifier (PGA0)
 Default gain is 1
 Gain can be programmed to be 0.5, 1, 2, 4, 8 or 16
 12-bit Successive approximation register (SAR) ADC
 ADC0 is enabled by setting AD0EN (ADC0CN.7) to 1

17
Starting ADC0 Conversions
 Conversions can be started in four different ways (depending on the
AD0CM1 and AD0CM0 bits in ADC0CN register)
1. Software command (writing 1 to AD0BUSY)
2. Overflow of timer 2
4. External signal input (rising edge of CNVSTR)
 The AD0BUSY bit remains set to 1 during conversion and restored to 0
when the conversion is complete
 The falling edge of AD0BUSY triggers an interrupt (when enabled) and
sets the AD0INT interrupt flag (ADC0CN.5)
 If ADC0 end-of-conversion interrupt (EIE2.1) is enabled, then an
interrupt will be generated when AD0INT is set and the appropriate
ADC0 ISR will be executed

18
Data Word Conversion Map (12-bit)
 Converted data is stored in the ADC0H and ADC0L registers and can
be either left- or right-justified in the register pair depending on the
programmed state of the AD0LJST (ADC0CN.0) bit
 ADC0H[3:0]:ADC0L[7:0], if AD0LJST = 0
(ADC0H[7:4] will be 0000b)
 ADC0H[7:0]:ADC0L[7:4], if AD0LJST = 1
(ADC0L[3:0] = 0000b)
 The mapping of the ADC0 analog inputs to the ADC0 data word
registers is given by:
where n=12 for single-ended and n=11 for differential inputs
n
VREF
Gain
VinCodeADC 20 
ADC0H ADC0L
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

19
 Suppose AIN0 is used as the input in single-ended mode
(AMX0CF=00H and AMXSL=00H) and gain is set to 1
4096
4095
VREF
2
VREF
4096
2047
VREF
AIN0 – AGND (Volts)
ADC0H:ADC0L
(AD0LJST=0)
Right Justified
ADC0H:ADC0L
(AD0LJST=1)
Left Justified
0FFFH FFF0H
0800H 8000H
07FFH 7FF0H
0 0000H 0000H

20
Programming ADC0
 ADC0 can be programmed through the following sequence
 Step 1: configure the voltage reference (REF0CN)
 Step 2: set the SAR0 conversion clock frequency and PGA0 gain
(ADC0CF)
 Step 3: configure the multiplexer input channels (AMX0CF)
 Step 4: select the desired multiplexer input channel (AMX0SL)
 Step 5: set the appropriate control bits and start-of-conversion mode
and turn on ADC0 (ADC0CN)

21
Configuring the ADC0 Voltage Reference
2.4V Output of
Internal VREF

22
Reference Control Register—REF0CN
Bit Symbol Description
7-5 - Unused. Read=000b; Write=Don’t care.
4 AD0VRS
ADC0 Voltage Reference Select
0: ADC0 voltage reference from VREF0 pin.
1: ADC0 voltage reference from DAC0 output.
3 AD1VRS
ADC1 Voltage Reference Select
0: ADC1 voltage reference from VREF1 pin.
1: ADC1 voltage reference from AV+
2 TEMPE
Temperature Sensor Enable Bit
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.
1 BIASE
ADC/DAC Bias Generator Enable Bit.
(Must be ‘1’ if using ADC or DAC)
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
0 REFBE
Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage
reference is driven on the VREF pin.

23
ADC0CF—ADC0 Configuration Register
10
0

SARCLK
SYSCLK
SCAD
7-3 AD0SC4-0
ADC0 SAR0 Conversion Clock frequency Bits
SAR0 Conversion clock is derived from system clock by
the following equation, where AD0SC refers to the 5-bit
value in AD0SC4-0 and CLKSAR0 refers to the desired
ADC0 SAR conversion clock frequency.
2-0 AMP0GN2-0
ADC0 Internal Amplifier Gain (PGA)
000: Gain = 1
001: Gain = 2
010: Gain = 4
011: Gain = 8
10x: Gain = 16
11x: Gain = 0.5

24
SAR0 Conversion Clock Frequency
 The conversion clock has a maximum frequency of 2.5 MHz
 The conversion clock frequency is calculated using the following
equation:
 If the System Clock Frequency is 16 MHz and AD0SC4-0 is set to
10000b, then the SAR0 conversion frequency is 16MHz/17 = 941.176
KHz
 If the value loaded in ADC0CF is 10000000, then the SAR0 conversion
frequency will be 941 KHz approximately and the PGA0 gain will be set
to 1
10
0


SCAD
SYSCLK
CLKSAR

25
AMX0CF—AMUX0 Configuration Register
7-4 - UNUSED. Read=0000, Write=don’t care
3 AIN67IC
AIN6, AIN7 Input Pair Configuration Bit
0: AIN6 and AIN7 are independent single-ended inputs
1: AIN6, AIN7 are (respectively) +,- differential input pair
2 AIN45IC
1 AIN23IC
0 AIN01IC

26
AMX0SL—AMUX0 Channel Selection Register
3-0 AMX0AD3-0
AMX0 Address Bits
0000-1111: ADC Inputs selected according to
channel selection table on next slide.

27
AMUX0 Channel Selection—AMX0SL SFR

28
ADC0CN—ADC0 Control Register

29
Detecting ADC0 End-of-Conversion
 Polling Method
 AD0INT bit (ADC0CN.5) may be polled to determine when a
conversion has completed
 Once the bit is set, read the ADC0 data
 Interrupt Method:
 If ADC0 End-of-Conversion Interrupt (EIE2.1) and global interrupts
are enabled, then an interrupt will be generated and the appropriate
 Inside the ADC0 ISR, read the ADC0 data

30
ADC0 Programming Example—Polling Method
void Init_ADC0(void)
{
REF0CN = 0x07; //Enable internal bias generator and
       //  internal reference buffer
//  Select ADC0 reference from VREF0 pin
//  Internal Temperature Sensor ON
ADC0CF = 0x81; //SAR0 conversion clock=941KHz approx
//  Gain=2
AMX0SL = 0x08; //Select Temp Sensor
ADC0CN = 0x80; //Enable ADC0, Continuous Tracking
      //  Mode Conversion initiated on write to
      //  AD0BUSY; ADC0 data is right justified.
}
void main (void)
{
Device_Init (); // Init device peripherals
AD0BUSY = 1; // Start ADC conversion
while (!AD0INT); // Wait till conversion is complete
ADC0_Value = ADC0; // Store ADC result in variable
AD0INT = 0; // Clear AD0INT flag
while (1); // Spin forever
}

31
 The timer 3 overflow is used to initiate ADC0 conversion
 Timer 3 interrupt is also enabled (not shown in the code)
 Timer 3 ISR is executed as soon at the ADC conversion starts
 Within the timer 3 ISR, we first reset the TF3 (timer 3 overflow flag) and
then poll the AD0INT flag, waiting for it to set to 1
 The AD0INT flag is set when the ADC conversion is complete
 We then read the ADC conversion value from the register ADC0 and
load it into the variable ADC0_reading

32
ADC0 Programming Example-Interrupt Method
 We could also use the ADC0 interrupt, which can be
enabled by setting EADC0 (EIE2.1) and enabling global
interrupts
 The ISR for ADC0 will be called each time the conversion is
completed
 Inside the ISR, we simply need to:
 Read the ADC0 register
 Store the value in a variable
 Clear the AD0INT flag

33
ADC0 Programming Example—Interrupt Method
{
REF0CN = 0x07; // Enable internal bias generator and
//   Internal Temperature Sensor ON
ADC0CF = 0x81; // SAR0 conversion clock=941KHz approx
//   Gain=2
AMX0SL = 0x08; // Select Temp Sensor
ADC0CN = 0x84; // Enable ADC0, Continuous Tracking
      //   Mode, Conversion initiated on Timer
      //   3 overflow, ADC0 data is right
//   justified
EIE2 |= 0x02; // Enable ADC Interrupts
}
//
void ADC0_ISR (void) interrupt 15
{
AD0INT = 0; // Clear ADC0 conversion complete
      //   interrupt flag
ADC0_reading = ADC0; // Read ADC0 data
}

36
8-Bit ADC (ADC1)
 The ADC1 subsystem consists of:
 8-channel, configurable analog multiplexer (AMUX1)
 Programmable gain amplifier (PGA1)
 Default gain is 0.5
 Gain can be programmed to be 0.5, 1, 2 or 4
 8 bit SAR ADC
 ADC1 is enabled by setting AD1EN (ADC1CN.7) to 1

37
Starting ADC1 Conversions
 Conversions can be started in 5 different ways, depending on the ADC1
start of conversion mode bits (AD1CM2-0) in register ADC1CN
1. Software command (writing 1 to AD1BUSY)
4. External signal input (Rising edge of CNVSTR)
5. Writing ‘1’ to the AD0BUSY (ADC0CN.4). (i.e., initiate conversion of ADC1
and ADC0 with a single software command)
 During conversion, the AD1BUSY bit remains set to 1 and is restored
to 0 when the conversion is complete
 The falling edge of AD1BUSY triggers an interrupt (when enabled) and
sets the AD1INT interrupt flag
 Converted data is stored in the ADC1 data word register, ADC1

38
 The mapping of the ADC1 analog inputs to the ADC1 data word register
is much simpler
 There is only one mode of input and the data word does not need to be
justified
2561 
VREF
Gain
VinCodeADC
256
255
VREF
2
VREF
256
127
VREF
AIN1.0 – AGND (Volts) ADC1
FFH
80H
7FH
0 00H

39
Programming ADC1
 ADC1 can be programmed through the following sequence
 Step 1: configure the voltage reference (REF0CN)
 Step 2: configure appropriate pins on Port 1 as analog input
(P1MDIN)
 Step 3: set the SAR1 conversion clock frequency and PGA1 gain
(ADC1CF)
 Step 4: select the desired multiplexer input channel (AMX1SL).
 Step 5: set the appropriate control bits and start of conversion mode
and turn on ADC1 (ADC1CN)

40
ADC1CF—ADC1 Configuration Register
7-
3
AD1SC4-0
ADC1 SAR Conversion Clock frequency Bits
SAR Conversion clock is derived from system clock by
the following equation, where AD1SC refers to the 5-bit
value in AD1SC4-0, and CLKSAR1 refers to the desired
ADC1 SAR conversion clock frequency.
2 - UNUSED. Read=0, Write=don’t care
1-
0
AMP1GN1-
0
ADC1 Internal Amplifier Gain (PGA)
00: Gain = 0.5
01: Gain = 1
10: Gain = 2
11: Gain = 4
11
1

SARCLK
SYSCLK
SCAD

41
SAR1 Conversion Clock Frequency
 The conversion clock has a maximum frequency of 6 MHz
 The conversion clock frequency is calculated using the
following equation:
11
1


SCAD
SYSCLK
CLKSAR

42
AMX1SL—AMUX1 Channel Select Register
3-0 AMX1AD2-0
AMX1 Address Bits
000: AIN1.0 selected

43
ADC1CN—ADC1 Control Register

44
Detecting ADC1 End-of-Conversion
 Polling Method
 AD1INT bit (ADC1CN.5) may be polled to determine when a
conversion has completed
 Once the bit is set, read the ADC1 data
 Interrupt Method
 If ADC1 end-of-conversion interrupt (EIE2.3) and global interrupts
are enabled, then an interrupt will be generated and the appropriate
 Inside the ADC1 ISR, read the ADC1 data

45
{
REF0CN = 0x03; // Enable internal bias generator and
ADC1CF = 0x81; // SAR1 conversion clock=941KHz approx., Gain=1
AMX1SL = 0x00; // Select AIN1.0 input
ADC1CN = 0x82; // Enable ADC1, Continuous Tracking Mode,
//   Conversion initiated on Timer 3 overflow
}
//
// Interrupt Service Routine
void Timer3_ISR (void) interrupt 14
{
TMR3CN &= ~(0x80);   // Clear TF3 flag
// Wait for ADC1 conversion to be over
while ( (ADC1CN |= 0x20) == 0); // Poll for AD1INT>1
ADC1_reading = ADC1; // Read ADC1 data
ADC1CN &= 0xDF; // Clear AD1INT
}

46
ADC1 Programming—Interrupt Method
 Instead of using the polling technique as illustrated in the
code on the previous slide, we could also use interrupt
method
 The ADC1 interrupt can be enabled by setting EADC1
(EIE2.3) and enabling global interrupts
 The ISR for ADC1 will be called each time the conversion is
completed
 Inside the ISR, we simply need to:
 Read the ADC1 register
 Store the value in a variable
 Clear the AD1INT flag

Lecture 12 (adc) rv01

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Lecture 12 (adc) rv01