May 2020: Top Read Articles in VLSI design & Communication Systems

May 2020: Top Read Articles
in VLSI design &
Communication Systems
International Journal of VLSI design & Communication
Systems (VLSICS)
ISSN : 0976 - 1357 (Online); 0976 - 1527(print)
http://airccse.org/journal/vlsi/vlsics.html

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM
Bijal Thakkar1
and V Jayashree2
1
Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
2
Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
ABSTRACT
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because
of its high performance and high-frequency operation without using complex bridges. AXI is also
backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using
AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which
is only possible in the other protocol but it is possible in AXI because it contains different write address
and data channels and AXI also supports out of order transfer based on the transaction ID which is
generated at the start of the transfer. The driver logic for the AXI has been designed and implemented
using the Universal Verification Methodology (UVM).The signaling of the five channels such as write
address, write data, write response, read address, read data channel of AXI protocol are considered for
verification. According to the AXI protocol,the signals of these channels are driven to the interconnect
and results are observed for single master and single slave. The driver logic has been implemented and
verified successfully according to AXI protocol using the Rivera Pro. The results observed for single
master and single slave have shown the correctness of AMBA-AXI design in Verilog.
KEYWORDS
AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible
Interface),UVM(Universal Verification Methodology),channel.
Original Source URL : https://aircconline.com/vlsics/V9N3/9318vlsi03.pdf
http://airccse.org/journal/vlsi/vol9.html

REFERENCES
[1] Amba axi protocol specification, arm, 2011.
[2] Gayathri m, rini sebastian, silpa rose mary, anoop thomas, “a sv-uvm framework verification of sgmii
ip core with reusable axi to wb bridge uvc”, ieee ,3rd international on advance computing and
communication systems,jan 22 & 23 ,2016 ,coimbatore, india.
[3] Rini sebastian, silpa rose mary, gayathri m, anoop thomas, “assertion based verification of sgmii ip
core incorporating axi transaction verification model”, ieee,international conference on control,
communication & computing india (iccc), 19-21 november 2015 , trivandrum.
[4] Golla mahesh, sakthivel.s.m, verification ip for an amba-axi protocol using system verilog,
international journal ofengineering research and general science, volume 3, issue 1, januaryfebruary,
2015.
[5] Mahendra.b.m,ramachandra.a.c, bus functional model verification ip development of axi protocol,
international journal ofengineeringresearch andgeneral science, volume 3, special issue 1, february, 2014
[6] Anusharanga, l. harivenkatesh, venkanna, design and implementation of amba-axi protocol using vhdl
for soc integration, international journal of engineering research and general science, vol. 2, issue4, july-
august 20,2012.
AUTHORS
Bijal Thakkar is currently pursuing her M.Tech in Electronics from Shivaji University,
Ichalkarnji .Doing project in DKTE Society’s Textile & Engineering Institute. She
Obtained her bachelor’s degree in Electronics and communication engineering from
Shivaji University,Kolhapur.Her interest includes,digital circuits design and
Verification.

VLSI DESIGN OF AMBA BASED AHB2APB BRIDGE
Aparna Kharade1
and V. Jayashree2
1
Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
2
Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
ABSTRACT
The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for
highperformance buses to communicate with low-power devices. In the AMBA Advanced High
Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance
memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal
Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB
buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to
communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented
using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable
RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB
Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality
by writing a verification program using UVM in future.
KEYWORDS
AMBA; AHB2APB; SOC; VERILOG; XILINX

REFERENCES
[1] Jaehoon Song, Student member, IEEE et al.,” An Efficient SOC Test Technique by Reusing
On/OffChip Bus Bridge”. IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 56, No.3,
March 2009.
[2] Krishna Sekar, Member, IEEE et al.” Dynamically Configurable Bus Topologies for
HighPerformance On-Chip Communication”. IEEE transactions on very large-scale integration (Vlsi)
systems, vol. 16, no. 10, October 2008.
[3] G. Geetha Reddy et al.,” Implementation of bus bridge between AHB and OCP”. Global Journal of
Advanced Engineering Technologies, Vol 1, Issue4-2012 ISSN: 2277-6370.
[4] Kalluri Usha and T. Ashok Kumar,” AXI To Apb Interface Design Using Verilog”. IOSR Journal of
Electronics and Communication Engineering, p- ISSN: 2278-8735.Volume 8, Issue 5 (Nov. - Dec. 2013),
pg. 01-09.
[5] Vani.R.M and Merope,” Design of AMBA based AHB2APB bridge” IJCSNS international journal of
computer science and network security, vol.10, no.11, November 2010
[6] Priyanka M Shettar1, Ashwin Kumar “Verification IP of AMBA AXI V1.0 Using UVM”. IOSR
Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 3, Ver. II (May -Jun. 2016),
pg. 54-58.
AUTHORS
Aparna Ramesh Kharade is currently pursuing Mtech in electronics from Shivaji
University Kolhapur.completing the project in DKTE Society’s Textile &
Enginnering Institute She obtained her bachelor’s degree in Electronics from
Shivaji University, Kolhapur. She obtained her diploma in Medical Electronics
from Government Polytechnic Miraj. Her research interests are VLSI based
SOC design and verification.

DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON
FPGA
Ramneet Kaur1
and Balwinder Singh2
1,2
Academic and Consultancy Services-Division, Centre for Development of Advanced Computing(C-
DAC), Mohali, India
ABSTRACT
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
KEYWORDS
Finite State Machine; Parking System; Virtex- 5;
Original Source URL : https://aircconline.com/vlsics/V4N3/4313vlsics07.pdf

REFERENCES
[1] Du Shaobo; Sun Shibao;,(2012) "The research and design of intellectual parking system based on
RFID," Fuzzy Systems and Knowledge Discovery (FSKD), 2012 9th International Conference on,
pp.2427-2430.
[2] Gongjun Yan; Weiming Yang; Rawat, D.B.; Olariu, S.,(2011) "SmartParking: A Secure and
Intelligent Parking System," Intelligent Transportation Systems Magazine, IEEE , vol.3, no.1, pp.18-
30.
[3] Liu Liang; Zhang Lei; Xiao Jin; ,(2011) "The simulation of an auto-parking system," Industrial
Electronics and Applications (ICIEA), 2011 6th IEEE Conference on , pp.249-253.
[4] Soh Chun Khang; Teoh Jie Hong; Tan Saw Chin; Shengqiong Wang;(2010) , "Wireless MobileBased
Shopping Mall Car Parking System (WMCPS)," Services Computing Conference (APSCC), 2010 IEEE
Asia-Pacific , pp.573-577.
[5] Gupta, A.; Divekar, R.; Agrawal, M.; ,(2010) "Autonomous parallel parking system for Ackerman
steering four wheelers," Computational Intelligence and Computing Research (ICCIC), 2010 IEEE
International Conference on , pp.1-6.
[6] Hua-Chun Tan; Jie Zhang; Xin-Chen Ye; Hui-Ze Li; Pei Zhu; Qing-Hua Zhao;(2009) , "Intelligent
car-searching system for large park," Machine Learning and Cybernetics, 2009 International Conference
on , vol.6, no., pp.3134-3138.
[7] Srikanth, S.V.; Pramod, P.J.; Dileep, K.P.; Tapas, S.; Patil, M.U.; Sarat, C.B.N.;(2009) , "Design and
Implementation of a Prototype Smart PARKing (SPARK) System Using Wireless Sensor Networks,"
Advanced Information Networking and Applications Workshops, 2009. WAINA '09. International
Conference on , pp.401-406.
[8] Gongjun Yan; Olariu, S.; Weigle, M.C.; Abuelela, M.; ,(2008) "SmartParking: A Secure and
Intelligent Parking System Using NOTICE," Intelligent Transportation Systems, 2008. ITSC 2008. 11th
International IEEE Conference on , pp.569-574.
[9] Tsung-hua Hsu; Jing-Fu Liu; Pen-Ning Yu; Wang-Shuan Lee; Jia-Sing Hsu; ,(2008) "Development of
an automatic parking system for vehicle," Vehicle Power and Propulsion Conference, 2008. VPPC '08.
IEEE , pp.1-6.
[10] Insop Song; Gowan, K.; Nery, J.; Han, H.; Sheng, T.; Li, H.; Karray, F.; ,(2006) "Intelligent Parking
System Design Using FPGA," Field Programmable Logic and Applications, 2006. FPL '06. International
Conference on , pp.1-6.
[11] http://www.ops.fhwa.dot.gov/congestion_report/chapter3.htm#footer14

AUTHORS BIOGRAPHY
Balwinder Singh has obtained his Bachelor of Technology degree from National
Institute of Technology, Jalandhar and Master of Technology degree from University
Centre for Inst. & Microelectronics (UCIM), Punjab University, and Chandigarh in
2002 and 2004 respectively. He is currently serving as Senior Engineer in Centre for
Development of Advanced Computing (CDAC), Mohali and is a part of the teaching
faculty and also pursuing Phd from GNDU Amritsar. He has 8+ years of teaching
experience to both undergraduate and postgraduate students. Singh has published three
books and many papers in the International & National Journal and Conferences. His current interest
includes Genetic algorithms, Low Power techniques, VLSI Design & Testing, and System on Chip.
Ramneet kaur has received the B.Tech. (Electronics and Communication Engineering)
degree from the CTIEMT, Jalandhar affiliated to Punjab Technical University,
Jalandhar in 2011, and presently she is doing M.Tech (VLSI design) degree from
Centre for of Advanced Computing (CDAC), Mohali and working on her thesis work.
Her area of interest is FPGA Implementation and VLSI Design.

EXTENDED K-MAP FOR MINIMIZING MULTIPLE OUTPUT LOGIC
CIRCUITS
Palash Das1
, Bikromadittya Mondal2
1
Department of Computer Science and Technology, Bengal Engineering and Science University,
Shibpur, Howrah, India.
2
Department of Computer Science and Engineering, B P Poddar Institute of Management and
Technology, Kolkata, India.
ABSTRACT
Minimization of multiple output functions of a digital logic circuit is a classic research problem.
Minimal circuit is obtained by using multiple Karnaugh Maps (K-map), one for each function. In
this paper we propose a novel technique that uses a single Karnaugh Map for minimizing
multiple outputs of a single circuit. The algorithm basically accumulates multiple K-Maps into a
single K-Map. Finding minimal numbers of minterms are easier using our proposed clustering
technique. Experimental results show that minimization of digital circuits where more than one
output functions are involved, our extended K-Map approach is more efficient as compare to
multiple K-Map approach.
KEYWORDS
Boolean Algebra, Karnaugh Map, Digital Logic Circuit, Clustering.

REFERENCES
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Publications.
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Vol. 57, No. 6, pp. 713–723.
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AIEE Comm. Electron.,Vol. 72, No. 4, pp. 593–598.
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No. 5, pp. 1417–1444.
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McGrawHill.
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C-20, pp. 925-929.
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the Fast Minimization of Switching Functions”, IEEE Trans. on Computers, Vol. C-26, pp. 757-
764.

MULTISIM DESIGN AND SIMULATION OF 2.2GHz LNA FOR
WIRELESS COMMUNICATION
Oluwajobi F. I, Lawalwasiu
Department of Electrical/Electronic Engineering, RUFUS GIWA Polytechnic, OWO, P.M.B
1019, Nigeria
ABSRACT
This paper presents the work done on the design and simulation of a high frequency low noise
amplifier for wireless communication. The purpose of the amplifier is to amplify the received RF
path of a wireless network. With high gain, high sensitivity and low noise using Bipolar Junction
transistor (BJT). The design methodology requires analysis of the transistor for stability, proper
matching, network selection and fabrication. The BJT transistor was chosen for the design of the
LNA due to its low noise and good gain at high frequency. These properties were confirmed
using some measurement techniques including Network Analyzer, frequency analyzer Probe and
Oscilloscope for the simulation and practical testing of the amplifier to verify the performance of
the designed High frequency Low noise amplifier. The design goals of noise figure of 0.52dB-
0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce 16.8 dB gain across the
0.4–2.2GHz band.
KEYWORDS
Amplifier, Bipolar Junction Transistor, Stability, LNA, Fabrication, Multism

REFERENCES
[1] Dixit, N.: Design And Performance Of Low Voltage, Low Noise 900MHz Amplifier, No. 43-
51, Pp. 26,2006
[2] A.O. Fadamiro1 and E.O. Ogunti Design of a High Frequency and High Sensitive Low Noise
Amplifier Asian Journal of Engineering and Technology (ISSN: 2321 – 2462) Volume 01– Issue
02, June 2013
[3] Yu Lin Wei and Jun De Jin, “A low power low noise amplifier for K-band applications,”
IEEE Microwave and Wireless Components Letters, vol. 19, no. 2, pp. 116-118, Feb. 2009
[4] Bonghyuk Park, Sangsungs Choi, and Songcheol Hong, “A low noise amplifier with tunable
interference rejection for 3.1 to 10.6 GHz UWB systems,” IEEE Microwave and Wireless
Components Letters, vol. 20, no. 1, pp. 40-42, Jan 2010.
[5] Mercer, S.: An Introduction to Low-Noise Amplifier Design, RF Design, Pp.4 2008
[6] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of
cylindrical surrounding double-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42,
no. 10, pp. 1124-1135, Oct. 2011
[7] Shouxian, M.: Dival Band Low Noise Amplifier Design For Bluetooth And Hiper Law
Application. PhD Dissertation In Electrical and Electronics Engineering, Nanyang Technological
University.2006
[8] H. W. Chiu, “A 2.17 dB NF 5 GHz band monolithic CMOS LNA with 10 mW DC power
consumption,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 3, pp. 813-824, March 2005.
[9] Aniket, P.J., Mahaya, S.P., Joshi, B.C.s, Design and Development of Low Noise Amplifier
for RF/MW Receiver. Journal of Scientific Research, Vol.2 Issue 6.2013

EVALUATION OF ATM FUNCTIONING USING VHDL AND FPGA
Manali Dhar1
, Debolina Roy2
and Tamosha Saha3
1
Assistant Professor, Department of Electronics & Communication Engineering,
DSCSDEC, Kolkata, India
2,3
UG Student, Department of Electronics & Communication Engineering,
DSCSDEC, Kolkata, India
ABSTRACT
It has been almost four decades that banks and other financial organizations have been gradually
computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund
Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of
services for the customer. This method uses a computer to transfer debits and credits, with the help of
electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated
Teller Machine) has become an important part in our daily lives. People use ATM for various purposes
such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's
money, it has to be a secure system on which we can rely. We have taken a step towards increasing this
security and integrity by trying to implement the functioning of an ATM using VLSI-based programming,
HDL(Hardware Description Language).The conventional coding languages such as C,C++ are replaced
by VHDL(Very High Speed Integrated Circuit Hardware Description Language) so that the code cannot
be easily hacked or changed. This article consists of an insight into the various functions that can be
performed using an ATM, a brief description of the Coding and the obtained simulation results. It also
consists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50).
KEYWORDS
ATM (Automated Teller Machine), Security, HDL (Hardware Description Language), FPGA (Field
Programmable Gate Array).

REFERENCES
[1] Yingxu Wang and Yanan Zhang, “The Formal Design Model of an Automatic Teller Machine
(ATM)” University of Calgary, Canada, International Journal of Software Science and Computational
Intelligence, 2(1), 102-131, January-March 2010.
[2] Avenet Avenue, user’s guide, Xilinx® Spartan™-3 Development Kit.
[3] Stanley MAZOR and Patricia LINGSTRAAT, "A guide to VHDL (2nd Edition)", copyright 1993,
Kluwer Achedamic Publishers, pp no: 1-1 to 7-16.
[4] http://www.fpga.com.cn/hdl/training/Vhdl_Golden_Reference_Guide.pdf
[5] Peter J. Ashenden and Jim Lewis, "The Designer's Guide to VHDL (3rd Edition)" copyright 2008,
Morgan KJaufmann Publication, pp no:207-225.
[6] Pong P. Chu "RTL Hardware Design Using VHDL, Coding For Efficiency, portability and
Scalability", Willy Interscience a john wilay & sons, inc., Publication, pp no:23-160.
[7] Hardware Implementation of Watchdog Timer for Application in ATM Machine Using Verilog and
FPGA Iqbalur Rahman Rokon, Toufiq Rahman, Md. Murtoza Ali Quader, and Mukit Alam,International
Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan. 7-8, 2012
Dubai
AUTHORS
[1] First Author – Manali Dhar, M.Tech (Microelectronics & VLSI Design), Dr.
Sudhir Chandra Sur Degree Engineering College, Assistant Professor, Dept. of ECE,
JIS Group and madhuja4u@gmail.com
[2] Second Author – Debolina Roy, Final Year B.Tech Student (Electronics &
Communication Engineering), Dr. Sudhir Chandra Sur Degree Engineering College,
JIS Group
[3] Third Author – Tamosha Saha, Final Year B.Tech Student (Electronics &
Communication Engineering), Dr. Sudhir Chandra Sur Degree Engineering College,
JIS Group

SINGLE ELECTRON TRANSISTOR: APPLICATIONS & PROBLEMS
Om Kumar1
and Manjit Kaur2
1,2
VLSI-ES Department, Centre for Development of Advanced Computing, Mohali, India
ABSTRACT
The goal of this paper is to review in brief the basic physics of nanoelectronic device single-electron
transistor [SET] as well as prospective applications and problems in their applications. SET functioning
based on the controllable transfer of single electrons between small conducting "islands". The device
properties dominated by the quantum mechanical properties of matter and provide new characteristics
coulomb oscillation, coulomb blockade that is helpful in a number of applications. SET is able to shear
domain with silicon transistor in near future and enhance the device density. Recent research in SET gives
new ideas which are going to revolutionize the random access memory and digital data storage
technologies.
KEYWORDS
Nanoelectronics; Single-electron transistor; Coulomb blockade, Coulomb oscillation, Quantum dot

REFERENCES
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AUTHORS
Om Kumar
I am a Student of Masters in Technology in VLSI Design, Centre for Development of
Advanced Computing(C-DAC), Mohali, India. My research interests include
Semiconductor Device Physics, Nano electronics.
Manjit Kaur
I am Bachelor in Electronics and communication Engineering, BECT
Gurdaspur,Punjab, India and Masters in Technology in Microelectronics from Punjab
University, Chandigarh, India. Presently working as Design Engineer at Centre for
Development of Advanced Computing(C-DAC), Mohali, India. This institute is a
scientific society of the Ministry of Communications & Information Technology, Govt.
of India, involved in Research and Development with an objective to create focus on Advanced
Information Technologies, High-end Academics & Training relevant to R & D societies. I am associated
with Masters in Technology in VLSI Des ign. My research interests include VLSI design, Low power
VLSI Design techniques, Semiconductor Device Physics, Nano electronics.

COMPARATIVE PERFORMANCE ANALYSIS OF XORXNOR
FUNCTION BASED HIGH-SPEED CMOS FULL ADDER CIRCUITS FOR
LOW VOLTAGE VLSI DESIGN
Subodh Wairya1
, Rajendra Kumar Nagaria2
and Sudarshan Tiwari2
1
Department of Electronics Engineering, Institute of Engineering & Technology (I.E.T), Lucknow, India,
226021
2
Department of ECED, Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India,
211004
ABSTRACT
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our
approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high
performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit
commands a high degree of regularity and symmetric higher density than the conventional CMOS design
style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input
(GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps
in reducing the power consumption and the area of digital circuits while maintaining low complexity of
logic design. This paper analyses, evaluates and compares the performance of various adder circuits.
Several simulations conducted using different voltage supplies, load capacitors and temperature variation
demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power
delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority
of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms
of power, delay and power delay product (PDP). .
KEYWORDS
Hybrid full adder, XOR-XNOR circuit, High Speed, Low Power, Very Large Scale Integrated (VLSI)
Circuits,

REFERENCES
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Article ID 173079, 18 pages.

NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE
CMOS FULL ADDER CIRCUITS
Subodh Wairya1
, Rajendra Kumar Nagaria2
, Sudarshan Tiwari3
Department of Electronics & Communication Engineering, M.N.N.I.T, Allahabad, India
ABSTRACT
This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode
logic family. The objective of this work is to present a new full adder design circuits combined
with current mode circuit in one unit to implement a full adder cell. This paper also discusses a
high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP)
in its structure with conventional static and dynamic CMOS logic circuit. The static Majority
function (bridge) design style enjoys a high degree of regularity and symmetric higher density
than the conventional CMOS design style as well as lower power consumption by using bridge
transistors. This technique helps in reducing power consumption, propagation delay, and area of
digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS
circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results
illustrate the superiority of the new designed adder circuits against the reported conventional
CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay
product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm
process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage
and simulations are carried out on Spectre S. .
KEYWORDS
Full adder, Majority-Not gate, Dynamic circuits, MOSCAP, Power-delay product (PDP), Very
Large Scale Integrated (VLSI) Circuits, Current mode logic, Hybrid XOR-XNOR circuit, Bridge
full adder.
For More Details : http://aircconline.com/vlsics/V2N2/2211vlsics07.pdf
Volume Link : http://airccse.org/journal/vlsi/vol2.html

REFERENCES
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DESIGN OF REVERSIBLE SEQUENTIAL CIRCUIT USING REVERSIBLE LOGIC
SYNTHESIS
Md. Belayet Ali1
, Md. Mosharof Hossin1
and Md. Eneyat Ullah1
1
Department of Computer Science and Engineering Mawlana Bhashani Science and Technology
University, Santosh, Tangail-1902, Bangladesh
ABSTRACT
Reversible logic is one of the most vital issue at present time and it has different areas for its
application, those are low power CMOS, quantum computing, nanotechnology, cryptography,
optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular
automata, communication, computer graphics. It is not possible to realize quantum computing
without implementation of reversible logic. The main purposes of designing reversible logic are
to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper,
we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by
using our proposed gate and Peres gate. The proposed designs are better than the existing
proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is
more efficient and less costly than other realizations.
KEYWORDS
Reversible logic, Reversible gate, Power dissipation, Flip-Flop, Garbage, BME gate.
For More Details : http://aircconline.com/vlsics/V2N4/2411vlsics04.pdf
Volume Link : http://airccse.org/journal/vlsi/vol2.html

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December 2011 45
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