June 2021: Top Read Articles in VLSI design & Communication Systems

June 2021: Top Read
Articles in VLSI design &
Communication Systems
International Journal of VLSI design &
Communication Systems (VLSICS)
ISSN: 0976 - 1357 (Online); 0976 - 1527(print)
http://airccse.org/journal/vlsi/vlsics.html

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM
Bijal Thakkar1
and V Jayashree2
1
Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
2
Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
ABSTRACT
Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because
of its high performance and high-frequency operation without using complex bridges. AXI is also
backwardcompatible with existing AHB and APB interfaces. So verification of driver logic using
AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which
is only possible in the other protocol but it is possible in AXI because it contains different write address
and data channels and AXI also supports out of order transfer based on the transaction ID which is
generated at the start of the transfer. The driver logic for the AXI has been designed and implemented
using the Universal Verification Methodology (UVM).The signaling of the five channels such as write
address, write data, write response, read address, read data channel of AXI protocol are considered for
verification. According to the AXI protocol,the signals of these channels are driven to the interconnect
and results are observed for single master and single slave. The driver logic has been implemented and
verified successfully according to AXI protocol using the Rivera Pro. The results observed for single
master and single slave have shown the correctness of AMBA-AXI design in Verilog.
KEYWORDS
AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible
Interface),UVM(Universal Verification Methodology),channel.
Original Source URL : https://aircconline.com/vlsics/V9N3/9318vlsi03.pdf
http://airccse.org/journal/vlsi/vol9.html

REFERENCES
[1] Amba axi protocol specification, arm, 2011.
[2] Gayathri m, rini sebastian, silpa rose mary, anoop thomas, “a sv-uvm framework verification of sgmii
ip core with reusable axi to wb bridge uvc”, ieee ,3rd international on advance computing and
communication systems,jan 22 & 23 ,2016 ,coimbatore, india.
[3] Rini sebastian, silpa rose mary, gayathri m, anoop thomas, “assertion based verification of sgmii ip
core incorporating axi transaction verification model”, ieee,international conference on control,
communication & computing india (iccc), 19-21 november 2015 , trivandrum.
[4] Golla mahesh, sakthivel.s.m, verification ip for an amba-axi protocol using system verilog,
international journal ofengineering research and general science, volume 3, issue 1, januaryfebruary,
2015.
[5] Mahendra.b.m,ramachandra.a.c, bus functional model verification ip development of axi protocol,
international journal ofengineeringresearch andgeneral science, volume 3, special issue 1, february, 2014
[6] Anusharanga, l. harivenkatesh, venkanna, design and implementation of amba-axi protocol using vhdl
for soc integration, international journal of engineering research and general science, vol. 2, issue4, july-
august 20,2012.
AUTHORS
Bijal Thakkar is currently pursuing her M.Tech in Electronics from Shivaji University,
Ichalkarnji .Doing project in DKTE Society’s Textile & Engineering Institute. She
Obtained her bachelor’s degree in Electronics and communication engineering from
Shivaji University,Kolhapur.Her interest includes,digital circuits design and
Verification.

VLSI DESIGN OF AMBA BASED AHB2APB BRIDGE
Aparna Kharade1
and V. Jayashree2
1
Research Scholar, Electronics Dept., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
2
Professor, Electronics Dept ., D.K.T.E. Society's Textile and Engineering Institute, Ichalkaranji,
Maharashtra, India.
ABSTRACT
The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for
highperformance buses to communicate with low-power devices. In the AMBA Advanced High
Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance
memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal
Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB
buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to
communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented
using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable
RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB
Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality
by writing a verification program using UVM in future.
KEYWORDS
AMBA; AHB2APB; SOC; VERILOG; XILINX

REFERENCES
[1] Jaehoon Song, Student member, IEEE et al.,” An Efficient SOC Test Technique by Reusing
On/OffChip Bus Bridge”. IEEE Transactions on Circuits and Systems-I: Regular Papers, Vol. 56, No.3,
March 2009.
[2] Krishna Sekar, Member, IEEE et al.” Dynamically Configurable Bus Topologies for
HighPerformance On-Chip Communication”. IEEE transactions on very large-scale integration (Vlsi)
systems, vol. 16, no. 10, October 2008.
[3] G. Geetha Reddy et al.,” Implementation of bus bridge between AHB and OCP”. Global Journal of
Advanced Engineering Technologies, Vol 1, Issue4-2012 ISSN: 2277-6370.
[4] Kalluri Usha and T. Ashok Kumar,” AXI To Apb Interface Design Using Verilog”. IOSR Journal of
Electronics and Communication Engineering, p- ISSN: 2278-8735.Volume 8, Issue 5 (Nov. - Dec. 2013),
pg. 01-09.
[5] Vani.R.M and Merope,” Design of AMBA based AHB2APB bridge” IJCSNS international journal of
computer science and network security, vol.10, no.11, November 2010
[6] Priyanka M Shettar1, Ashwin Kumar “Verification IP of AMBA AXI V1.0 Using UVM”. IOSR
Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 3, Ver. II (May -Jun. 2016),
pg. 54-58.
AUTHORS
Aparna Ramesh Kharade is currently pursuing Mtech in electronics from Shivaji
University Kolhapur.completing the project in DKTE Society’s Textile &
Enginnering Institute She obtained her bachelor’s degree in Electronics from
Shivaji University, Kolhapur. She obtained her diploma in Medical Electronics
from Government Polytechnic Miraj. Her research interests are VLSI based
SOC design and verification.

DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGA
Ramneet Kaur1
and Balwinder Singh2
1,2
Academic and Consultancy Services-Division, Centre for Development of Advanced Computing(C-
DAC), Mohali, India
ABSTRACT
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
KEYWORDS
Finite State Machine; Parking System; Virtex- 5;
Original Source URL : https://aircconline.com/vlsics/V4N3/4313vlsics07.pdf

REFERENCES
[1] Du Shaobo; Sun Shibao;,(2012) "The research and design of intellectual parking system based on
RFID," Fuzzy Systems and Knowledge Discovery (FSKD), 2012 9th International Conference on,
pp.2427-2430.
[2] Gongjun Yan; Weiming Yang; Rawat, D.B.; Olariu, S.,(2011) "SmartParking: A Secure and
Intelligent Parking System," Intelligent Transportation Systems Magazine, IEEE , vol.3, no.1, pp.18-
30.
[3] Liu Liang; Zhang Lei; Xiao Jin; ,(2011) "The simulation of an auto-parking system," Industrial
Electronics and Applications (ICIEA), 2011 6th IEEE Conference on , pp.249-253.
[4] Soh Chun Khang; Teoh Jie Hong; Tan Saw Chin; Shengqiong Wang;(2010) , "Wireless MobileBased
Shopping Mall Car Parking System (WMCPS)," Services Computing Conference (APSCC), 2010 IEEE
Asia-Pacific , pp.573-577.
[5] Gupta, A.; Divekar, R.; Agrawal, M.; ,(2010) "Autonomous parallel parking system for Ackerman
steering four wheelers," Computational Intelligence and Computing Research (ICCIC), 2010 IEEE
International Conference on , pp.1-6.
[6] Hua-Chun Tan; Jie Zhang; Xin-Chen Ye; Hui-Ze Li; Pei Zhu; Qing-Hua Zhao;(2009) , "Intelligent
car-searching system for large park," Machine Learning and Cybernetics, 2009 International Conference
on , vol.6, no., pp.3134-3138.
[7] Srikanth, S.V.; Pramod, P.J.; Dileep, K.P.; Tapas, S.; Patil, M.U.; Sarat, C.B.N.;(2009) , "Design and
Implementation of a Prototype Smart PARKing (SPARK) System Using Wireless Sensor Networks,"
Advanced Information Networking and Applications Workshops, 2009. WAINA '09. International
Conference on , pp.401-406.
[8] Gongjun Yan; Olariu, S.; Weigle, M.C.; Abuelela, M.; ,(2008) "SmartParking: A Secure and
Intelligent Parking System Using NOTICE," Intelligent Transportation Systems, 2008. ITSC 2008. 11th
International IEEE Conference on , pp.569-574.
[9] Tsung-hua Hsu; Jing-Fu Liu; Pen-Ning Yu; Wang-Shuan Lee; Jia-Sing Hsu; ,(2008) "Development of
an automatic parking system for vehicle," Vehicle Power and Propulsion Conference, 2008. VPPC '08.
IEEE , pp.1-6.
[10] Insop Song; Gowan, K.; Nery, J.; Han, H.; Sheng, T.; Li, H.; Karray, F.; ,(2006) "Intelligent Parking
System Design Using FPGA," Field Programmable Logic and Applications, 2006. FPL '06. International
Conference on , pp.1-6.
[11] http://www.ops.fhwa.dot.gov/congestion_report/chapter3.htm#footer14

AUTHORS BIOGRAPHY
Balwinder Singh has obtained his Bachelor of Technology degree from National
Institute of Technology, Jalandhar and Master of Technology degree from University
Centre for Inst. & Microelectronics (UCIM), Punjab University, and Chandigarh in
2002 and 2004 respectively. He is currently serving as Senior Engineer in Centre for
Development of Advanced Computing (CDAC), Mohali and is a part of the teaching
faculty and also pursuing Phd from GNDU Amritsar. He has 8+ years of teaching
experience to both undergraduate and postgraduate students. Singh has published three
books and many papers in the International & National Journal and Conferences. His current interest
includes Genetic algorithms, Low Power techniques, VLSI Design & Testing, and System on Chip.
Ramneet kaur has received the B.Tech. (Electronics and Communication Engineering)
degree from the CTIEMT, Jalandhar affiliated to Punjab Technical University,
Jalandhar in 2011, and presently she is doing M.Tech (VLSI design) degree from
Centre for of Advanced Computing (CDAC), Mohali and working on her thesis work.
Her area of interest is FPGA Implementation and VLSI Design.

MULTISIM DESIGN AND SIMULATION OF 2.2GHZ LNA FOR WIRELESS
COMMUNICATION
Oluwajobi F. I, Lawalwasiu
Department of Electrical/Electronic Engineering, RUFUS GIWA Polytechnic, OWO, P.M.B1019,
Nigeria
ABSRACT
This paper presents the work done on the design and simulation of a high frequency low noise amplifier
for wireless communication. The purpose of the amplifier is to amplify the received RFpath of a wireless
network. With high gain, high sensitivity and low noise using Bipolar Junction transistor (BJT). The
design methodology requires analysis of the transistor for stability, proper matching, network selection
and fabrication. The BJT transistor was chosen for the design of the LNA due to its low noise and good
gain at high frequency. These properties were confirmed using some measurement techniques including
Network Analyzer, frequency analyzer Probe and Oscilloscope for the simulation and practical testing of
the amplifier to verify the performance ofthe designed High frequency Low noise amplifier. The design
goals of noise figure of 0.52dB- 0.7dB and bias conditions are Vcc = 3.5 V and Icc= 55 mA to produce
16.8 dB gain across the 0.4–2.2GHz band.
KEYWORDS
Amplifier, Bipolar Junction Transistor, Stability, LNA, Fabrication, Multism

REFERENCES
[1] Dixit, N.: Design And Performance Of Low Voltage, Low Noise 900MHz Amplifier, No. 43-51, Pp.
26,2006
[2] A.O. Fadamiro1 and E.O. Ogunti Design of a High Frequency and High Sensitive Low Noise
Amplifier Asian Journal of Engineering and Technology (ISSN: 2321 – 2462) Volume 01– Issue02, June
2013
[3] Yu Lin Wei and Jun De Jin, “A low power low noise amplifier for K-band applications,”
IEEE Microwave and Wireless Components Letters, vol. 19, no. 2, pp. 116-118, Feb. 2009
[4] Bonghyuk Park, Sangsungs Choi, and Songcheol Hong, “A low noise amplifier with tunable
interference rejection for 3.1 to 10.6 GHz UWB systems,” IEEE Microwave and Wireless Components
Letters, vol. 20, no. 1, pp. 40-42, Jan 2010.
[5] Mercer, S.: An Introduction to Low-Noise Amplifier Design, RF Design, Pp.4 2008
[6] Viranjay M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of cylindrical
surrounding double-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42, no. 10, pp. 1124-
1135, Oct. 2011
[7] Shouxian, M.: Dival Band Low Noise Amplifier Design For Bluetooth And Hiper Law Application.
PhD Dissertation In Electrical and Electronics Engineering, Nanyang TechnologicalUniversity.2006
[8] H. W. Chiu, “A 2.17 dB NF 5 GHz band monolithic CMOS LNA with 10 mW DC power
consumption,” IEEE Trans. Microwave Theory Tech., vol. 53, no. 3, pp. 813-824, March 2005.
[9] Aniket, P.J., Mahaya, S.P., Joshi, B.C.s, Design and Development of Low Noise Amplifier for
RF/MW Receiver. Journal of Scientific Research, Vol.2 Issue 6.2013

EXTENDED K-MAP FOR MINIMIZING MULTIPLE OUTPUT LOGIC CIRCUITS
Palash Das1
, Bikromadittya Mondal2
1
Department of Computer Science and Technology, Bengal Engineering and Science University,Shibpur,
Howrah, India.
2
Department of Computer Science and Engineering, B P Poddar Institute of Management andTechnology,
Kolkata, India.
ABSTRACT
Minimization of multiple output functions of a digital logic circuit is a classic research problem. Minimal
circuit is obtained by using multiple Karnaugh Maps (K-map), one for each function. Inthis paper we
propose a novel technique that uses a single Karnaugh Map for minimizing multiple outputs of a single
circuit. The algorithm basically accumulates multiple K-Maps into a single K-Map. Finding minimal
numbers of minterms are easier using our proposed clustering technique. Experimental results show that
minimization of digital circuits where more than one output functions are involved, our extended K-Map
approach is more efficient as compare to multiple K-Map approach.
KEYWORDS
Boolean Algebra, Karnaugh Map, Digital Logic Circuit, Clustering.

REFERENCES
[1] Boole G. (1954): An Investigation of the Laws of Thought. — New York: Dover Publications.
[2] Shannon C.E. (1938): A symbolic analysis of relay and switching circuits. —Trans. AIEE, Vol. 57,
No. 6, pp. 713–723.
[3] Karnaugh M. (1953): The map method for synthesis of combinatorial logic circuits. — Trans.AIEE
Comm. Electron.,Vol. 72, No. 4, pp. 593–598.
[4] McCluskey E. J. (1956), “Minimization of Boolean functions”, Bell System Tech. J., Vol. 35,No. 5,
pp. 1417–1444.
[5] Quine W. V. (1952), “The problem of simplifying truth tables”, Amer. Math. Month., Vol. 59, No. 8,
pp. 521–531.
[6] Petrick S. K. (1959), “On the minimization of Boolean functions”, Proc. Int. Conf. Information
Processing, Paris: Unesco, pp. 422–423.
[7] McCluskey E. J. (1965), “Introduction to the Theory of Switching Circuits”, New York,
McGrawHill.
[8] Biswas N. N. (1971), “Minimization of Boolean Functions”, IEEE Trans. on Computers, Vol.C-20,
pp. 925-929.
[9] Hong S. J., Cain R. G., Ostapko D. L. (1974), “MINI: A Heuristic Approach for Logic
Minimization”, IBM Journal of Research and Development, Vol. 18, pp. 443-458.
[10] Rhyne V. T., Noe P. S., McKinney M. H., and Pooch U.W. (1977) “A New Technique for the Fast
Minimization of Switching Functions”, IEEE Trans. on Computers, Vol. C-26, pp. 757- 764.

EVALUATION OF ATM FUNCTIONING USING VHDL AND FPGA
Manali Dhar1
, Debolina Roy2
and Tamosha Saha3
1
Assistant Professor, Department of Electronics & Communication Engineering,
DSCSDEC, Kolkata, India
2,3
UG Student, Department of Electronics & Communication Engineering,
DSCSDEC, Kolkata, India
ABSTRACT
It has been almost four decades that banks and other financial organizations have been gradually
computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund
Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of
services for the customer. This method uses a computer to transfer debits and credits, with the help of
electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated
Teller Machine) has become an important part in our daily lives. People use ATM for various purposes
such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's
money, it has to be a secure system on which we can rely. We have taken a step towards increasing this
security and integrity by trying to implement the functioning of an ATM using VLSI-based programming,
HDL(Hardware Description Language).The conventional coding languages such as C,C++ are replaced
by VHDL(Very High Speed Integrated Circuit Hardware Description Language) so that the code cannot
be easily hacked or changed. This article consists of an insight into the various functions that can be
performed using an ATM, a brief description of the Coding and the obtained simulation results. It also
consists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50).
KEYWORDS
ATM (Automated Teller Machine), Security, HDL (Hardware Description Language), FPGA (Field
Programmable Gate Array).

REFERENCES
[1] Yingxu Wang and Yanan Zhang, “The Formal Design Model of an Automatic Teller Machine
(ATM)” University of Calgary, Canada, International Journal of Software Science and Computational
Intelligence, 2(1), 102-131, January-March 2010.
[2] Avenet Avenue, user’s guide, Xilinx® Spartan™-3 Development Kit.
[3] Stanley MAZOR and Patricia LINGSTRAAT, "A guide to VHDL (2nd Edition)", copyright 1993,
Kluwer Achedamic Publishers, pp no: 1-1 to 7-16.
[4] http://www.fpga.com.cn/hdl/training/Vhdl_Golden_Reference_Guide.pdf
[5] Peter J. Ashenden and Jim Lewis, "The Designer's Guide to VHDL (3rd Edition)" copyright 2008,
Morgan KJaufmann Publication, pp no:207-225.
[6] Pong P. Chu "RTL Hardware Design Using VHDL, Coding For Efficiency, portability and
Scalability", Willy Interscience a john wilay & sons, inc., Publication, pp no:23-160.
[7] Hardware Implementation of Watchdog Timer for Application in ATM Machine Using Verilog and
FPGA Iqbalur Rahman Rokon, Toufiq Rahman, Md. Murtoza Ali Quader, and Mukit Alam,International
Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan. 7-8, 2012
Dubai
AUTHORS
[1] First Author – Manali Dhar, M.Tech (Microelectronics & VLSI Design), Dr.
Sudhir Chandra Sur Degree Engineering College, Assistant Professor, Dept. of ECE,
JIS Group and madhuja4u@gmail.com
[2] Second Author – Debolina Roy, Final Year B.Tech Student (Electronics &
Communication Engineering), Dr. Sudhir Chandra Sur Degree Engineering College,
JIS Group
[3] Third Author – Tamosha Saha, Final Year B.Tech Student (Electronics &
Communication Engineering), Dr. Sudhir Chandra Sur Degree Engineering College,
JIS Group

SINGLE ELECTRON TRANSISTOR:APPLICATIONS &PROBLEMS
Om Kumar1
and Manjit Kaur2
1,2
VLSI-ES Department, Centre for Development of Advanced Computing, Mohali, India
ABSTRACT
The goal of this paper is to review in brief the basic physics of nanoelectronic device single-electron
transistor [SET] as well as prospective applications and problems in their applications. SET functioning
based on the controllable transfer of single electrons between small conducting "islands". The device
properties dominated by the quantum mechanical properties of matter and provide new characteristics
coulomb oscillation, coulomb blockade that is helpful in a number of applications. SET is able to shear
domain with silicon transistor in near future and enhance the device density. Recent research in SET gives
new ideas which are going to revolutionize the random access memory and digital data storage
technologies.
KEYWORDS
Nanoelectronics; Single-electron transistor; Coulomb blockade, Coulomb oscillation, Quantum dot

REFERENCES
[1] M. A. Kastner, “The single electron transistor and artificial atoms”, Ann. Phy. (Leipzig), vol. 9, pp.
885-895, 2000.
[2] S. Bednarek, B. Szafran, and J. Adamowski, “Solution of the Poisson Schrodinger problem for a
single-electron transistor”, Phys. Rev. B, Vol. 61, pp. 4461-4464, 2000.
[3] Songphol Kanjanachuchai and Somsak Panyakeow, “Beyond CMOS: Single-Electron Transistors”,
IEEE International Conference on Industrial Technology, Bangkok, Thailand, 2002.
[4] Masumi Saitoh, Hidehiro Harata1ion and Toshiro Hiramoto, “Room-Temperature Demonstration of
Integrated Silicon Single-Electron Transistor Circuits for Current Switching and Analog Pattern
Matching”, IEEE International Electron Device Meeting, San Francisco, USA, 2004.
[5] K. Matsumoto, M. Ishii, K. Segawa, Y. Oka B. J. Vartanian and J. S. Harris, “Room temperature
operation of a single electron transistor made by the scanning tunneling microscope nano oxidation
process for the TiOx/Ti system”, Appl. Phys. Lett. 68 (1), pp. 34-36, 1996.
[6] Ken Uchida, Jugli Kaga, Ryuji Ohba and Akira Toriumi, “Programmable Single-Electron Transistor
Logic for Future Low-Power Intelligent LSI: Proposal and Room-Temperature Operation”, IEEE
Transactions on Electron Devices, Vol. 50, No. 7, July 2003.
[7] T.A. Fulton and G.D. Dolan, “Observation of single electron charging effect in small tunnelling
junction”, Phys. Rev. Lett., Vol. 59, pp. 109-112, July 1987.
[8] Lingjie Guo, Effendi Leobandung and Stephen Y. Chou, “A silicon Single-Electron transistor
Memory operating at room temperature”, Science Vol. 275, pp. 649-651, 1997.
[19] A.N. Cleand, D. Estene, C. Urbina and M.H. Devoret, “An extremely Low noise Photodetector
based on the single electron Transistor” , Journal of Low Temperature Physics, Vol. 93, Nos. 3/4, pp.767-
772, 1993.
[10] R. Knobel, C.s. Yung and A.N. clelanda, “Single -electron transistor as a radio frequency mixer”,
Applied Physics Letters, Vol. 81, No. 3, pp. 532-534, July 2002.

AUTHORS
Om Kumar
I am a Student of Masters in Technology in VLSI Design, Centre for Development of
Advanced Computing(C-DAC), Mohali, India. My research interests include
Semiconductor Device Physics, Nano electronics.
Manjit Kaur
I am Bachelor in Electronics and communication Engineering, BECT
Gurdaspur,Punjab, India and Masters in Technology in Microelectronics from Punjab
University, Chandigarh, India. Presently working as Design Engineer at Centre for
Development of Advanced Computing(C-DAC), Mohali, India. This institute is a
scientific society of the Ministry of Communications & Information Technology, Govt.
of India, involved in Research and Development with an objective to create focus on Advanced
Information Technologies, High-end Academics & Training relevant to R & D societies. I am associated
with Masters in Technology in VLSI Des ign. My research interests include VLSI design, Low power
VLSI Design techniques, Semiconductor Device Physics, Nano electronics.

DESIGN OF HIGH EFFICIENCY TWO STAGE POWER AMPLIFIER IN 0.13UM RF
CMOS TECHNOLOGY FOR 2.4GHZ WLAN APPLICATION
Shridhar R. Sahu1
and Dr. A. Y. Deshmukh2
1
Research Scholar, Department of Electronics Engineering, G. H. Raisoni College of Engineering,
Nagpur, India
2
Professor, Department of Electronics Engineering, G. H. Raisoni College of Engineering, Nagpur, India
ABSTRACT
A two stage CMOS power amplifier is implemented in 0.13µm RF CMOS technology using ADS tool
operating at 2.4 GHz with dc supply of 2.5 V. Driver stage as the input stage and power stage as the
output stage are the two stages. A cascode topology is used in the driver stage and basic topology is used
in the power stage. Output power at 1dB compression point is 20.028 dBm and maximum output power
delivered by this circuit is 22.002 dBm. Power added efficiency calculated at 1 dB compression point is
44.669 % whereas the maximum power added efficiency comes out to be 70.196 %. The input return and
output return losses are -11.132 dB and -12.467 dB respectively. Isolation loss and small signal gain are
calculated to be -61.889 dB and 43.745 dB respectively. This circuit shows power gain of 42.728 dB at
1dB compression point. The total dc current flowing through this circuit is 0.0901 A. MOSFET only bias
circuits are used to reduce total dc current. This circuit is designed for application in WLAN.
KEYWORDS
RFIC, RF CMOS, PAE, Impedance Matching, Cascode Topology

REFERENCES
[1] M.Hella, M.Ismail, “RF CMOS Power Amplifiers: Theory, Design and Implementation”, Ohio State
University
[2] Thomas H. Lee, ”The Design of CMOS Radio Frequency Integrated Circuits”, Second Edition,
Cambridge University Press
[3] Ho Ka Wai, “A 1-V CMOS Power Amplifier for Bluetooth Applications”, Hong Kong University of
Science and Technology, 2002
[4] Kyu Hwan An, “CMOS RF POWER AMPLIFIERS FOR MOBILE WIRELESS
COMMUNICATIONS”, Georgia Institute of Technology, 2009
[5] Ravinder Kumar, Munish Kumar, Balraj, “Design and Implementation of a High Efficiency CMOS
Power Amplifier for Wireless Communication at 2.45 GHz”. 2012 International Conference on
Communication Systems and Network Technologies.
[6] Wenyuan Li, Yulong Tan , “2.4GHz Power Amplifier with Adaptive Bias Circuit”, Institute of RF- &
OEICs Southeast University Nanjing, China, 2012 International Conference on Systems and Informatics
(ICSAI 2012)
[7] G. Monprasert, P. Suebsombut, T. Pongthavornkamol, S. Chalermwisutkul, “2.45 GHz GaN HEMT
ClassAB RF Power Amplifier Design for Wireless Communication Systems”, The Sirindhorn
International Thai-German Graduate School of Engineering (TGGS), King Mongkut’s University of
Technology North Bangkok, IEEE 2010
[8] Yongbing Qian, Wenyuan Li, Zhigong Wang, “2.4-GHz 0.18-µm CMOS Highly Linear Power
Amplifier” Institute of RF- & OE-ICs, Southeast University, 210096 Nanjing, China, The 2010
International Conference on Advanced Technologies for Communications, 2010 IEEE
[9] Cheng-Chi Yen Student Member, IEE and , Huey-Ru Chuang IEEE, “A 0.25um 20-dBm 2.4-GHz
CMOS Power Amplifier With an Integrated Diode Linearizer”, MICROWAVE AND WIRELESS
COMPONENTS LETTERS, VOL. 13, NO. 2, FEBRUARY 2003
[10] Chia-Jun Chang, Po-Chih Wang, Chih-Yu Tsai, Chin-Lung Li, Chiao-Ling Chang, Han-Jung Shih,
MengHsun Tsai, Wen-Shan Wang, Ka-Un Chan, and Ying-Hsi Lin, “A CMOS Transceiver with internal
PA and Digital Pre-distortion For WLAN 802.11a/b/g/n Applications”, 2010 IEEE Radio Frequency
Integrated Circuits Symposium
[11] Yi Zhao, John R. Long, and Marco Spirito, “A 60GHz-band 20dBm Power Amplifier with 20% Peak
PAE”, 2011 IEEE
[12] Ville Saari, Pasi Juurakko, Jussi Ryynanen and Kari Halonen, “lntegrated 2.4 GHz Class-E CMOS
Power Amplifier” 2005 lEEE Radio Frequency Integrated Circuits Symposium

AUTHORS
Shridhar R. Sahu
Shridhar R. Sahu was born in Mumbai, India on 14th April 1989. He obtained his B.
E. degree in Electronics and Telecommunication Engineering from Saraswati College
of Engineering, Mumbai University in 2010. He completed his M. T ech degree in
VLSI from G. H. Raisoni College of Engineering, Nagpur in 2013. He is currently
working as Assistant professor in Department of electronics and telecommunication
engineering, Saraswati College of Engineering. His areas of interests are VLSI and
MEMS.
Dr. A. Y. Deshmukh
Dr. A. Y. Deshmukh completed his Ph.D from VNIT Nagpur in 2010. He is currently
working as Professor (Electronics Engg.) & Dean (Quality and Planning Assurance) at
G. H. Raisoni College of Engineering Nagpur, India. He is also working as Coordinator
TEQIP-II (World Bank Assistance Project) and Associate Dean (R&D). He is Technical
Committee Member of IEEE Soft Computing, USA. He is also Counselor of IEEE
Students Branch. He has to his credit around 45 International Conference and Journal Publications. He
has also worked as International Co-Chair for ICETET-08, ICETET09, ICETET-10, ICETET-11,
ICETET-12 (International Conference on Emerging Trends in Engineering & Technology). He has
worked as Reviewer & Session Chair for many conferences. He has also worked as Guest Editor for
International Journal IJSSST. He received research grant from AICTE. He has received Best Teacher
Award in 2004 at GHRCE.

COMPARATIVE PERFORMANCE ANALYSIS OF XORXNOR FUNCTION BASED HIGH-
SPEED CMOS FULL ADDER CIRCUITS FOR LOW VOLTAGE VLSI DESIGN
Subodh Wairya1
, Rajendra Kumar Nagaria2
and Sudarshan Tiwari2
1
Department of Electronics Engineering, Institute of Engineering & Technology (I.E.T), Lucknow, India,
226021
2
Department of ECED, Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India,
211004
ABSTRACT
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our
approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high
performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit
commands a high degree of regularity and symmetric higher density than the conventional CMOS design
style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input
(GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps
in reducing the power consumption and the area of digital circuits while maintaining low complexity of
logic design. This paper analyses, evaluates and compares the performance of various adder circuits.
Several simulations conducted using different voltage supplies, load capacitors and temperature variation
demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power
delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority
of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms
of power, delay and power delay product (PDP). .
KEYWORDS
Hybrid full adder, XOR-XNOR circuit, High Speed, Low Power, Very Large Scale Integrated (VLSI)
Circuits,

REFERENCES
[1] John P. Uyemura, (2002) Introduction to VLSI Circuits and Systems, John Wiley & Sons.
[2] Sung-Mo Kang, Y. Leblebici, (2005) CMOS Digital Integrated Circuits: Analysis and Design, Tata
McGraw Hill, New York,NY,USA.
[3] N. Weste and D. Harris, (2005) CMOS VLSI Design, Pearson Wesley.
[4] N. Zhuang and H. Wu, (1992) “A new design of the CMOS full adder,” IEEE Journal of Solid-State
Circuits, Vol. 27, No. 5, pp. 840–844.
[5] Y.Tsividis, (1996) Mixed Analog- Digital VLSI Devices and Technology, Singapore; McGraw Hill.
[6] K.M. Chu and D. Puffrey, (1987) “A Comparison of CMOS Circuit Techniques Differential Cascode
Voltage Switch Logic versus Conventional Logic,” IEEE Journal of Solid-State Circuit, Vol. SC 22,
No. 4, pp. 528- 532.
[7] A. P. Chandrakasan, S. Sheng and R. W. Bordersen, (1992) “Low-power CMOS digital design,”
IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp. 473- 484.
[8] E. Abu-Sharma and M. Bayoumi, (1995) “A new cell for low power adders,” in Proceeding of
International Midwest Symposium Circuits System, pp. 1014-1017.
[9] I. S. Abu-Khater, A. Bellaouar, and M.I. Elmasry, (1996) “Circuit techniques for CMOS low power
high performance multipliers,” IEEE Journal of Solid- State Circuits, Vol. 31, No. 10, pp. 1535-1546.
[10] Uming Ko, Poras T. Balsara and Wai Lee, (1995) “Low-Power Design Techniques for
HighPerformance CMOS adders,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Vol. 3, No. 2, pp. 327-333.
[11] A. Bellaouar and M. I. Elmasry, (1995) Low-Power Digital VLSI Design: Circuits and Systems,
Kluwer Academic.
[12] A. Parameswar, H. Hara and T. Sakurai, (1994) “A high speed, low power, swing restored
passtransistor logic based multiply and accumulate circuit for multimedia applications,” in Proceedings of
IEEE Custom Integrated Circuits Conference, San Diego, USA, pp. 278–281.
[13] A. Parameswar, H. Hara and T. Sakurai, (1996) “A swing restored pass-transistor logic-based
multiply and accumulate circuit for multimedia applications,” IEEE Journal of Solid-State Circuits, Vol.
31, No. 6, pp. 804–809.
[14] K. Yano, Y. Sasaki, K. Rikino and K. Seki, (1996) “Top-down pass-transistor logic design,” IEEE
Journal of Solid-State Circuits, Vol. 31,No. 6, pp. 792–803.
[15] Reto Zimmermann and Wolfgang Fichtner, (1997) “Low-power Logic Styles: CMOS versus pass
transistor logic,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1079-1090.
[16] Ahmed M. Shams, and Magdy A. Bayoumi, (2000) “A Novel High- Performance CMOS 1-Bit
FullAdder Cell,” IEEE Transaction on Circuits and Systems. II, Vol. 47, No. 5, pp. 478–481.

[17] Abdulkarim Al-Sheraidah, Yingtao Jiang, Yuke Wang and Edwin Sha, (2001) “A Novel Low Power
Multiplexer-Based Full Adder,” European Conference on Circuit Theory and Design, Espoo, Finland,
pp. I329-I332.
[18] D. Radhakrishnan, (2001) “Low-voltage low-power CMOS Full Adder,” IEE Proceedings Circuit:
Devices and Systems, Vol. 148, No. 1, pp. 19-24.
[19] Fartash Vasefi and Z. Abid, (2005) “Low Power N-bit Adders and Multiplier using lowest number of
Transistors 1-bit Adders,” in Proceedings of IEEE Conference CCECE/CCGEI, 05 Saskatoon, pp. 1731-
1734.
[20] Sumeer Goel, Ashok Kumar, Magdy A. Bayouni, (2006) “Design of Robust, Energy-Efficient Full
Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style,” IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, Vol. 14, No. 12, pp. 1309-1321.
[21] Ahmed M. Shams, Tarek K. Darwish, and Magdy A. Bayoumi, (2002) “Performance Analysis of
Low-Power 1-Bit CMOS Full Adder Cells,” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, Vol. 10, No. 1, pp. 20–29.
[22] Mark Vesterbacka, (1999) “14-Transistor CMOS Full Adder with Full Voltage-Swing Nodes,” in
Proceedings of IEEE Workshop Signal Processing Systems, pp. 713-722.
[23] R. Shalem, E. John and L. K. John, (1999) “Novel Low Power Energy Recovery Full Adder Cell,” in
Proceeding of 9th Great Lakes Symposium on VLSI (GLSVLSI’99), pp. 380–383.
[24] Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Shah, and J. Chung, (2004) “A Novel Multiplexer-Based
Low Power Full Adder,” IEEE Transactions on Circuits and Systems, Vol. 51, No. 7, pp. 345-348.
[25] Hung Tien Bui, Yuke Wang and Yingtao Jiang, (2002) “Design and Analysis of Low-Power 10-
Transistor Full Adders Using Novel XOR-XNOR Gates,” IEEE Transactions on Circuits and Systems
II: Analog and Digital Signal Processing, Vol. 49, No. 1, pp. 25-30.
[26] S. Wairya, Himanshu Pandey, R. K. Nagaria and S. Tiwari, (2010) “Ultra Low Voltage High Speed
1- Bit CMOS Adder,” in Proceedings of IEEE International Conference on Power, Control and Embedded
System (ICPCES’10), India, pp. 1-6.
[27] Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang, (2005) “A Review of 0.18µm Full Adder
Performances for Tree Structured Arithmetic Circuits,” IEEE Transaction on Very Large Scale
Integration (VLSI) Systems, Vol. 13, No. 6, pp. 686-694.
[28] Sumeer Goel, Mohammed A. Elgamel, Magdy A. Bayoumi, Yasser Hanafy, (2006) “Design
Methodologies for High-Performance Noise-Tolerant XOR-XNOR Circuits,” IEEE Transactions on
Circuits and Systems- I, Vol. 53, No. 4, pp. 867-878.
[29] Jin-Fa-Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, and Cheng-Che Ho, (2007) “A Novel High-Speed
and Energy Efficient 10-Transistor Full Adder Design,” IEEE Transaction on Circuits and Systems I,
Vol. 54, No. 5, pp. 1050-1059.
[30] S. Veeramachaneni, M. B. Srinivas, (2008) “New Improved 1-Bit Full Adder Cells,” CCECE
/CCGEI, May 5-7, 2008, Niagara Falls, Ontano, Canada, pp. 735-738,.

[31] Arkadiy Morgenshtein, , Alexander Fish and Israel A. Wagner, (2002) “Gate-Diffusion Input (GDI):
A Power Efficient Method for Digital Combinatorial Circuits,” IEEE Transactions on Very Large Scale
Integration (VLSI) Systems, Vol. 10 No. 5, pp. 566 -581
[32] Adarsh Kumar Agrawal, S. Wairya, R. K. Nagaria and S. Tiwari, (2009) “A New Mixed Gate
Diffusion Input Full Adder Topology for High Speed Low Power Digital Circuits,” World Applied
Sciences Journal (WASJ) 7 (Special Issue of Computer & IT): pp. 138-144.
[33] Mohammad Hossein Moaiyeri and Reza Faghih Mirzaee, (2009) “Two New Low-Power and
HighPerformance Full Adders,” Journal of Computers, Vol. 4, No. 2, pp. 119-126.
[34] MA Elgmal, S. Goel and M.A. Bayoumi, (2003) “Noise Tolerant Low Voltage XOR-XNOR for Fast
Arithmetic,” in Proceeding of IEEE Great Lakes Symposium on VLSI (GLSVLSI’ 03), 2003,Wasting
D.C., pp. 285-288.
[35] Shiv Shankar Mishra, S. Wairya, R.K. Nagaria and S. Tiwari, (2009) “New Design Methodologies
for High Speed Low Power XOR-XNOR Circuits,” Journal of World Academy Science, Engineering and
Technology (WASET), Vol. 55, No. 35, pp. 200-206.
[36] S. Wairya, R. K. Nagaria and S. Tiwari, (2010) “A Novel CMOS Full Adder Topology for Low
Voltage VLSI Applications,” in Proceeding of International Conference on Emerging Trends in Signal
Processing & VLSI Design (SPVL’10)’, Hyderabad, India, pp. 1142-1146.
[37] Shubhajit Roy Chowdhury, Aritra Banerjee, Aniruddha Roy and H. Saha, (2008) “A high Speed 8
Transistor Full Adder Design using Novel 3 Transistor XOR Gates,” International Journal of Electronics,
Circuits and Systems, WASET Fall, Vol. 2, No. 4, pp. 217-223.
[38] Mariano Aguirre-Hernandez and Monico Linares-Aranda, (2011) “CMOS Full Adders for
EnergyEfficient Arithmetic Application,” IEEE Transactions on Very Large Scale Integration (VLSI)
System, Vol. 19, No. 4, pp. 718-721.
[39] M. Hosseinghadiry, H. Mohammadi, M. Nadisenejani, (2009) “Two New Low Power High
Performance Full Adders with Minimum Gates,” International Journal of Electronics, Circuits and
Systems, Vol. 3, No. 2, pp. 124-131.
[40] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, (2011) “New Design
Methodologies for High-Speed Low-Voltage 1 Bit CMOS Full Adder Circuits,” Journal of Computer
Technology and Application, Vol. 2, No. 3, pp. 190-198.
[41] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, (2011) “New Design
Methodologies for High Speed Mixed Mode Full Adder Circuits,” International Journal of VLSI and
Communication Systems, Vol. 2, No. 2, pp. 78-98.
[42] Subodh Wairya , Garima Singh, Vishant, R. K. Nagaria and S. Tiwari (2011), “Design Analysis of
XOR (4T) based Low Voltage CMOS Full Adder Cell,” In Proceeding of IEEE International Conference
on Current Trends In Technology (NUiCONE’11), Ahmedabad, India pp. 1-7.
[43] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, (2012) “Performance Analysis of
High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design,” VLSI Design, Vol. 2012,
Article ID 173079, 18 pages.

DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING
OSCILLATOR
Sushil Kumar and Gurjit Kaur
School of Information and Communication Technology Gautam Buddha University, UP, India
ABSTRACT
This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm
technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal
(AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC)
designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose
output oscillates between two voltage levels representing high and low. There are a number of challenges
ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the
technology of choice for many applications, CMOS oscillators with low power, phase noise and timing
jitter are highly desired. In this paper, we have designed a CMOS ring oscillator with nine
stages.Previously, the researchers were unable to reduce the phase noise in ring oscillators substantially
with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz center frequency
of oscillation.
KEYWORDS
Analog and mixed signal (AMS), VLSI circuit, CMOS Ring oscillator (RO), integrated circuit (IC), phase
noise, center frequency of oscillation

REFERENCES
[1] A. Bell and G. Borriello, “A single chip nMOS Ethernet controller,” IEEE International Solid-State
Circuits Conference (ISSCC) Dig. Tech. Papers, 1983, pp. 70–71.
[2] B. Kim, D. Helman, and P. Gray, “A 30 MHz hybrid analog/digital clock recovery circuit in 2 um
CMOS,” IEEE J. Solid State Circuits, vol. 25, no. 6, pp. 1385–1394, June 1990.
[3] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, Upper Saddle River, NJ:
Pearson/Prentice Hall, 2003.
[4] N. Weste and D. Harris, CMOS VLSI Design. Boston, MA: Pearson/Addison-Wesley, 2005.
[5] R. Bayruns, R. Johnston, D. Fraser , and S. C. Fang, “Delay analysis of Si nMOS Gbit/s logic
circuits,” IEEE J. Solid State Circuits, vol. 19, no. 5, pp. 755–764, May 1984.
[6] N. Hedenstierna and K. Jeppson, “CMOS circuit speed and buffer optimization,”IEEE Trans.
Computer Aided Deign. Integrated Circuits Systems, vol.6, no. 2, pp. 270–281, Mar. 1987.
[7] L. Bisdounis, S. Nikolaidis, and O. Loufopavlou, “Propagation delay and short circuit power
dissipation modeling of the CMOS inverter, ”IEEE Trans. Circuits System International, Fundamental
Theory Applications, vol. 45, no. 3, pp. 259–270, Mar. 1998.
[8] A. Kabbani, D. Al-Khalili, and A. Al-Khalili, “Technology portable analytical model for DSM CMOS
inverter transition time estimation, ”IEEE Trans. Computer Aided Design Integrated Circuits Systems,
vol. 22, no. 9,pp. 1177–1187, Sep. 2003.
[9] T.Weigandt, B. Kim, and P. Gray, “Analysis of timing jitter in CMOS ring oscillators,” in Proc. IEEE
Int. Symposium Circuits and Systems (ISCAS), 1994, pp. 27–30.
[10] A. A. Abidi and R. G. Meyer, “Noise in relaxation oscillators,” IEEE J. Solid State Circuits, vol.
SC18, no. 6, pp. 794–802, Dec. 1983.
[11] J. McNeill, “Jitter in ring oscillators,” IEEE J. Solid State Circuits, vol. 32, no. 6, pp. 870–879, Jun.
1997.
[12] A. Hajimiri, S. Limotyrakis, and T. Lee, “Jitter and phase noise in ring oscillators,” IEEE J.
SolidState Circuits, vol. 34, no. 6, pp. 790–804, Jun. 1999. International Journal of VLSI design &
Communication Systems (VLSICS) Vol.3, No.3, June 2012 69
[13] B. Leung, “Anovel model on phase noise of ring oscillator based on last passage time,” IEEE
Trans.Circuits System International, Fundamental Theory Application ,vol. 51, no. 3, pp. 471–482,
Mar.2004.
[14] Guang-Kaai Dehng, Ching-Yuan Yang, June-Ming Hsu, and Shen-Iuan Liu,"A 900 MHz 1 V CMOS
Frequency Synthesizer", IEEE Journal of solid state circuits, Vol. 35, No. 8, pp.1211-1214, 2000.
[15] Andrea Bonfanti, Davide De Caro, Alfio Dario Grasso, Salvatore Pennisi, Carlo Samori, and
Antonio G. M. Strollo, "A 2.5 GHz DDFS PLL with 1.8 MHz Bandwidth in 0.35 µm CMOS" IEEE
Journal of Solid state circuits, Vol. 43, No. 6, pp.1403-1413, 2008.

[16] Asad A. Abidi, Fellow, IEEE,” Phase Noise and Jitter in CMOS Ring Oscillators”, IEEE Journal of
Solid-State Circuits, Vol. 41, No. 8, August 2006.

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