SMART LOAD SHEDDING

SMART LOAD SHEDDING
A PROJECT REPORT
Submitted by
BALAJI.V 113211105014
DINESH KUMAR.S 113211105021
HARIRAM.R 113211105032
VIGNESH.E 113211105322
in partial fulfillment for the award of the degree
of
BACHELOR OF ENGINEERING
IN
ELECTRICAL AND ELECTRONICS ENGINEERING
VELAMMAL ENGINEERING COLLEGE, CHENNAI
ANNA UNIVERSITY: CHENNAI 600 025
APRIL 2015

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ANNA UNIVERSITY: CHENNAI 600 025
BONAFIDE CERTIFICATE
Certified that this project report “ SMART LOAD SHEDDING ” is
the bonafide work of V.BALAJI, S.DINESH KUMAR, R.HARIRAM,
E.VIGNESH”, who carried out the project work under my supervision .
SIGNATURE SIGNATURE
Dr.SHEILAA HARAN Dr.GABRIEL GERMANS
HEAD OF THE DEPARTMENT SUPERVISOR
PROFESSOR
Electrical and Electronics Engineering, Electrical and Electronics Engineering,
Velammal engineering college, Velammal engineering college,
Chennai – 600066. Chennai – 600066.

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CERTIFICATE OF EVALUATION
College Name : 1132 Velammal Engineering College
Branch & Semester : 105 Electrical and Electronics Engineering /VIII
Semester
NAMES OF THE
STUDENTS
TITLE OF THE
PROJECT
NAME OF THE
SUPERVISOR WITH
DESIGNATION
V.BALAJI
SMART LOAD
SHEDDING
S.DINESH KUMAR DR.GABRIEL GERMANS
R.HARIRAM PROFESSOR
E.VIGNESH
The report of the project work submitted by the above students in partial
fulfillment for the award of Bachelor of Engineering degree in
ELECTRICAL AND ELECTRONICS ENGINEERING of Anna
University was evaluated and confirmed to be report of the work done by
the above students and then evaluated.
INTERNAL EXAMINER EXTERNAL EXAMINER

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ACKNOWLEDGEMENT
We express our sincere thanks to Shri.M.V.Muthuramalingam,
Chairman and Mr.M.V.M.Velmurugan, Chief Executive Officer of
Velammal Engineering College for their support during our project work.
We thank Dr.N.Duraipandian, Principal, Velammal Engineering
College for his motivation and support during the course of the project.
We are very much grateful to Dr.Sheilaa Haran, Professor and Head,
Department of Electrical and Electronics Engineering, Velammal Engineering
College for the encouragement and useful suggestions during this work.
We are very much indebted to our Internal Guide, Dr.Gabriel germans,
Professor, Department of Electrical and Electronics Engineering, Velammal
Engineering College for his admirable guidance and constant encouragement
throughout the project work.
We would like to extend our fullest gratitude to our Project
Coordinators, Dr.S.Srinath, Assistant professor-III and Mr.M.Karthikeyan,
Assistant Professor –II for their timely advice and successful grooming.
We take this opportunity to thank our parents, all faculty and staff of our
department for their kind help during the course of work.

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ABSTRACT:
This project presents a new strategy for load shedding with the aim of
providing the consumers with the benefit of using high priority loads of their
choice, even when load shedding is done. A simple low cost bidirectional Power
Line Communication (PLC) system is utilized to control and monitor the loads
of consumer. The adopted design calculates the consumed power continuously
and turns off the low priority appliances in case of lack of power.

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TABLE OF CONTENTS
TITLE PAGE NO
ABSTRACT iv
LIST OF FIGURES vii
LIST OF ABBREVIATIONS viii
1.INTRODUCTION
1.1 GENERAL 1
1.2 OBJECTIVES 2
1.3 SCOPES OF PROJECT 2
1.4 PROJECT PLANNING 2
1.5 SYSTEM DESIGN 2
1.6 HARDWARE MODEL IMPLEMENTATION 3
2.EXISITING SYSTEM
2.1 LOAD SHEDDING 4
2.2 LOAD RESTORATION 4
2.3 UNDERFREQUENCY RELAYS FOR LOAD
SHEDDING 6
2.4 STATIC RELAY 6
2.5 ELECTROMECHANICAL RELAY 7

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TITLE PAGE NO
3.LITERATURE SURVEY
3.1 SOURCE DATA FORMAT 8
3.2 MODULATION TECHNIQUES 8
3.3 POWER LINE COMMUNICATION 10
4.THE PROPOSED SYSTEM 13
4.1 HARDWARE MODEL 17
4.2 COMPONENTS DESCRIPTION 17
4.3 ATMEGA 8 17
4.4 MOTOR DRIVER (L293D) 23
4.5 AVR DEVELOPMENT BOARD CIRCUIT DIAGRAM 27
4.6 DESCRIPTION OF HARDWARE MODEL 28
4.7 WORKING OF HARDWARE MODEL 28
4.8 CIRCUIT DIAGRAM OF HARDWARE MODEL 36
4.9 ADVANTAGES 37
5.FUTURE SCOPE AND CONCLUSION
5.1 FUTURE SCOPE OF PROJECT 38
5.2 CONCLUSION 38
6.REFERENCES 39

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LIST OF FIGURES
FIGURE NO CONTENT PAGE NO
3.1 POWER LINE COMMUNICATING 12
CIRCUIT
4.1 BLOCK DIAGRAM OF THE 16
PROPOSED SYSTEM
4.2 PIN DIAGRAM 21
4.3 PIN DIAGRAM OF L293D 25
4.4 BLOCK DIAGRAM OF L293D 25
4.5 AVR DEVELOPMENT BOARD 27
CIRCUIT DIAGRAM
4.6 WORKING STATE 1 32
4.10 CIRCUIT DIAGRAM OF HARDWARE
MODEL 36

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LIST OF ABBREVIATIONS:
ADC: ANALOG TO DIGITAL CONVERTER
HD: HIGH DEFINITION
PLC: PROGRAMMABLE LOGIC CONTROLLER
CISC: COMPLEX INSTRUCTION SET COMPUTING
EEPROM: ELECTRICALLY ERASABLE PROGRAMMABLE
READ-ONLY MEMORY
SRAM: STATIC RANDOM-ACCESS MEMORY
USART: UNIVERSAL SYNCHRONOUS/ASYNCHRONOUS
RECEIVER/TRANSMITTER
TQFP: THIN QUAD FLAT PACK
SPI: SERIAL PERIPHERAL INTERFACE
CPU: CENTRAL PROCESSING UNIT
TTL: TRANSISTOR–TRANSISTOR LOGIC

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CHAPTER 1
1. INTRODUCTION
1.1 GENERAL
Electric power generation may not always meet peak demand requirement.
In these situations, overall demand must be lowered, either by turning off service
to some devices or cutting back the supply voltage (brownouts), in order to
prevent uncontrolled service disruptions such as power outages (widespread
blackouts) or equipment damage. Distribution control centers may impose load
shedding on service areas via rolling blackouts or by agreements with specific
high-use industrial consumers to turn off equipment at times of system-wide peak
demand.
The major disadvantage of load shedding is that the consumers are totally
restricted from using electric power. Even in case of an emergency they won’t be
able to use electric power. This project mainly aims to address this problem by
dividing the loads of the consumer into different priority groups and when it is
required to do load shedding then the lowest priority loads of the consumer will
only get disconnected from the power supply. Thus providing consumers with the
benefit of using electric power for their most needed high priority loads, even
when load shedding is done.
In this project when it is required to do load shedding, Power Line
Communication is used for switching the loads of consumer. Power Line
Communication has proven to be a reliable communications technology for high
bandwidth distribution of entertainment-grade HD video, gaming, internet access
and other applications in homes. This same proven technology will allow the

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distribution control centers to monitor and manage their customer’s electricity
usage as never before.
1.2 OBJECTIVES
The objective of this project is to design and develop a low cost power line
communication module to control the loads of consumer, by using the existing
power lines.
1.3 SCOPES OF PROJECT
The scope of this project consists of three main structures; which includes
project planning, system design and hardware model implementation.
1.4 PROJECT PLANNING
Project planning consists of analytical studies and academic research on the
existing Technologies of the power line communication system. Conceptual
design and also sourcing for the main components will also be included in this
state.
1.5 SYSTEM DESIGN
System design consists of hardware and software design. In hardware design,
design and building of associated circuitry, like interfacing relays, switches with
microcontroller and power supply. Whereas, the software design, is to develop
and program the microcontroller as per the project requirement.

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1.6 HARDWARE MODEL IMPLEMENTATION
This will be the last section of the entire project. Full integrated hardware
model showing the actual operating process of smart load shedding will be
presented.

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CHAPTER 2
2. EXISITING SYSTEM
2.1 LOAD SHEDDING
To prevent the complete collapse of the system, under frequency relays are
used to automatically drop load in accordance with a predetermined schedule to
balance the load to the available generation in the affected area. Such action must
be taken promptly and must be of sufficient magnitude to conserve essential load
and enable the remainder of the system to recover from the under frequency
condition. Also, by preventing a major shutdown, restoration of the entire system
to normal operation is greatly facilitated and expedited.
Where individual operating utility companies are inter-connected, resulting
in a power pool, it is essential that system planning and operating procedures be
coordinated to provide a uniform automatic load shedding scheme. The numbers
of steps, the frequency levels and the amount of load to be shed at each step are
established by agreement between the power pool members.
2.2 LOAD RESTORATION
If a load shedding program has been successfully implemented, the system
frequency will stabilize and then recover to 50 Hz. This recovery is assisted by
governor action on available spinning reserve generation, or by the addition of
other generation to the system. The recovery of system frequency to normal is
likely to be quite slow and may extend over a period of several minutes. When 50
Hz operation has been restored to an island, then interconnecting tie lines with
other systems or portions of systems can be synchronized and closed in.

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As the system frequency approaches the normal 50 Hz, a frequency relay can
be used to automatically begin the restoration of the load that has been shed. The
amount of load that can be restored is determined by the ability of the system to
serve it. The criterion is that the available generation must always exceed the
amount of load being restored so that the system frequency will continue to
recover towards 50 Hz. Any serious decrease in system frequency at this point
could lead to undesirable load shedding repetition, which could start a system
oscillation between shedding and restoration. This would be a highly undesirable
condition. The availability of generation, either locally or through system
interconnections, determines whether or not the shed load can be successfully
restored. Therefore, a load restoration program usually incorporates time delay,
which is related to the amount of time required to add generation or to close tie-
lines during emergency conditions. Also, both the time delay and the restoration
frequency set points should be staggered so that the entire load is not reconnected
at the same time. Reconnecting loads on a distributed basis also minimizes power
swings across the system and thereby minimizes the possibility of initiating a new
disturbance.
In general, wide frequency fluctuations and the possibility of starting a load
shedding/restoration oscillation can be greatly minimized if the amount of load
restored per step is small and the spinning reserve generation available is
adequate. There should also be adequate time delay provided between load
restoration steps to allow the system to stabilize before an additional block of load
is picked up.

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2.3 UNDERFREQUENCY RELAYS FOR LOAD SHEDDING
There are two basic types of under frequency relays available for application
in load shedding schemes. They are the static relay, and electromechanical relay.
The operating characteristics and features of each of these relays are described in
the following paragraphs.
2.4 STATIC RELAY
The static under frequency relay employs digital counting techniques to
measure system frequency. Basically, this relay consists of a highly stable,
crystal-controlled oscillator which continuously supplies two mHz pulses to a
binary counter. The counter, in conjunction with other logic circuitry, determines
system frequency by counting the number of two mHz pulses which occur during
a full cycle (one period) of power system voltage. For any preset frequency, a
specific number of pulses should occur during a one-cycle period. If the number
of pulses is less than this specific number, it would indicate that system frequency
is above the setting. Conversely, if the number of pulses is greater than this
specific number, it indicates that the system frequency is less than the setting. For
security reasons, an under frequency indication must occur for a minimum of
three consecutive cycles before the relay produces an output. This minimum time
can be extended to 80 cycles by means of an adjustable auxiliary timer. If the
system frequency should recover even for one cycle during the timing period, the
timing circuits will be reset and the relay will immediately start monitoring
system frequency again. The relay operating time is independent of the rate of
change of the system frequency.

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2.5 ELECTROMECHANICAL RELAY
The Type CFF under-frequency relay is a high-speed, induction cup type. Its
basic principle of operation is the use of two separate coil circuits which provide
increasing phase displacement of fluxes as the frequency decreases, thereby
causing torque to be developed in the cup unit to close the tripping contacts. The
quantity of torque produced is proportional to the sine of the angle between these
two fluxes. As the frequency decays the angular displacement increases, thereby
increasing the torque produced. If the frequency decays rapidly the torque will
increase rapidly and cause the relay to close its contacts in less time. Thus the
relay operating time is a function of the rate-of-change of frequency. The CFF
relay setting is continuously adjustable over a range of 56 to 59.5 Hz.

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CHAPTER 3
3. LITERATURE SURVEY
To design a power line modem, a good background of digital communication
techniques and existing standards for power line communication is required. A
literature review has been carried out as per this requirement and summarized as
follows:
3.1 SOURCE DATA FORMAT
For a simple control scheme to switch a contactor from host controller, it
will be sending either ON or OFF command. A low to high digital pulse will be
modulated over the power line in this case and the receiving side will simply
demodulate this pulse back from the carrier and the trigger circuit will then
activate ON or OFF operation. This is not a practical approach as a noise signal
may be wrongly interpreted as ON or OFF signal by the modem circuit. To
prevent false triggering, addresses are given for the PLC modems.
In this project we will have same address for all the PLC modems, since
every consumer connected to a centre is expected to receive and interpret the data
sent from the distribution centre in the same manner.
3.2 MODULATION TECHNIQUES
There are three main digital modulation schemes as follows:
 Amplitude Shift Keying (ASK)
 Frequency Shift Keying (FSK)
 Phase Shift Keying (PSK)

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For higher data transmission rates, narrower bandwidths, Lower error rates at
lower Signal to Noise ratios, and lower power consumption of modem devices,
the following advanced digital modulation schemes as considered:
1. M-ary Modulation
a. M-ASK
b. M-PSK
c. M-ASK
2. Quadrature Modulation (M-QAM)
3. Spread Spectrum Techniques
a. Frequency Hopping Spread Spectrum (FHSS)
b. Direct Sequence Spread Spectrum (DSSS)
4. Multiplexing Techniques
a. Code Division Multiple Access (CDMA)
b. Orthogonal Frequency Division Multiplexing (OFDM)
Communicating with the power line communication layer demands robust
modulation techniques like Frequency Shift Keying (FSK), Code-Division
Multiple Access (CDMA) and Orthogonal Frequency Division Multiplexing
(OFDM). For low cost, low data rate applications, such as power line protection
and telemetering, FSK is seen as a good solution. For data rates up to 1Mbps, the

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CDMA technique may provide an effective solution. However, for high data
applications beyond that, OFDM is the technology of choice for PLC.
3.3 POWER LINE COMMUNICATION
The PLC is the generic name for a network technology that transmits data
over electrical wiring. It is the result of extensive research on high bandwidth data
transmission on the power line medium. In the transmitting mode the application
resides on a master (Host) microcontroller which generates messages to be
transmitted on the power line. These messages are sent over an RS232 serial link
and modulated by the FSK Modem and coupled with power line by the coupling
circuit. In the receiving mode the signals are received by the coupling circuit and
demodulated by the FSK Modem then transferred to the host microcontroller in an
RS232 format. ―fig-1 shows the block diagram for the transceiver and coupler
circuit.
A. Transmitter Section:
The microcontroller serializes the data and sends them through Tx line to the
modulator. The modulator divides the local oscillator frequency by a definite
factor depending on whether the input data is high level logic=1 ‘or’ low level
logic=0. It then generates a sine wave at 133.3 kHz (logic=0) ‘or’ 131.8 kHz
(logic=1), which is fed to the Programmable Gain Amplifier to generate FSK
modulated signals.

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B. Receiver Section
The incoming FSK signal from the power line is inputted to a High
Frequency (HF) Band Pass Filter that filters out-of band frequency components
and outputs filtered signal within the desired spectrum of 125 kHz to 140 kHz for
further demodulation. The Mixer block multiplies the filtered FSK signals with a
locally generated signal to produce heterodyned frequencies. The mentioned
frequencies are set as default but they can be changed according to the used
channel frequency response. Band Pass filters further removes out-of-band noise
as required for further demodulation. This signal is fed to the correlator which
produces a DC component (consisting of logic ’1’ and ‘0’) and a higher frequency
component. The output of the correlator is fed to a Low Pass Filter (LPF) that
outputs only the demodulated digital data at 9600 baud and suppresses all other
higher frequency components generated in the correlation process.
The output of the LPF is digitized by the hysteresis comparator. This
eliminates the effects of correlator delay and false logic triggers due to noise. The
receiver also implements Automatic Gain Control (AGC). This functionality
enables the receiver to adjust its gain automatically depending on the signal
strength of the input FSK signal.

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Fig 3.1 power line communicating circuit

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CHAPTER 4
4. THE PROPOSED SYSTEM
The proposed system consists of a Microcontroller which can be installed in
the consumer premises and another microcontroller and a PLC transmitter module
installed in the distribution control centre. There will be PLC receiver module
and three contactors for controlling the different priority groups in the consumer
premises.
The Microcontroller in the distribution control centre will continuously
monitor the power supply and load demand values. In case if the power supply is
less than the certain predefined level of demand; then this microcontroller will
send a signal through Tx line to the modulator. The modulator divides the local
oscillator frequency by a definite factor depending on whether the input data is
high level logic=1 ‘or’ low level logic=0. It then generates a sine wave at 131.8
kHz (logic=1), which is fed to the Programmable Gain Amplifier to generate FSK
modulated signals. This signal is transmitted through the power line to the
consumer premises.
At the consumer premises this incoming FSK signal from the power line is
inputted to a High Frequency (HF) Band Pass Filter that filters out-of band
frequency components and outputs filtered signal within the desired spectrum of
125 kHz to 140 kHz for further demodulation. The Mixer block multiplies the
filtered FSK signals with a locally generated signal to produce heterodyned
frequencies. The mentioned frequencies are set as default but they can be changed
according to the used channel frequency response. Band Pass filters further
removes out-of-band noise as required for further demodulation. This signal is fed
to the correlator which produces a DC component (consisting of logic ’1’ and ‘0’)

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and a higher frequency component. The output of the correlator is fed to a Low
Pass Filter (LPF) that outputs only the demodulated digital data at 9600 baud and
suppresses all other higher frequency components generated in the correlation
process.
The output of the LPF is digitized by the hysteresis comparator. This
digitized signal is fed to the Microcontroller at the consumer premises, on
receiving logic high (‘1’); the microcontroller will output signals to turn-off the
lowest priority load group. On receiving this signal the contactor of the lowest
priority group operates and causes its contacts to switch from NC to open state,
thus disconnecting the entire group of loads from the power supply.
After disconnecting the low priority load group from supply, the
microcontroller at the distribution control centre will again check whether the
balance between supply and demand are within the prescribed limits. If they are
within limits then no new switching operations are made for a certain period of
time, after this time period the controller will check for the balance between
supply and demand. If the supply is more than demand to a certain extent, then
the microcontroller at the distribution control centre will transmit a signal to turn-
on the low priority load group. But if the supply is less than the demand, then the
microcontroller at the distribution control centre will again transmit a signal to
turn-off the next available lowest priority load group.
After disconnecting the second lowest priority load group from supply, the
microcontroller at the distribution control centre will again check whether the
balance between supply and demand are within the prescribed limits. If they are
within limits then no new switching operations are made for a certain period of
time, after this time period the controller will again check for the balance between

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supply and demand. If the supply is more than demand to a certain extent, then
the microcontroller at the distribution control centre will transmit a signal to turn-
on the second lowest priority load group. But if the supply is less than the
demand, then the microcontroller at the distribution control centre will transmit a
signal to turn-off the highest priority load group. Thus the entire distribution area
gets completely disconnected from the supply to avoid total shutdown of the
system.
ATmega32 has good features of making the system developable and easy to
interface with the Wi-Fi, Wi-Max or GPRS so as to be kept informed with all
what is happening in the house. In addition the system can calculate the total
power consumed in the house for prepaid purposes.

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fig 4.1 block diagram of the proposed system

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4.1 HARDWARE MODEL
4.2 COMPONENTS DESCRIPTION
4.3 ATMEGA 8
DESCRIPTION:
The Atmel®AVR® core combines a rich instruction set with 32 general
purpose working registers. All the 32 registers are directly connected to the
Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed
in one single instruction executed in one clock cycle. The resulting architecture is
more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.
The ATmega8 provides the following features: 8 Kbytes of In-System
Programmable Flash with Read-While-Write capabilities, 512 bytes of EEPROM,
1 Kbyte of SRAM, 23 general purpose I/O lines, 32 general purpose working
registers, three flexible Timer/Counters with compare modes, internal and
external interrupts, a serial programmable USART, a byte oriented Two wire
Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF
packages) with 10-bit accuracy, a programmable Watchdog Timer with Internal
Oscillator, an SPI serial port, and five software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI
port, and interrupt system to continue functioning. The Powerdown mode saves
the register contents but freezes the Oscillator, disabling all other chip functions
until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous
timer continues to run, allowing the user to maintain a timer base while the rest of
the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except asynchronous timer and ADC, to minimize switching noise

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during ADC conversions. In Standby mode, the crystal/resonator Oscillator is
running while the rest of the device is sleeping. This allows very fast start-up
combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory
technology. The Flash Program memory can be reprogrammed In-System through
an SPI serial interface, by a conventional non-volatile memory programmer, or
by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application
program in the Application Flash memory. Software in the Boot Flash Section
will continue to run while the Application Flash Section is updated, providing true
Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega8 is a powerful
microcontroller that provides a highly-flexible and cost-effective solution to many
embedded control applications.
The ATmega8 is supported with a full suite of program and system
development tools, including C compilers, macro assemblers, program simulators,
and evaluation kits.
FEATURES:
• High-performance, Low-power Atmel®AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier

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• High Endurance Non-volatile Memory segments
– 8Kbytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1Kbyte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
 Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
 Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
 Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator

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• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,
and standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
– 2.7V - 5.5V (ATmega8L)
– 4.5V - 5.5V (ATmega8)
• Speed Grades
– 0 - 8MHz (ATmega8L)
– 0 - 16MHz (ATmega8)
• Power Consumption at 4Mhz, 3V, 25 C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5μA

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Pin diagram:
Fig 4.2 Pin diagram

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Pin Descriptions
VCC: Digital supply voltage.
GND: Ground.
Port B (PC7...PB0):
It is an 8-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). The Port B output buffers have symmetrical drive characteristics
with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The
Port B pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port C (PC5...PC0):
Port C is a 7-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port C output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are
activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D (PD7...PD0):
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port D output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are

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activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
RESET (Reset input):
A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. The Shorter pulses are not
guaranteed to generate a reset.
AVCC:
AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and
ADC (7..6). It should be externally connected to VCC, even if the ADC is not
used. If the ADC is used, it should be connected to VCC through a low-pass filter.
AREF:
AREF is the analog reference pin for the A/D Converter. These pins are
powered from the analog supply and serve as 10-bit ADC channels.
Basic Function:
The main function of the CPU core is to ensure correct program execution.
The CPU must therefore be able to access memories, perform calculations,
control peripherals, and handle interrupts.
4.4 MOTOR DRIVER (L293D)
DESCRIPTION:
The L293 and L293D are quadruple high-current half-H drivers. The L293 is
designed to provide bidirectional drive currents of up to 1 A at voltages from 4.5
V to 36 V. The L293D is designed to provide bidirectional drive currents of up to

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600-mA at voltages from 4.5 V to 36 V. Both devices are designed to drive
inductive loads such as relays, solenoids, dc and bipolar stepping motors, as well
as other high-current/high-voltage loads in positive-supply applications.
All inputs are TTL compatible. Each output is a complete totem-pole drive
circuit, with a Darlington transistor sink and a pseudo- Darlington source. Drivers
are enabled in pairs, with drivers 1 and 2 enabled by 1,2EN and drivers 3 and 4
enabled by 3,4EN.
When an enable input is high the associated drivers are enabled, and their
outputs are active and in phase with their inputs. When the enable input is low,
those drivers are disabled, and their outputs are off and in the high-impedance
state. With the proper data inputs, each pair of drivers forms a full-H (or bridge)
reversible drive suitable for solenoid or motor applications.
FEATURES:
_ Wide Supply-Voltage Range: 4.5 V to 36 V
_ Separate Input-Logic Supply
_ Internal ESD Protection
_ Thermal Shutdown
_ High-Noise-Immunity Inputs
_ Functionally Similar to SGS L293 and SGS L293D
_ Output Current 1 A Per Channel (600 mA for L293D)
_ Peak Output Current 2 A Per Channel (1.2 A for L293D)
_ Output Clamp Diodes for Inductive Transient Suppression (L293D)

25
PIN DIAGRAM:
Fig 4.3 pin diagram of L293D
BLOCK DIAGRAM:
FIG 4.4 block diagram of L293D

26
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR
TEMPERATURE RANGE:
Supply voltage, VCC1 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . … . 36 V
Output supply voltage, VCC2 . . .. . . . . . . . . 36 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . 7
V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . .. −3 V to VCC2 + 3 V
Peak output current, IO (nonrepetitive, t ≤ 5 ms): L293 . . .. . . . . . . . . . . ±2 A
Peak output current, IO (nonrepetitive, t ≤ 100 μs): L293D . . . . . . .. . . . …… . . . .
±1.2 A
Continuous output current, IO: L293 . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . .
. ±1 A
Continuous output current, IO: L293D . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . .
±600 mA
Package thermal impedance, θJA (see Notes 2 and 3): DWP package . . . . .. . . . . .
. . TBD°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NE package . . . . . . . . . . . . . . . . . . . . . . . . . TBD°C/W
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . .
150°C
Storage temperature range, Tstg . . ….... . . . −65°C to 150°C

27
4.5 AVR DEVELOPMENT BOARD CIRCUIT DIAGRAM
FIG 4.5 AVR development board circuit diagram

28
4.6 DESCRIPTION OF HARDWARE MODEL
The model has a board for power supply, a board for relays and the AVR
development board. In the Atmega8 microcontroller there are five ADC pins in
port c, ADC in atmega8 device uses a technique known as successive
approximation by comparing input voltage with half of reference voltage
generated internally. The comparison continues by dividing the voltage further
down and updating each bit in ADC register by 1 if input voltage is high, 0
otherwise. This process lasts 10 (10 bit ADC) times and generates resulting binary
output.
Of the five ADC pins, pc4/ADC4 (pin 27) is used in this project. This pin is
connected with the variable terminal of the potentiometer as shown in the circuit
diagram. Such that when potentiometer’s resistance is varied then the voltage in
pin 27 also varies accordingly. For 10 bit ADC, there can be 1024 different
voltages.
The motor driver IC (L293D) is connected with port b terminals and with
three relay coils as shown in circuit diagram. It is used as a driver for turning on
the relays when respective input signals from port b is given to it. The common
terminal of relays is connected with the phase of 230V AC power supply.
4.7 WORKING OF HARDWARE MODEL
The atmega8 microcontroller is programmed to work in such a manner that,
when the resistance of potentiometer is varied from 0 to maximum; then the port b
will output data to turn-on the relays one by one through the motor driver IC.

29
PROGRAM:
#include <avr/io.h>
#define PORT_ON(port,pin) port |= (1<<pin)
#define PORT_OFF(port,pin) port &= ~(1<<pin)
int main(void)
{
unsigned int adc_value; // Variable to hold ADC result
DDRB=0xff; // Set Port b for output to connect with relay driver IC
PORTB = 0x00; // Clear Portb pins
ADCSRA = (1<<ADEN) | (1<<ADPS2) | (1<<ADPS0); // Set ADCSRA
Register with division factor 32
ADMUX=0x04; //Binary equivalent of 0101
while (1) //Forever since it is in single conversion mode
{
ADCSRA |= (1<<ADSC); // Start conversion
while (ADCSRA & (1<<ADSC)); // wait until conversion completes;
ADSC=0 means Complete
adc_value = ADCW; //Store ADC result
if (adc_value < 256) // checking the output of ADC to switch off the
lowest priority load groups

30
{
PORT_OFF (PORTB,0); // Clear 0th bit
PORT_OFF (PORTB,1); // Clear 1st bit
PORT_OFF (PORTB,2); // clear 2th bit
}
else if (adc_value <= 512 && adc_value > 256 ) // checking the output of
ADC to switch off the lowest priority load groups
{
PORT_ON(PORTB,0); // Set 0th bit to turn ON realy 1 which inturn
disconnects the lowest priority loads from the power supply
PORT_OFF (PORTB,2); // clear 2th bit
PORT_OFF (PORTB,1); // Clear 7th bit
}
else if (adc_value <= 720 && adc_value > 512 )
{
PORT_ON (PORTB,1); // Set 1st bit to turn ON realy 2 which inturn
disconnects the second lowest priority loads from the power supply
PORT_OFF (PORTB,2);

31
}
else if (adc_value <= 1024 && adc_value > 720 )
{
PORT_ON (PORTB,1); // Set 1st bit to turn ON realy 2 which inturn
disconnects the second lowest priority loads from the power supply
PORT_ON (PORTB,2); // Set 2nd bit to turn ON realy 3 which inturn
disconnects the highest priority loads from the power supply
}
}
}

32
PROGRAM DESCRIPTION AND WORKING:
When the output of ADC due to varying the resistance of potentiometer is
less than 256 in decimal value, then all three relays won’t be supplied with any
power to turn them ON, thus all 3 bulbs will be glowing.
Fig 4.6 working state 1

33
Similarly when the output of ADC due to varying the resistance of
potentiometer is greater than 256 but less than 512, then portb-0 pin will output a
high signal(1). This high signal from portb-0 will enable the 1Y pin of L293D to
supply the coil of relay-1 with sufficient power to turn it ON.
When coil of relay-1 is supplied with sufficient electric power, then it will
switch its contacts from NC to NO. This makes the bulb-1 connected with the
relay-1 to get disconnected from supply, thus it turns OFF. This bulb is assumed
to be the lowest priority load of the consumer. But the other 2 bulbs will be
glowing.

34
potentiometer is greater than 512 but less than 720, then portb-0 and portb-1
pins will output a high signal(1). This high signal from portb-0 and portb-1 will
enable the 1Y and 2Y pins of L293D to supply the coils of relay-1 and relay-2
with sufficient power to turn it ON.
When coil of relay-1 and relay-2 are supplied with sufficient electric power,
then it will switch its contacts from NC to NO. This makes the bulb-1 and bulb-2
connected with the relay-1 and relay-2 respectively to get disconnected from
supply, thus they both turns OFF. But the other one bulb, which is assumed to be
the highest priority load of the consumer will be glowing.

35
potentiometer is greater than 720 but less than 1024, then portb-0 , portb-1 and
portb-2 pins will output a high signal(1). This high signal from portb-0 , portb-1
and portb-2 will enable the 1Y, 2Y and 3Y pins of L293D to supply the coils of
relay-1, relay-2 and relay-3 with sufficient power to turn it ON.
When coil of relay-1, relay-2 and relay-3 are supplied with sufficient electric
power, then it will switch its contacts from NC to NO. This makes the bulb-1,
bulb-2 and bulb-3 connected with the relay-1, relay-2 and relay-3 respectively to
get disconnected from supply, thus they all turns OFF.

36
4.8 CIRCUIT DIAGRAM OF HARDWARE MODEL:
FIG 4.10 circuit diagram of hardware model

37
4.9 ADVANTAGES
 Implementation of this project will provide the consumers with the benefit
of using electric power for their most needed high priority loads; even
when load shedding is done.
 Reduction of downtime for critical loads.
 User-defined load priority and groups.
 Reduction of spinning reserve requirements.

38
CHAPTER 5
5.FUTURE SCOPE AND CONCLUSION
5.1 FUTURE SCOPE OF PROJECT
Instead of starting from the lowest priority load group, when it is required to
do load shedding then the load group except the highest priority group, which is
currently loaded very close to the level of supply-demand difference can be
turned-OFF first. This will reduce the time required to overcome the disturbance
in the system due to overloading and also the system will remain overloaded only
for a shot time interval.
5.2 CONCLUSION
The proposed design offers the consumers with the benefit of using electric
power for their most needed high priority loads; even when load shedding is done.
A simple low cost bidirectional PLC system has been utilized to control and
monitor the loads of all consumers.

39
CHAPTER 6
6. REFERENCES
1. N. Shah, A. Abed, C. Thomas, J. Seabrook, L. Pereira, M. Kreipe, S.
Mavis, T. Green, Final report of UVLS taskforce: under voltage load
shedding guidelines", Western Systems Coordinating Council, 1999.
2. Y. Min, S.B. Hong, Y.D.Han, Y.K. Gao, Y. Wang, Analysis of power-
frequency dynamics and designation of under frequency load shedding
scheme in large scale multi-machine power systems", IEE International
Conference on Advance Power System Control, Operation and
Management, Vol. 2, pp. 871{876, 1991.
3. Design of Power-Line Communication System (PLC) Using a PIC
Microcontroller Q. Al-Zobi1, I. Al Tawil2, K. Gharaibeh3 and I. S. Al-
KofahiJ. of Active and Passive Electronic Devices, Vol. 3, pp. 331–340
4. Power Line Communications: An Overview - Part I,II Muhammad Salman
Yousuf*, Mustafa El Shafei**
5. http://america2.renesas.com/applications/wired_connectivity/powerline_co
mm.html
6. Olaf Hooijien, ‘ Aspects of Residential Power Line Communication” , Ph
D. Thesis, Shaker Verlag GmbH, ISBN 3-8265-3429-8,1998
7. Y. Lai, J. Rodrigues, Y. Huang, H. Wang, and C. Lai,"An
intercommunication home energy management system with appliance
recognition in home network", Mobile Netw Appl, Springer (2012)
17:132–142.
8. Power Lin Communications Theory and Applications for Narrowband and
Boardband Communications over Power Lines Editors, Hendrik C.
Ferreira, Lutz Lampe, John Newbury, Theo G. Swart

40
9. Clien Y Bai, H Chen and C Hung, “ Home Application energy monitoring
and controlling based on PLC”, IEEE, ICCE, 2009
10. S. T. Wang, R. M. Yuan, Z. J. Sun. “The Technology of Low Voltage
Power Line Carrier and Its Implementation in Automated Meter Reading
System”, Electrical Measuring and Instrumentation, 3, pp. 31-34, (2008).
11.H. L. Zhang, M. J. Jia, Z. C. Yue, H. Zhang. “The Development and Using
of Power Line Carrier Technology at Home and Abroad”, Power System
Technology, pp.646-652, (2006).
12.http://en.wikipedia.org/wiki/Power-line_communication
13.http://www.researchgate.net/post/What_are_the_advantages_and_disadvant
ages_of_power_line_carrier_communication
14.http://loadshedding.eskom.co.za/LoadShedding/Description
15.“A New Frequency Relay for Power System Applications” by H.J.Carlin
and J.L. Blackburn, AIEE Transactions, Vol. 63, 1944,p.553.
16.“The Effect of Frequency Reduction on Plant Capacity and on System
Operation” by H.A.Bauman, G.R. Hahn and C.N. Metcalf (54-370).
17.“The Effect of Frequency and Voltage” by R.Holgate (54-390).

SMART LOAD SHEDDING

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