Three dimensional silicon integration
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The document discusses three-dimensional silicon integration, highlighting its definition, history, and the benefits and challenges associated with the technology. It emphasizes the importance of through-silicon vias (TSVs) in connecting stacked silicon wafers and details the wafer thinning process. Key references are provided for further reading.
Three dimensional silicon integration
- 1. Three Dimensional Silicon Integration Presented To: • Prof. Mohamed Aboudina Presented By: • Mohamed Ashraf Atwa • Mohamed Badr
- 2. Content • Intoduction • History • Benefits and challenges • TSVs • Wafer Thinning • References
- 3. Definition • Integrated Circuit manufactured by stacking silicon wafers and/or dies and interconnecting them vertically using Through-Silicon Vias (TSVs).
- 5. Why ?! • Footprint • Cost • Heterogeneous Integration • Shorter Interconnects • Power Efficiency • Design • Bandwidth • Noise
- 6. TSV (Through Silicon Vias) • Critical Component • Joins two separate wafers • Cylindrical structure composed of copper, aluminum, tungsten or polysilicon. • Introduced early 1950s by William Shockley then an exponential growth by 1990s • Industrial leaders • 5 Major to form TSVs
- 8. • Mechanical grinding with mesh size #325 then #2000 • About 20% of the TSV fabrication cost • The BOX acts an etch stop while thinning • Improves the alignment of layers. Wafer Thinning