Assic 17th Lecture
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This document discusses several Verilog HDL system tasks: - $readmemb and $readmemh initialize memories from binary or hexadecimal data files by reading numbers from a specified file into a specified memory name. - $strobe displays values after all other assignments in the same time unit, ensuring synchronization. - $random generates random numbers that can be used for random testing and performance analysis. The task optionally takes a seed value to reproduce random sequences.
Assic 17th Lecture
- 1. 1 Verilog HDLVerilog HDL ASIC DESIGN USING FPGA BEIT VII KICSIT Oct 8 2012 Lecture 17
- 2. 2 Initializing Memory from File Oct 8 2012 • Verilog provides a very useful system task to initialize memories from a data file. • Two tasks are provided to read numbers in binary or hexadecimal format. • Keywords $readmemb and $readmemh are used to initialize memories. Lecture 17
- 3. 3 Initializing Memory from File Oct 8 2012 • Usage: $readmemb("<file_name>", <memory_name>); $readmemb("<file_name>", <memory_name>, <start_addr>); $readmemb("<file_name>", <memory_name>, <start_addr>,<finish_addr>); • Identical syntax for $readmemh. Lecture 17
- 4. 4 Initializing Memory from File Oct 8 2012 • The <file_name> and <memory_name> are mandatory; <start_addr> and <finish_addr> are optional. • Defaults are start index of memory array for <start_addr> and end of the data file or memory for <finish_addr>. Lecture 17
- 5. 5 Initializing Memory from File Oct 8 2012 • Example Lecture 17
- 6. 6 Strobing Oct 8 2012 • Strobing is done with the system task keyword $strobe. • This task is very similar to the $display task except for a slight difference. • If many other statements are executed in the same time unit as the $display task, the order of execution is nondeterministic. Lecture 17
- 7. 7 Strobing Oct 8 2012 • If $strobe is used, it is always executed after all other assignment statements in the same time unit have executed. • Thus, $strobe provides a synchronization mechanism to ensure that data is displayed only after all other assignment statements, which change the data in that time step, have executed. Lecture 17
- 8. 8 Strobing Oct 8 2012 • Example Lecture 17
- 9. 9 Strobing Oct 8 2012 • In this example the values at positive edge of clock will be displayed only after statements a = b and c = d execute. • If $display was used, $display might execute before statements a = b and c = d, thus displaying different values. Lecture 17
- 10. 10 Random Number Generation Oct 8 2012 • Random number generation is required for a random set of test vectors. • Random testing is important because it often catches hidden bugs in the design. • Random vector generation is also used in performance analysis of chip architectures. • The system task $random is used for generating a random number. Lecture 17
- 11. 11 Random Number Generation Oct 8 2012 • Usage: $random; $random(<seed>); • The value of <seed> is optional and is used to ensure the same random number sequence each time the test is run. Lecture 17
- 12. 12 Random Number Generation Oct 8 2012 • Example Lecture 17