Verilog lect 7
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1. The document discusses different types of operators in Verilog HDL including logical, bitwise, reduction, shift, concatenation, relational, equality, conditional, and arithmetic operators. 2. It provides examples of using each type of operator and how they are used to perform operations on operands of different sizes and types. 3. Replication operators and concatenation operators are described as ways to combine operands of different sizes into a single output. An example of using replication to implement a 5x5 bit multiplier is also shown.
![7
Concatenation Operator
• {op1, op2, ..} → concatenates op1, op2, .. to single
number
• Operands must be sized !!
reg a;
reg [2:0] b, c;
..
a = 1’b 1;
b = 3’b 010;
c = 3’b 101;
catx = {a, b, c}; //catx = 1_010_101
Lecture 7](https://image.slidesharecdn.com/veriloglect7-130624043621-phpapp02/85/Verilog-lect-7-7-320.jpg)
![10
Replication: Verilog Code of Multiplier
module mul_5x5(A, B, mul_out); // Multiplier Unsigned X
Unsigned Number
input [4:0] A, B ;
output [9:0] mul_out ;
wire [4:0] pp0, pp1, pp2, pp3, pp4 ;
wire [9:0] mul_out ;
assign ppo = A & {5{B[0]}} ;
assign pp1 = A & {5{B[1]}} ;
assign pp2 = A & {5{B[2]}} ;
assign pp3 = A & {5{B[3]}} ;
assign pp4 = A & {5{B[4]}} ;
assign mul_out = pp0 + {pp1, 1’b0} + {pp2, 2’b0} + {pp3,
3’b0} +{pp4, 4’b0} ;
endmodule
Lecture 7](https://image.slidesharecdn.com/veriloglect7-130624043621-phpapp02/85/Verilog-lect-7-10-320.jpg)
![14
Arithmetic Operators
• +, -, *, /, %
• If any operand is x the result is x
• Negative registers:
• regs can be assigned negative but are
treated as unsigned
reg [15:0] regA;
Lecture 7](https://image.slidesharecdn.com/veriloglect7-130624043621-phpapp02/85/Verilog-lect-7-14-320.jpg)
![16
Arithmetic Operators
reg [15:0] regA;
integer intA;
..
intA = -12/3;
//evaluates to –4 (no base
spec)
intA = -’d12/3;
//evaluates to 1431655761
(base spec) Lecture 7](https://image.slidesharecdn.com/veriloglect7-130624043621-phpapp02/85/Verilog-lect-7-16-320.jpg)
Verilog lect 7
- 2. 2 Logical Operators • && → logical AND • | | → logical OR • ! → logical NOT • Operands evaluated to ONE bit value: 0, 1 or x • Result is ONE bit value: 0, 1 or x • A= 6; A&&B → 1&&0 → 0 • B = 0; A | | !B → 1| |1 → 1 • C= x; C | | B → x | | 0 → x, C&&B = 0 Lecture 7
- 3. 3 Bitwise Operators • & → bitwise AND • | → bitwise OR • ~ → bitwise NOT • ^ → bitwise XOR • ~^ or ^~ → bitwise XNOR • Operation on bit by bit basis Lecture 7
- 5. 5 Reduction Operators • & → AND • | → OR • ~& → NAND • ~| → NOR • ^ → XOR • ~^ or ^~ → XNOR • One multi-bit operand → One single-bit result • a = 4’b1001; • c = |a ; // c = 1|0|0|1 = 1 Lecture 7
- 6. 6 Shift Operators • >> → shift right • << → shift left • Result is same size as first operand, always zero filled • a = 4’b1010; • d = a>>2; //d= 0010 • c = a<<1; //c= 0100 Lecture 7
- 7. 7 Concatenation Operator • {op1, op2, ..} → concatenates op1, op2, .. to single number • Operands must be sized !! reg a; reg [2:0] b, c; .. a = 1’b 1; b = 3’b 010; c = 3’b 101; catx = {a, b, c}; //catx = 1_010_101 Lecture 7
- 8. 8 Concatenation Operator caty = {b, 2’b11, a};//caty = 010_11_1 catz = {b, 1}; // WRONG !! • Replication .. catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101 Lecture 7
- 9. 9 Example of Replication We want to multiply A and B 5-bits numbers. Lecture 7
- 10. 10 Replication: Verilog Code of Multiplier module mul_5x5(A, B, mul_out); // Multiplier Unsigned X Unsigned Number input [4:0] A, B ; output [9:0] mul_out ; wire [4:0] pp0, pp1, pp2, pp3, pp4 ; wire [9:0] mul_out ; assign ppo = A & {5{B[0]}} ; assign pp1 = A & {5{B[1]}} ; assign pp2 = A & {5{B[2]}} ; assign pp3 = A & {5{B[3]}} ; assign pp4 = A & {5{B[4]}} ; assign mul_out = pp0 + {pp1, 1’b0} + {pp2, 2’b0} + {pp3, 3’b0} +{pp4, 4’b0} ; endmodule Lecture 7
- 11. 11 Relational Operators • > → greater than • < → less than • >= → greater or equal than • <= → less or equal than • Result is one bit value: 0, 1 or x 1 > 0 → 1 ’b1x1 <= 0 → x 10 < z → x Lecture 7
- 12. 12 Equality Operators • == → logical equality • != → logical inequality • === → case equality • !== → case inequality • 4’b 1z0x == 4’b 1z0x → x • 4’b 1z0x != 4’b 1z0x → x • 4’b 1z0x === 4’b 1z0x → 1 • 4’b 1z0x !== 4’b 1z0x → 0 Lecture 7
- 13. 13 Conditional Operator • cond_expr ? true_expr : false_expr • Like a 2-to-1 mux .. Lecture 7
- 14. 14 Arithmetic Operators • +, -, *, /, % • If any operand is x the result is x • Negative registers: • regs can be assigned negative but are treated as unsigned reg [15:0] regA; Lecture 7
- 15. 15 Arithmetic Operators regA = -16’d12; //stored as 216 -12 = 65524 regA/3 evaluates to 21841 •Negative integers: • can be assigned negative values • different treatment depending on base specification or not Lecture 7
- 16. 16 Arithmetic Operators reg [15:0] regA; integer intA; .. intA = -12/3; //evaluates to –4 (no base spec) intA = -’d12/3; //evaluates to 1431655761 (base spec) Lecture 7