A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC IN 180NM CMOS

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976 –
6480(Print), ISSN 0976 – 6499(Online), Volume 5, Issue 12, December (2014), pp. 25-34 © IAEME
25
A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT
SWITCHED CAPACITANCE BASED MDAC IN 180NM
CMOS
Deep Joshi
M.S. Ramaiah School of Advanced Studies, Coventry Uni, Bangalore-560058,
ABSTRACT
The primary motivation of the work presented in this paper is to significantlyreduce power
consumption in pipelined ADCs using Switched Capacitance based MDAC with Opamp Sharing
configuration. ADC power reduction enables longerbattery life in mobile applications, and lower
cost packaging in wired applications.For conventional ADCs differential amplifiers dominate the
power dissipation in most high-speed analog to digital conversion applications. This work presents a
9 stage, 10-bit Pipelined ADC with Error Correction Algorithm which achieves the dynamic power
consumption of 138.38 mW for 25 MS/s sampling rate at a 1.8V supply voltage in GPDK 180nm
CMOS. All the sub-blocks to generate top level Pipelined ADC have been designed in Cadence
environmentand simulated to output parameters in Cadence Spectre and MATLAB. Designed ADC
achieves 63.17 dB SFDR, INL of 0.35 LSB and DNL of 0.5 LSB.
Keywords: Pipelined ADC, MDAC, Analog & Mixed Signal Circuit Design, CMOS, Low Power
Abbreviations Nomenclatures
ADC Analog to Digital Convertor dB Decibel
CMOS Complementary Metal Oxide MHz Mega Hertz (106
Hz) – Frequency
Semiconductor MS/s Mega Samples per Second
ICMR Input common Mode Range mW Mili Watt (10-3
W) – Power
INL Integral Non‐Linearity Nm NanoMetre (10-9
m) – Length
SFDR Spurious Free Dynamic Range pF Pico Farad (10-12
F) – Capacitance
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Volume 5, Issue 12, December (2014), pp. 25-34
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26
I. INTRODUCTION
Currently, digital chips have occupied a large part of the chip market, but in practical
application they stillcannot do without analog circuits, which transform analog signal into digital
signal because the real world signals are analog. For example, the photocells in a camera produces a
current on the scale of a few electrons per microsecond, while the microphone inside a cell phone
picking up the sound of human voice generates a voltage whose amplitude may vary from a few
microvolts to hundreds of millivolts.Therefore, between the received analog signal and DSP system,
an analog-to-digital interface is required.
The design of ADCs for high speed, high precision and low power dissipation has
continuouslybeen a challenge for analog designers.Among many types of CMOS ADC architectures,
the pipelined ADC has the attractive feature of maintaining high accuracy at high conversion rate
with low complexity and power consumption.For systems whichrequire a medium to high resolution
converter with a system clock at the Nyquist rate, the pipelined ADC is a popular choice.Within the
scope of pipelined ADC research, the focus has beenon techniques to reduce the power consumption
of the MultiplyingDigital to Analog Converter (MDAC), which is typically the largest consumer of
power in the ADC.
Low power consumption in pipelined ADCs is motivated by the fact that many mobile
systems use pipelined ADCs, where low power consumption enables increased battery life and thus
increased user productivity.Switched capacitor circuits fill a critical role in analog/digital interfaces
particularly highly integrated applications. In these applications, a complex, digital-signal-processing
switched capacitive core is often interfaced to real-world inputs andoutputs.In particular, switched-
capacitor circuits exploit the charge storing abilities of CMOS to achieve precision signal
processing[1][2]. Thus, high-performance data converters can be implemented competently in
CMOS. Although an increasing amount of signal processingis performed in the digital domain, the
analog-digital interface will remain a fundamentally necessary element.
II. PIPELINED ADC ARCHITECTURE AND OPERATION
As its name suggests pipelined ADC employs several pipelined stages to achieve high speed
and high resolution.Generic 10-bit pipeline ADC architecture with 1.5 bit stages is shown in Figure
1.The architecture uses 1 stage per bit while each stageresolves 1.5 bits. The additional half bit from
the first 8 stages is used for digital errorcorrection which relaxes the comparison accuracy for each
stage. The final, 9th stage is 2 bit Flash ADC.
Figure 1: Pipelined ADC with 1.5-bit per stage Architecture

27
Each 1.5-bit stage consists of a 1.5-bit ADC, 1.5-bit DAC, and subtractor and signal amplification
circuitry as shown in Figure 1. This stagearchitecture is typically called a multiplying DAC or
MDAC. The MDAC samples theinput voltage at the beginning of the clock period. The sampled
input is converted to athree level (1.5-bit) digital code which is passed to a Digital Encoder to feed
the input to 3levels DAC. The DAC output is subtracted from the sampled signal and the result
isamplified by2 to produce the output signal. The analog output of the MDAC stage is twotimes the
difference between the input and the 1.5 bit DAC.Theadvantages of the pipelined structure lie in the
predefined latency and high throughput [3].
In each stage, the sub DAC resolves 2 bits. Then subtracts its quantization value and amplifies the
resulting residue by a gain of 2. The full input signal ranges from – VRefto +VRef, and the sub ADC
has the thresholds at +VRef/4 and –VRef/4, therefore, the equation system modelling the function is:
∆ܸ௢ =
‫ە‬
ۖ
‫۔‬
ۖ
‫ۓ‬ 2. ∆ܸ௜௡ + ܸோ௘௙, ∆ܸ௜௡ < −
௏ೃ೐೑
ସ
2. ∆ܸ௜௡ , −
௏ೃ೐೑
ସ
≤ ∆ܸ௜௡ ≤
௏ೃ೐೑
ସ
2. ∆ܸ௜௡ − ܸோ௘௙, ∆ܸ௜௡ >
௏ೃ೐೑
ସ
… (1)
Ideal Transfer Function Plot according to Equation 1 is described in Figure 2. By observing
the model equation and transfer function plot, there is the need for havingthree functions in the
MDAC: a digital-to-analog conversion, a sample-and-hold function, and amplification. To achieve
the desired resolution, linearity, and signal-to-noise ratio, each stagemust be designed such that non-
ideal effects do not excessively degrade the overallperformance. Capacitor linearity and matching,
Opamp gain and settling, andthermal noise are all critical to pipeline ADC performance.
Figure 2: Ideal Transfer Function of 1.5-bit MDAC Stage
III. LOW POWER IMPLEMENTATION OF PIPELINED ADC
In the interest of prolonging battery life in mobile systems, recently there has been a shift to
achieve even more powersavings afforded from MDAC and Opampbased techniques by substituting
the circuitry with more power efficient circuit or making architectural level changes for reduction in
power consumption. In this work Opamp level, MDAC stage level and architectural level power
efficient implementations are scrutinized.

28
A. Switched Capacitance based MDAC implementation
The proposed 1.5-bit pipeline stage is denoted by Figure 3, which represents three structures:
Opamp, 1.5-bit Flash ADC and Switched capacitor network.
Figure 3: 1.5-bit MDAC Structure
A switched-capacitor circuit is realized with the useof some basic building blocks such as
opamp, capacitor, CMOS switches, andnon-overlapping clocks.Each MDAC stage procedure
according to Figure 2, starts by performing a low resolution quantization of stage input, converts the
result result of a quantization to an analog value and subtracts the analog value to the stage DAC
input.The resulting difference is then amplified by gain of two to compensate the extra bit of Digital
Correction.
Figure 4: Switched Capacitor Circuit Adaption in MDAC
The procedure can further be streamlined by dividing into two phases as per non-overlapping
clock phases. In phase1, the input signal is sampled into both ‫ܥ‬s and ‫ܥ‬F. In phase2, thebottom plate
of ‫ܥ‬F is connected to the output of opamp and the bottom plate of ‫ܥ‬S is connected to the reference
voltages determined by the digital output of sub-ADC. Characterization of phases is described by
Figure 4 and transfer function is shown in Equation 2.

International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976
6480(Print), ISSN 0976 – 6499(Online), Volume 5, Issue 12, December (2014), pp.
ܸை௎் =
஼ೄା஼ಷ
஼ಷ
ܸூே − ܸ஽஺஼… (2)
The capacitor is the key component to the MDAC. Capacitors also take up a large amount
ofdie area. Therefore, it is important to keep capacitor sizes as small as possible to reduce die
yet large enough to reduce noise effects
based on our desired signal-to-noise ratio (SNR) of around 60dB.
B. Opamp Sharing Technique
Like it was previously mentioned the main concern of this
reduction of overall power consumption even if there are eight opamps for each of the eight switched
capacitor networks. This approach works by sharing an opamp between two consecutive stages in the
pipeline and the power consumption
reducing the number of necessary opamps by half. This implementation is represented in
Figure
The use of this technique is only possible because of the temporal way that the switched
capacitor circuit uses the opamp as denoted in Figure 4. With the classical approach the opamp is
only being used in half of a clock cycle, which is during amplificati
during the sampling phase. So instead of being idle, the resource can be doing its work where it is
needed as described in Figure 5.The sharing of opamp is made between adjacent stages because of
those two stages have their switched capacitor networks operat
they are in opposite clock phases, it is possible to shar
In architecture based on this technique, the non
reset, so every input sample is affected by the finite gain error component from the previous sample.
Also noise sources including flicker noise and opamp’s intrinsic offset voltage cannot be cancelled
because the amplifier is always in active mode [
which is input dependent [8]. To compensate this, proposed technique augments two additional
switches at input terminal, as it is represented in Figure 6.
International Journal of Advanced Research in Engineering and Technology (IJARET), ISSN 0976
6499(Online), Volume 5, Issue 12, December (2014), pp. 25-
29
ofdie area. Therefore, it is important to keep capacitor sizes as small as possible to reduce die
yet large enough to reduce noise effects [4].The capacitor size for the MDAC is selected to be 50fF
noise ratio (SNR) of around 60dB.
Opamp Sharing Technique
Like it was previously mentioned the main concern of this work is trying to substantiate
sumption and die area of the ADC can be reduced significantly [5
reducing the number of necessary opamps by half. This implementation is represented in
Figure 5: Opamp Sharing Technique
of a clock cycle, which is during amplification phase, and it’s in relaxation
So instead of being idle, the resource can be doing its work where it is
The sharing of opamp is made between adjacent stages because of
switched capacitor networks operating at opposite clock phases [6
they are in opposite clock phases, it is possible to share the opamp between two stages.
In architecture based on this technique, the non-zero input voltage of the amplifier is
fier is always in active mode [7]. This shortcoming results in memory effects
]. To compensate this, proposed technique augments two additional
switches at input terminal, as it is represented in Figure 6.
-34 © IAEME
ofdie area. Therefore, it is important to keep capacitor sizes as small as possible to reduce die area,
].The capacitor size for the MDAC is selected to be 50fF
work is trying to substantiate
can be reduced significantly [5], by
reducing the number of necessary opamps by half. This implementation is represented in Figure 5.
on phase, and it’s in relaxation
So instead of being idle, the resource can be doing its work where it is
The sharing of opamp is made between adjacent stages because of
ing at opposite clock phases [6]. Since
e the opamp between two stages.
zero input voltage of the amplifier is never
]. This shortcoming results in memory effects,
]. To compensate this, proposed technique augments two additional

30
Figure 6: Schematic of Pipeline Stage with Shared Opamp
C. Pipeline Stage Scaling
The precision requirements of each pipeline stage decrease along the pipeline (i.e.)the first
stage must be most precise, subsequent stages need only be as precise as theprevious stage less the
number of bits resolved previously [9]. Thus analog designcomplexity can be reduced along the
pipeline as shown in Figure 7 (less opamp gainand bandwidth for later stages).
Figure 7: Pipeline Stage Scaling – Stages are Sequentially Smaller
As the backend pipeline stages have relaxed precisionrequirements, they can be designed
with smaller area and lower power consumption.Hence it is possible to significantly reduce total
power consumption and area by havingmany stages, where each subsequent stage opamp in the
pipeline is sized smaller than theprevious stage, which is implemented in ADC as shown in Figure 8.
Figure 8: Pipeline Stage Scaling Implementation

31
IV. 10-BIT PIPELINED ADC TOP-LEVEL DESIGN
Top level design of Pipelined ADC with implementation of low power techniques discussed
in Section III, is described in Figure 9.
Figure 9: Architecture of Developed 10-bit 25MS/s Pipelined ADC
A fully differential mode 10-bit pipelined ADC is designed and implemented in 0.18µm
GPDK CMOS technology with 1.8V power supply. All sub-blocks are designed in Cadence Virtuoso
and merged together as depicted in Figure 9, to implement the top level design of Pipelined ADC.
All sub-blocks are simulated and analyzed in Cadence Spectre for correctness.
The synchronization logic is needed because of pipeline latency. The latency exists because
this architecture doesn’t make a full conversation at the same instant. This means that the front stages
converted codes need to be stored for more clock cycles than the last stages, which is made with D
flip-flop. The full conversion in this design is achieved after five clock cycles. The digital correction
can also be called digital redundancy because of the extra bit that each one of the pipeline stage has
to convert. The Principal behind that is, The Flash ADC present in this stages is composed by two
comparators with threshold voltages of –VRef/4 and +VRef/4, resulting in three possible digital output
codes. Using a higher resolution in each stage leads to redundant bits and Digital Error Correction
allows up to ±0.5 LSB voltages for comparator offsets.
V. RESULTS AND DISCUSSION
The correctness of developed 10-bit Pipelined ADC is verified for Static Parameters,
Dynamic Parameters and Power Dissipation in this section.
A. Static Parameter
Static parameters, as the name suggests, pertain to the performance of the ADC with respect
to some static or dc input voltage. These parameters are namely, the differential non-linearity (DNL)
and integral non-linearity (INL). ADC step-size is defined as the smallest change in input voltage
required, to obtain a unit change in the output code. For an ideal ADC, the step-size is uniform.
DNL, for the ith
code transition, is defined as the difference between the actual step-size and the ideal
step size that causes the transition:

32
DNLi = Actual step-size for ith
code transition – Ideal step-size …3
INL, for the ith code, is defined as follows (assuming ADC codes start from i=0):
INLi=∑௜
௝ୀ଴ DNLj …4
Histogram test is the estimation of the static transfer characteristic of the ADC under test.
The test uses the histogram of measured data and calculates the INL and DNL estimators [10].
Output waveform of Histogram test for INL and DNL parameters are shown in Figure 10 and
Figure11 respectively. As per simulated output, INL for developed ADC is 0.35 LSB and DNL is 0.5
LSB.
Figure 10: 256-point Histogram Test for INL Measurement
Figure 11: 256-point Histogram Test for DNL Measurement
B. Dynamic Parameter
Dynamic parameters are a measure of the ADC performance with respect to a time-varying
input signal.To measure theseparameters, a pure sinusoid input is fed to the ADC and the ADC
output spectrum isanalyzed using techniques such as Fast Fourier Transform (FFT).To verify ADC
performance, noise parameter SFDR is analyzed in frequency domain by FFT test as shown in
Figure 12. Theresults provide information about the amplitudes and frequencies of the harmonics of
thesignal relative to the carrier and relative to the full scale of the ADC.

33
Figure 12: FFT Analysis for Developed ADC
C. Power Analysis
Figure 13: Output Power Simulation for Developed ADC
To analyze the power, Power Meter is implemented at the voltage sourceand output of Power
Meter is simulated for Transient analysis [11]. The simulated dynamic poweroutput of developed 10
bit Pipelined ADC for 20 MHz input is as shown in Figure 13. Ashighlighted by vertical marker in
Figure 13, dynamic power consumption of developed Pipelined ADC is 138.3 mW.

34
VI. CONCLUSION
A 10-bit 25 MS/s Pipelined ADC is developed in 180nm CMOS to achieve higher power
efficiency. Switched Capacitance based MDAC circuit with consecutive stage opamp sharing is
proposed for memory effect elimination and lower power profile. Pipelined stage scaling is
comprised for power and area reduction of Pipelined ADC and overall power consumption of 138.3
mW is achieved. SFDR of 63.1 dB and SNDR of 58.9 dB is achieved from designed ADC, which
depicts better power performance of overall design. INL and DNL of 0.35 LSB and 0.5 LSB is
achieved, which describes ultra-efficiency in analog to digital conversion of developed ADC.
VII. REFERENCES
[1] A. Abo, Design for Reliability of Low Voltage, Switched Capacitor Circuits, Master of
Science thesis, University of California, Berkeley, CA, 1999.
[2] D. Cline, Noise, Speed and Power Trade-offs in Pipelined ADC, Doctor of Philosophy in
Engineering thesis, University of California, Berkeley, CA, 1995.
[3] S. Ryu, K. Bacriana, A 10-bit 50 MS/s Pipelined ADC with Opamp Current Reuse, IEEE
Journal of Solid-State Circuits,42(3), 2007, 475-485.
[4] R. Schreier, G.C. Temes, Design-oriented Estimation of Thermal Noise in Switched
Capacitor Circuits, IEEE Transaction on Circuits and Systems-I, 52(11), 2005, 2358-2368.
[5] K. Nagaraj, S. H. Lewis, A 250 mW 8-bit 52 MS/s Parallel-pipelined A/D Convertor with
Reduced no. of Amplifiers, IEEE Journal of Solid-State Circuits, 32(7) 1997, 312-325.
[6] P. Y. Wu, V. S. Cheung, H. C. Luong, A 1-V 100-MS/s 8-bit CMOS Switched-opamp
Pipelined ADC using Loading-freearchitecture,IEEE J Journal of Solid-State Circuits, 42(4),
2007, 730-738.
[7] http://www.maximintegrated.com/en/app-notes/index.mvp/id/1023, Aug 20th
, 2014.
[8] K. Chandrashekar,B. Bakkaloglu, A 10 b 50 MS/s Opamp-Sharing Pipeline A/D with
Current-Reuse OTAs, IEEE Transactions on VLSI Systems, 19(9), 2011, 1610-1616.
[9] I. Ahmed, D.A. Johns, A high bandwidth power scalable sub-sampling 10-bit Pipelined ADC
with embedded sample and hold, Proc. 33rd
European Solid-State Conference, 13 Sept. 2007.
[10] IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters.
[11] Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits Analysis and Design,
3rd
edition (New York, McGraw-Hill, 2003).
[12] Vijay Kumar Jinde, Nagaraju Boya, Swapna Chinthakunta and Ramanjappa Thogata,
“Design and Implementation of Low Power Pipelined 64-Bit RISC Processor Using FPGA”
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[13] Qazi Raza Abdul Quadir, Arif Rasool, Manan Mushtaq and Yasirbhat, “Design and
Simulation of A Non-Pipelined, Multi- Cycle 16 Bit RISC Educational Processor Using
Verilog HDL” International journal of Electronics and Communication Engineering
&Technology (IJECET), Volume 5, Issue 9, 2014, pp. 14 - 23, ISSN Print: 0976- 6464, ISSN
Online: 0976 –6472.

A 10-BIT 25 MS/S PIPELINED ADC USING 1.5-BIT SWITCHED CAPACITANCE BASED MDAC IN 180NM CMOS

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