Advanced MOSFET
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This document discusses advanced MOSFET architectures and their advantages over traditional bulk MOSFETs. It describes issues with bulk MOSFETs like short channel effects and proposes solutions like multi-gate architectures and high-k dielectrics. Specifically, it examines double-gate MOSFETs, tri-gate MOSFETs, gate-all-around MOSFETs, SOI MOSFETs, FinFETs, and tunnel FETs, outlining their characteristics and benefits over other designs for low power electronics applications.
Advanced MOSFET
- 1. Advanced MOSFET Architectures Arpan Deyasi RCCIIT, Kolkata 19-06-2021 Arpan Deyasi, RCCIIT, India 1
- 2. Present problems in Bulk MOSFET Excessive short-channel effects Minimum channel length becomes 50 nm approx., can’t be reduced further Lower threshold for Gate oxide scaling Lower threshold for Supply voltage Discrete dopant fluctuations substrate S D channel Dielectric G substrate S D 19-06-2021 Arpan Deyasi, RCCIIT, India 2
- 3. Possible Solutions Better gate control to nullify the short channel effect Incorporation of high-K dielectric to reduce tunneling effect, which simultaneously helps to reduce dielectric thickness Use of semiconductors with higher carrier mobility as substrate material 19-06-2021 Arpan Deyasi, RCCIIT, India 3
- 4. Better gate control Novel architectures are proposed for the purpose Better scalability and lower sub threshold current Multi-gate architecture Gate wrapping SOI with multi-gate 19-06-2021 Arpan Deyasi, RCCIIT, India 4
- 5. Source Bottom Gate Multi-gate Architecture First design is Double-Gate MOSFET Source Drain Channel Top Dielectric Bottom Dielectric Drain Top Gate 19-06-2021 Arpan Deyasi, RCCIIT, India 5
- 6. Double-Gate MOSFET Drain Source Gate Gate 19-06-2021 Arpan Deyasi, RCCIIT, India 6
- 7. Double Gate MOSFET Front and back gates control carrier flow in channel region Channel length is scalable upto 30 nm Ultrathin channel works as quantum confined region Lower subthreshold slope Lower gate leakage ION/IOFF ratio is better compared with single gate MOSFET 19-06-2021 Arpan Deyasi, RCCIIT, India 7
- 8. Drawbacks of Double Gate MOSFET Electric field between body and drain increases band-to-band tunneling probability Small channel length provides reduced potential width, which leads to quantum mechanical tunneling between source and drain Owing to lower potential barrier, thermionic emission takes place Quantum confinement effect in ultrathin body region 19-06-2021 Arpan Deyasi, RCCIIT, India 8
- 9. Gate Tri-Gate MOSFET Gate Source Gate Drain 19-06-2021 Arpan Deyasi, RCCIIT, India 9
- 10. Tri-Gate MOSFET Conducting channel forms across all three sides, two on sides, one at top Additional control enables maximum possible current flow at ON state, makes close to zero when OFF state, and helps the device to switch as quick as possible between the two states 19-06-2021 Arpan Deyasi, RCCIIT, India 10
- 11. Advantages of Tri-Gate MOSFET Performance gain at lower operating voltage Low power operation speaks for power reduction Higher drive current Improved switching characteristics 19-06-2021 Arpan Deyasi, RCCIIT, India 11
- 12. Disadvantages of Tri-Gate MOSFET Conventional fabrication technology makes hindrance for non-planar growth Fabrication of semiconductor ‘fin’ of nano-dimension Fabrication of matched gates on multiple sides of ‘fin’ 19-06-2021 Arpan Deyasi, RCCIIT, India 12
- 13. Gate Quadruple-Gate MOSFET Gate Source Gate Drain Gate 19-06-2021 Arpan Deyasi, RCCIIT, India 13
- 14. Quadruple-Gate MOSFET Better gate control …………… Problem is related to fabrication …………… Therefore, alternative architecture is considered having same effect …………… Gives birth to Gate-All-Around Architecture 19-06-2021 Arpan Deyasi, RCCIIT, India 14
- 15. 19-06-2021 Arpan Deyasi, RCCIIT, India 15 GAA MOSFET gate drain source channel
- 16. 19-06-2021 Arpan Deyasi, RCCIIT, India 16 Advantages of GAA MOSFET Better gate controllability as gate is all around the channel Leakage current is almost negligible Short channel effect is negligible Higher drain current Lower Subthreshold slope
- 17. 19-06-2021 Arpan Deyasi, RCCIIT, India 17 SOI Technology Si channel layer is grown on oxide layer Negligible junction capacitance Low leakage current Electrical active layer is isolated from bulk layer Reduced parasitic effect Superior electrostatic control
- 18. 19-06-2021 Arpan Deyasi, RCCIIT, India 18 SOI MOSFET MOSFET device in which a semiconductor layer is formed on an insulator layer which may be a buried oxide (BOX) layer formed in a semiconductor substrate Why it is on demand? Allows continuous miniaturization of MOSFET Low parasitic resistances and capacitances Compatible with existing fabrication techniques Providing higher current densities
- 19. 19-06-2021 Arpan Deyasi, RCCIIT, India 19 SOI MOSFET structure n+ n+ gate source drain gate dielectric p-body n+ n+ gate source drain p-body dielectric gate p BOX
- 20. 19-06-2021 Arpan Deyasi, RCCIIT, India 20 Different SOI MOSFET Partially depleted MOSFET Fully depleted MOSFET Thickness of p-region (sandwiched between gate oxide and buried oxide) is greater than bulk depletion width Si film thickness is less than bulk depletion width KINK effect is observed No such effect is observed Comparatively slower Comparatively faster Behaves like bulk MOSFET Doesn’t behave like bulk MOSFET Used in analog circuit Used in low power applications Drawback: packaging scalability Drawback: complex fabrication process
- 21. 19-06-2021 Arpan Deyasi, RCCIIT, India 21 Partially depleted MOSFET Fully depleted MOSFET source source Front-gate Front-gate drain drain Back-gate Back-gate Body
- 22. 19-06-2021 Arpan Deyasi, RCCIIT, India 22 Advantages of SOI MOSFET Lower parasitic capacitance due to isolation from semiconductor substrate, which improves power conservation Resistance to latch-up due to complete isolation of n-well and p-well structures Lower leakage currents Reduced temperature dependency Steeper sub-threshold swing
- 23. 19-06-2021 Arpan Deyasi, RCCIIT, India 23 Disadvantages of SOI MOSFET Kink effect Self-heating effect Floating body effect can get freely charged/ discharged due to transients which affects threshold voltage
- 24. Gate FinFET Gate Gate Drain 19-06-2021 Arpan Deyasi, RCCIIT, India 24 Source
- 25. 19-06-2021 Arpan Deyasi, RCCIIT, India 25 FinFET characteristics Non-planar DGMOSFET built on SOI substrate Conducting channel is wrapped up by Si thin ‘fin’ which forms body of the device Thickness of ‘fin’ determines effective channel length of device It is basically vertical Double Gate MOSFET
- 26. 19-06-2021 Arpan Deyasi, RCCIIT, India 26 Advantages of FinFET Suppressed short channel effect Higher driving current Higher technological maturity than planar DGMOSFET More compact in terms of architecture Lower cost
- 27. 19-06-2021 Arpan Deyasi, RCCIIT, India 27 Disadvantages of FinFET Reduced mobility for electrons Higher source and drain resistances Poor reliability
- 28. 19-06-2021 Arpan Deyasi, RCCIIT, India 28 Direction towards low power electronics Lower subthreshold swing Higher speed of operation Steeper subthreshold slope Promising candidate for low power electronics
- 29. 19-06-2021 Arpan Deyasi, RCCIIT, India 29 Tunnel FET Drain Gate substrate BOX p+ n+ i Source p-TFET Drain Gate substrate BOX n+ p+ n Source n-TFET
- 30. 19-06-2021 Arpan Deyasi, RCCIIT, India 30 Tunnel FET characteristics Uses gate-controlled p-i-n structure with carrier with carriers tunneling through barrier Interband tunneling occurs in heavily doped p+ - n+ junctions Operation is based on principle of band-to-band tunneling Switch between OFF and ON states at low voltages Less amount of current compared with MOSFET
- 31. 19-06-2021 Arpan Deyasi, RCCIIT, India 31 Tunnel FET characteristics Very low leakage current at OFF state Steeper subthreshold slope Higher ON-to-OFF current ratio
- 32. 32 OFF ON 𝑬𝒄 𝑬𝒗 Channel Source Drain TFET Band Diagram
- 33. 19-06-2021 Arpan Deyasi, RCCIIT, India 33 Electrical characteristics of TFET OFF state: wider potential barrier restricts tunneling ON state: gate voltage exceeds threshold voltage which reduces potential barrier width, and therefore tunneling starts Channel valence band lifted above source conduction band which makes tunneling possible Only carriers in energy window ΔΦ can tunnel from source to channel
- 34. 19-06-2021 Arpan Deyasi, RCCIIT, India 34 Advantages of Tunnel FET Subthreshold slope lower than 60 mV/decade Highest possible ON current and lowest possible OFF current Higher intrinsic voltage gain and higher maximum oscillation frequency at low current levels compared with FinFET
- 35. 19-06-2021 Arpan Deyasi, RCCIIT, India 35 Disadvantages of Tunnel FET Magnitude of current is smaller than that of MOSFET