ALGORITHMIC STATE MACHINE
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This document introduces the basics of asynchronous sequential machine (ASM) notation for describing finite state machines: - ASM uses state boxes, decision boxes, and conditional boxes to graphically describe the operations of a finite state machine more concisely than conventional flowcharts. State boxes indicate states, decision boxes represent conditional transitions between states, and conditional boxes list outputs. - An ASM block consists of interconnecting a single state box with decision and/or conditional boxes, representing the operations that occur within a single clock cycle as the system enters the next state. All elements within the block are evaluated simultaneously. - Timing considerations require that all sequential elements be controlled by a master clock, though multiple clocks can
ALGORITHMIC STATE MACHINE
- 1. Pune Vidyarthi Griha’s COLLEGE OF ENGINEERING, NASHIK – 3. “ASM” By Prof. Anand N. Gharu (Assistant Professor) PVGCOE Computer Dept. 30th June 2017 .
- 2. CONTENTS :- 1. Introduction to ASM 2. The Chart Notation 3. The State Box 4. Decision Box 5. Condition Box 6. Examples 7. MUX Controller Method 8. Examples
- 3. INTRODUCTION OF ASM •Used to graphically describe the operations of an FSM more concisely •Resembles conventional flowcharts – differs in interpretation. •Conventional flowchart – sequential way of representing procedural steps and decision paths for algorithm -No time relations incorporated •ASM chart – representation of sequence of events together with timing relations between states of sequential controller and events occurring while moving between steps
- 4. •Three basic elements: state box, decision box and conditional box -State and decision boxes used in conventional flowcharts -Conditional box characteristic to ASM •State box -Used to indicate states in control sequence •Register operations and output signals used to control generation of next state written
- 5. State box •Represents one state in the ASM. •May have an optional state output list. •Single entry. •Single exit to state or decision boxes.
- 6. ACOE161 - Digital Logic for Computers - Frederick University State Box State name T3 •Binary code of T3 – 011 •Register operation R <- 0 •START – name of outputs signal generated in this stage
- 7. ACOE161 - Digital Logic for Computers - Frederick University Decision box • Provides for next alternatives and conditional outputs. • Conditional output based on logic value of Boolean expression involving external input variables and status information. • Single entry. • Dual exit, denoting if Boolean expression is true or false. • Exits to decision, state or conditional boxes.
- 8. ACOE161 - Digital Logic for Computers - Frederick University Decision Box •Input condition subject to test inside diamond shape box •Two or more outputs represent exit paths dependant on value of condition in decision box •Two paths for binary based conditions
- 9. ACOE161 - Digital Logic for Computers - Frederick University Conditional output box • Provides a listing of output variables that are to have a value logic-1, i.e., those output variables being asserted. • Single entry from decision box. • Single exit to decision or state box.
- 10. ACOE161 - Digital Logic for Computers - Frederick University •In state T1 Output signal START generated Status of input E checked •If E = 1, R <- 0, otherwise remains unchanged •Conditional operation executed depending on result of coming from decision box Conditional Box
- 11. ACOE161 - Digital Logic for Computers - Frederick University ASM Block • Consists of the interconnection of a single state box along with one or more decision and/or conditional boxes. • It has one entry path which leads directly to its state box, and one or more exit paths. • Each exit path must lead directly to a state, including the state box in itself. • A path through an ASM block from its state box to an exit path is called a link path.
- 12. ACOE161 - Digital Logic for Computers - Frederick University Timing Considerations All sequential elements in datapath and control path controlled by master-clock generator. Does not necessarily imply single clock in design. •Multiple clocks can be obtained through division of clock signals from master-clock generator. •Not only internal signals, but also inputs synchronized with clock. •Normally, inputs supplied by other devices working with the same master clock. •Some inputs can arrive asynchronously Difficult to handle by synchronous designs, require asynchronous glue-logic.
- 13. ACOE161 - Digital Logic for Computers - Frederick University •In conventional flowchart, evaluation of each chart element takes one clock cycle Step 1: Reg A incremented Step 2: Condition E evaluated Step 3: Based on evaluation results, state T2, T3 or T4 entered •In ASM the entire block considered as one unit •All operations within block occurring during single edge transition The next state evaluated during the same clock System enters next state T2, T3 or T4 during transition of next clock Block
- 14. ASM Block • An ASM block describes the operation of the system during the state time in which it is in the state associated with the block. • The outputs listed in the state box are asserted. • The conditions indicated in the decision boxes are evaluated simultaneously to determine which link path is to be followed. • If a conditional box is found in the selected path then the outputs found in its output list are asserted. • Boolean expression may be written for each link path. The selected link paths are those that evaluate to logic-1.
- 15. Example 2 • Extract the FSM diagram from the ASM diagram T0 x F T1 T2 x E T4 T6 T3 T7 0 0 0 T5 1 0 1 1
- 19. DESIGN MUL CONTROLLER METHOD