Configurable fifo with panda fv
- 1. Configurable FIFO with Panda FV
- 2. Configurable FIFO • FIFO has two control signals: push and pop • Each time push is asserted, the design captures value present on 'in' bus and stores it in internal memory. • Each time pop is asserted, the design discards the oldest value from internal memory and drives the next (less old) value on 'out' bus. • Register Access Bus for FIFO Configuration FIFO push pop in out Register Access
- 3. FIFO Interface Name Bits Dir Description clk 1 IN Clock rst 1 IN Active-high reset push 1 IN Push data into a FIFO pop 1 IN Pop data out from FIFO empty 1 OUT FIFO is empty full 1 OUT FIFO is full in Width IN FIFO Data In out Width IN FIFO Data out cpu_req_data 8 IN Register Interface Input cpu_rsp_data 8 OUT Register Interface Output
- 4. FIFO Registers Name Addr Access Type Description MAX_DEPTH 0 RW Capacity of the FIFO. Valid range: from 2 to depth. Written value shall be less by one than the desired capacity. Recent written value is returned upon the read. Shall not be written while there are entries in the FIFO. RPTR 1 R Current value of a read pointer is returned upon the read. Used for diagnostic purposes. WPTR 2 R Current value of a write pointer is returned upon the read. Used for diagnostic purposes TOTAL_ENTRIES 3 R Total number of values pushed into the FIFO since the recent reset. Used for statistic collection.
- 5. Register Interface • Packet-Based Interface: • Commands: IDLE, READ, WRITE, READ_REPLY, READ_ERROR, WRITE_ACK, WRITE_ERR • Address valid only for READ and WRITE; otherwise reserved • Value present only for READ_REPLY and WRITE Command Value Address 73 40
- 6. Property to Verify • For all possible configurations of FIFO_DEPTH, FIFO operation is valid. FIFO push pop in out Register Access Property
- 7. FIFO Testbench • Re-used between Dynamic Simulation and Formal Analysis with Panda FV • Parametric, with data width and FIFO depth FIFO push pop in out Register Access Data Driver Checker Control Driver
- 9. Register Interface • Goal: program FIFO depth randomly • Use parametric cell tbs_rnum to constantly generate random number from 2 to 16 • Capture random data for register write access
- 10. Data Generation & Checking Generation: – Supply increasing numbers; choose random increment at the beginning of test: Data check: – Just check for data values increase with known increment Generate radnom delta 0 3 6 9 12 0 2 4 6 8 0 1 2 3 4 0 4 8 12 16 … … … …
- 12. Data Checking Code Check if output data not increases with the given increment in the working mode (tcnt > 5):
- 13. FIFO Simulation
- 14. FIFO Formal Analysis • Run bounded model checking, 20-25 cycles from initial state • Formal Analysis statically covers : – All possible configurations – All possible data increments – All possible push & pop timings As a result, thorough verification of configurable FIFO design