Design And Analysis Of Low Power High Performance Single Bit Full Adder
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The document presents the design and analysis of a low-power, high-performance single-bit full adder using only 8 transistors and pass-transistor logic. It emphasizes the importance of reducing power consumption, delay, and ground bounce noise through techniques such as power gating and forward body bias. The proposed adder demonstrates significant improvements in performance compared to existing designs, particularly in terms of power reduction and noise management.
![INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY
VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303
61
Design And Analysis Of Low Power High
Performance Single Bit Full Adder
JAYACHITHRA P1
SARAVANA KUMAR P2
1
PG Scholar of ECE department 2
Asst. professor of ECE Department
Kalasalingam Institute of Technology Kalasalingam Institute of Technology
shyachithra@gmail.com kumar271985@gmail.com
Abstract: Adder is the significant circuit in arithmetic operations. Adder cells are designed for power and delay
reduction. Now ground bounce noise is also necessary for good performance. In this paper the full adder is
designed using only 8 Transistors using Pass Transistor Logic (PTL). The power gating technique is one such a
best technique which reduces leakage power through the ground. This technique is implemented using sleep
transistor added between ground rail and actual ground. Here a single bit 8 Transistor full adder is proposed. We
will perform analysis and simulation of various parameters like power, delay and ground bounce noise using
tanner EDA tool 180nm CMOS Technology.
Index terms- Full adder, Ground bounce noise, PTL, Sleep transistor
1. INTRODUCTION
With the extensive development of electronic
devices, the low power VLSI system is most
important. The single bit full adder is used in various
arithmetic operations, digital signal processing and
micro controller. The area of full adder is the major
concern for area reduction. The current 50-60 %
affects the performance of system [1-2]. The full
adder is designed with increased transistor count
which is used in multiplexer, compressor and parity
checker [3-5]. The ground bounce noise disturb the
performance of device. The scope of paper is to
implement full adder to reduce the power and delay
[6-7]. To achieve reduced the ground bounce noise,
forward body bias with multiple thresholds is
introduced to add additional wait mode which
separate the sleep and active mode [8]. The ground
bounce noise and leakage current during mode
transistor cause performance reduction. To overcome
this stacking power gating technique is introduced [9].
The Nano CMOS technology is implemented for full
adder but the area requirement is high compared to
our paper [10]. The degenerate pass transistor logic is
developed for low power requirement of full adder.
But the threshold voltage loss problem occurred [11].
One of the most important techniques is MTCMOS
also known as power gating technique which is used
for reduce the leakage power and leakage current in
an idle mode and to improve the performance of
device in active mode [12-13]. The main idea
behind this technique is to turn off the device in sleep
mode. In our paper 8 transistor full adder is designed
with power gating technique to reduce noise, delay
and area.
2. 8T FULL ADDER DESIGN
The full adder has been designed using various
logic styles to reduce the area and power dissipation.
Figure 1: 8T full adder
To analyses the various parameters of adders we
use the pass transistor 8T full adder as our base
structure as shown in the figure 1 which have 2 xnor
C
B
A
A C
Carry
Sum
PM1 PM2
NM1
NM2
NM3
NM4
PM3
NM5](https://image.slidesharecdn.com/ictte051-150928053558-lva1-app6892/85/Design-And-Analysis-Of-Low-Power-High-Performance-Single-Bit-Full-Adder-1-320.jpg)
![INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY
VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303
64
TABLE 3: GROUND BOUNCE NOISE
Interconnection circuit Ground bounce noise
(nV)
14T Full Adder 4.0834
10T Full Adder 2.6308
10T Full Adder with
Power Gating
Technique
2.5354
8T Full Adder with
Power Gating
Technique
0.987
6. CONCLUSION
The proposed 8T Full adder is designed in
Tanner EDA toll version 13.0. The performance of
full adder is best compared to others. The 8T full
adder performance is examined to have a better delay,
power and ground bounce noise. It gives reduction in
power, ground bounce noise and delay than existing
full adder.
REFERENCES
[1] R.Singh S.akashe “design and analysis of low stand
by leakage current and reduced ground bounce
noise of static 10T cmos full adder”vol 7 no 2 june
2014, african Journal of Computing & ICT
[2] S.G.Nagendra and A.Chandkasam,”Leakage in
Nanometer CMOS Technologies, New York :
Springer-verilog , 2006
[3] M. Hossseinghadiery H. Mohammadi, nadasenejani
“two low power high Performance FullAdders with
Minimum Gates,” International Journal of Electrical
and Computer Engineering 10 2009.
[4] Radu Zlatanovici, Sean Kao, Borivoje Nikolic,
“Energy-Delay of Optimization 64-Bit Carry-
Lookahead Adders With a 240ps 90nm CMOS
Design Example,” IEEE J. Solid State circuits,
vol.44, no. 2, pp. 569-583, Feb. 2009.
[5] K.Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S.
Mehrabi, N. Dadkhai, “Low-Power and High-
Performance 1-bit CMOS Full Adder Cell,” Journal
of Computers, Academy Press, vol. 3, no. 2, Feb.
2008.
[6] Pren R. Zimmermann, W. Fichtner, “Low-power
logic styles: CMOS versus pass-transistor logic,”
IEEE J. Solid- State Circuits, vol. 32, pp. 1079–
1090, July 1997.
[7] Tripti Sharma, K.G.Sharma, Prof.B.P.Singh, “High
Performance Full Adder : Cell:Comparative
Analysis”, Proceedings of 2010 IEEE Students’
Technology Symposium, IIT Kharagpur, 3-4 April
2010.
[8] Shashikant Sharma, Anjan Kumar, Manisha
Pattanaik, and Balwinder Raj, “Forward Body
Biased Multimode Multi-Threshold CMOS
Technique for Ground Bounce Noise Reduction in
Static CMOS Adders”, International Journal of
Information and Electronics Engineering, Vol. 3,
No. 6, November 2013.
[9] R. Bhanuprakash, Manisha Pattanaik and S. S.
Rajput, “ Analysis and Reduction of Ground
Bounce Noise and Leakage Current During Mode
Transition of Stacking Power Gating Logic Circuits
”,IEEE Region 10 Conference TENCON 2009, pp.
1-6.
[10] Manisha Pattanaik, Muddala V. D. L. Varaprasad
and Fazal Rahim Khan “ Ground Bounce Noise
Reduction of Low Leakage 1-bit Nano-CMOS
based Full Adder Cells for Mobile Applications”,
International Conference on Electronic Devices,
Systems and Applications (ICEDSA) 2010, pp. 31-
36.
[11] Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu,”
Low Power 10-Transistor Full Adder Design Based
on Degenerate Pass Transistor Logic, IEEE. 2012.
[12] Y.Chang, S.k. Gupta, and M. A. Breuer,” analysis
of Ground Bounce in Deep Sub-micron Circuit,
Procceding15th IEEE VLSI Test
Symposium,”1999, pp.110-116 .
[13] V. Kosonocky, M. Immediato, P. Cottrell, T. Hook,
R. Mann, and J. Brown, “Enhanced multi- threshold
(MTCMOS) circuits using variable bias,” in
Proceedings of International Symposium on Low-
Power Electronics and Design, pp. 165-169, Aug.
2001.](https://image.slidesharecdn.com/ictte051-150928053558-lva1-app6892/85/Design-And-Analysis-Of-Low-Power-High-Performance-Single-Bit-Full-Adder-4-320.jpg)
Design And Analysis Of Low Power High Performance Single Bit Full Adder
- 1. INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 61 Design And Analysis Of Low Power High Performance Single Bit Full Adder JAYACHITHRA P1 SARAVANA KUMAR P2 1 PG Scholar of ECE department 2 Asst. professor of ECE Department Kalasalingam Institute of Technology Kalasalingam Institute of Technology shyachithra@gmail.com kumar271985@gmail.com Abstract: Adder is the significant circuit in arithmetic operations. Adder cells are designed for power and delay reduction. Now ground bounce noise is also necessary for good performance. In this paper the full adder is designed using only 8 Transistors using Pass Transistor Logic (PTL). The power gating technique is one such a best technique which reduces leakage power through the ground. This technique is implemented using sleep transistor added between ground rail and actual ground. Here a single bit 8 Transistor full adder is proposed. We will perform analysis and simulation of various parameters like power, delay and ground bounce noise using tanner EDA tool 180nm CMOS Technology. Index terms- Full adder, Ground bounce noise, PTL, Sleep transistor 1. INTRODUCTION With the extensive development of electronic devices, the low power VLSI system is most important. The single bit full adder is used in various arithmetic operations, digital signal processing and micro controller. The area of full adder is the major concern for area reduction. The current 50-60 % affects the performance of system [1-2]. The full adder is designed with increased transistor count which is used in multiplexer, compressor and parity checker [3-5]. The ground bounce noise disturb the performance of device. The scope of paper is to implement full adder to reduce the power and delay [6-7]. To achieve reduced the ground bounce noise, forward body bias with multiple thresholds is introduced to add additional wait mode which separate the sleep and active mode [8]. The ground bounce noise and leakage current during mode transistor cause performance reduction. To overcome this stacking power gating technique is introduced [9]. The Nano CMOS technology is implemented for full adder but the area requirement is high compared to our paper [10]. The degenerate pass transistor logic is developed for low power requirement of full adder. But the threshold voltage loss problem occurred [11]. One of the most important techniques is MTCMOS also known as power gating technique which is used for reduce the leakage power and leakage current in an idle mode and to improve the performance of device in active mode [12-13]. The main idea behind this technique is to turn off the device in sleep mode. In our paper 8 transistor full adder is designed with power gating technique to reduce noise, delay and area. 2. 8T FULL ADDER DESIGN The full adder has been designed using various logic styles to reduce the area and power dissipation. Figure 1: 8T full adder To analyses the various parameters of adders we use the pass transistor 8T full adder as our base structure as shown in the figure 1 which have 2 xnor C B A A C Carry Sum PM1 PM2 NM1 NM2 NM3 NM4 PM3 NM5
- 2. INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 62 and one multiplexer module .The outputs are sum and carry. Adder uses pass transistor logic to reduce the stand by leakage current and area. However still the 8 Transistor full adder is suffer from ground bounce noise. TABLE 1: TRUTH TABLE OF FULL ADDER. The ground bounce noise does not the circuit operation at lower frequency. At higher frequency, the ground bounce noise affects switching behavior of design at wrong time. The ground bounce noise is reduced with Forward Body bias MTCMOS technique which also reduce stand by leakage current and power. The reduced ground bounce noise 8T full adder is shown in figure (2) & (3). In this paper forward body bias MTCMOS technique in figure (2) where NM6, NM7 and PM4 have high threshold voltage in order to reduce the leakage power. In this technique stack transistor (NM6 & NM7) reduce the standby current in idle mode and an additional wait mode is added between sleep and active mode to discharge the virtual ground voltage during mode transition. The activation of transistor NM7 is delayed by T when wait to active mode transition takes place. To control the drain current to NM5 in mode transition the capacitor C is used. V bias voltage has been applied to PM4 so it reduced threshold voltage of wait transistor and discharges the ground voltage during sleep to wait mode transition. Our main thought is to turn of the full adder in sleep mode and provides the reduced leakage power with improved performance. In 8T full adder sum is generated, the sum output is generated by 2 xnor gate and the carry output is generated by multiplexer. When the output of first stage xnor gate is 0, then the carry output is equal to “C”. When the output of first stage xnor is 1 the carry out is equal to input “A”. The equation full adder is Sum = (A XNOR B XNOR C) Carry = (A XNOR B) * A + (A XOR B) * C 3. STACKING EFFECT Sub threshold current depends exponentially on VT, VDS and VGS. Therefore it is a function of the terminal voltages Vd, Vb, Vs and Vg. This means that to know sub threshold leakage of a device the biasing condition should be known or by controlling the terminal voltages the sub threshold leakage can be controlled. Input pattern of each gate affects the sub threshold as well as gate leakage current.. Source biasing is the general term for several techniques that change the voltage at the source of transistor. The goal is to reduce VGS, which has the effect of exponentially reducing the sub threshold current. Fig 2: 8T Full Adder with stacking power Another result of raising the source is that it also reduces Vbs, resulting in a slightly higher threshold voltage due to the body effect. Circuits that directly operate the source voltage are infrequent, and those that exist usually use switched source impedance or a self-reversed biasing technique. Probably the simplest example of source biasing occurs when “off” transistors are stacked in series connection. Theoretically, the source voltage of the upper A B C SUM CARRY 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1
- 3. INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 63 transistor will be a little higher than the source voltage of the lower transistors in the stack. 4. GROUND BOUNCE NOISE During the active mode of the circuit an instant current pass from sleep transistor, causes a sudden rush of the current. Because of self-inductance of the off- chip bonding wires and parasitic inductance on chip power rails, resulting voltage function in the circuit depends on input / output buffers and internal circuitry. The noise depends on the voltage. The ground bounce noise model. Fig3: 8T Full Adder with Stacking power gating and ground bounce noise 5. PERFORMANCE ANALYSIS AND SIMULATION RESULTS In this section, we have performed simulation of our base structure 8T and modified 8T full adder on tanner EDA simulator at 0.18µm CMOS technology. The output wave form have A,B,C WAIT and SELECT inputs and SUM, CARRY outputs of full adder which is given below. Fig 4: Simulation output of 8T Full Adder The average power and delay of various full adders is given below. The power and delay are perfectly reduced in full adder. TABLE 2: DELAY AND POWER COMPARISON OF 8T FULL ADDER Interconnection circuit Average power (pW) Total delay (nS) 14T full adder 21.03 80 10T Full Adder 2.0 40 10T full adder with power gating technique 0.81 30 8T Full Adder with power gating technique 0.007 0.98 The ground bounce noise of various full adders is summarized below. From that we know our best performance compared with other full adder.
- 4. INTERNATIONAL JOURNAL FOR TRENDS IN ENGINEERING & TECHNOLOGY VOLUME 5 ISSUE 1 – MAY 2015 - ISSN: 2349 - 9303 64 TABLE 3: GROUND BOUNCE NOISE Interconnection circuit Ground bounce noise (nV) 14T Full Adder 4.0834 10T Full Adder 2.6308 10T Full Adder with Power Gating Technique 2.5354 8T Full Adder with Power Gating Technique 0.987 6. CONCLUSION The proposed 8T Full adder is designed in Tanner EDA toll version 13.0. The performance of full adder is best compared to others. The 8T full adder performance is examined to have a better delay, power and ground bounce noise. It gives reduction in power, ground bounce noise and delay than existing full adder. REFERENCES [1] R.Singh S.akashe “design and analysis of low stand by leakage current and reduced ground bounce noise of static 10T cmos full adder”vol 7 no 2 june 2014, african Journal of Computing & ICT [2] S.G.Nagendra and A.Chandkasam,”Leakage in Nanometer CMOS Technologies, New York : Springer-verilog , 2006 [3] M. Hossseinghadiery H. Mohammadi, nadasenejani “two low power high Performance FullAdders with Minimum Gates,” International Journal of Electrical and Computer Engineering 10 2009. [4] Radu Zlatanovici, Sean Kao, Borivoje Nikolic, “Energy-Delay of Optimization 64-Bit Carry- Lookahead Adders With a 240ps 90nm CMOS Design Example,” IEEE J. Solid State circuits, vol.44, no. 2, pp. 569-583, Feb. 2009. [5] K.Navi, O. Kavehei, M. Rouholamini, A. Sahafi, S. Mehrabi, N. Dadkhai, “Low-Power and High- Performance 1-bit CMOS Full Adder Cell,” Journal of Computers, Academy Press, vol. 3, no. 2, Feb. 2008. [6] Pren R. Zimmermann, W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid- State Circuits, vol. 32, pp. 1079– 1090, July 1997. [7] Tripti Sharma, K.G.Sharma, Prof.B.P.Singh, “High Performance Full Adder : Cell:Comparative Analysis”, Proceedings of 2010 IEEE Students’ Technology Symposium, IIT Kharagpur, 3-4 April 2010. [8] Shashikant Sharma, Anjan Kumar, Manisha Pattanaik, and Balwinder Raj, “Forward Body Biased Multimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders”, International Journal of Information and Electronics Engineering, Vol. 3, No. 6, November 2013. [9] R. Bhanuprakash, Manisha Pattanaik and S. S. Rajput, “ Analysis and Reduction of Ground Bounce Noise and Leakage Current During Mode Transition of Stacking Power Gating Logic Circuits ”,IEEE Region 10 Conference TENCON 2009, pp. 1-6. [10] Manisha Pattanaik, Muddala V. D. L. Varaprasad and Fazal Rahim Khan “ Ground Bounce Noise Reduction of Low Leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile Applications”, International Conference on Electronic Devices, Systems and Applications (ICEDSA) 2010, pp. 31- 36. [11] Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu,” Low Power 10-Transistor Full Adder Design Based on Degenerate Pass Transistor Logic, IEEE. 2012. [12] Y.Chang, S.k. Gupta, and M. A. Breuer,” analysis of Ground Bounce in Deep Sub-micron Circuit, Procceding15th IEEE VLSI Test Symposium,”1999, pp.110-116 . [13] V. Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J. Brown, “Enhanced multi- threshold (MTCMOS) circuits using variable bias,” in Proceedings of International Symposium on Low- Power Electronics and Design, pp. 165-169, Aug. 2001.