Digital Integrated Circuit A Design Perspective

© Digital Integrated Circuits2nd Memories
Digital Integrated
Digital Integrated
Circuits
Circuits
A Design Perspective
A Design Perspective
Semiconductor
Semiconductor
Memories
Memories
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
December 20, 2002

Chapter Overview
Chapter Overview
 Memory Classification
 Memory Architectures
 The Memory Core
 Periphery
 Reliability
 Case Studies

Semiconductor Memory Classification
Semiconductor Memory Classification
Read-Write Memory
Non-Volatile
Read-Write
Memory
Read-Only Memory
EPROM
E
2
PROM
FLASH
Random
Access
Non-Random
Access
SRAM
DRAM
Mask-Programmed
Programmable (PROM)
FIFO
Shift Register
CAM
LIFO

Memory Timing: Definitions
Memory Timing: Definitions
Write cycle
Read access Read access
Read cycle
Write access
Data written
Data valid
DATA
WRITE
READ

Memory Architecture: Decoders
Memory Architecture: Decoders
Word 0
Word 1
Word 2
WordN 22
WordN 21
Storage
cell
M bits M bits
S0
S1
S2
SN 22
A0
A1
A K 21
K 5 log2N
SN 21
Word 0
Word 1
Word 2
WordN 22
WordN 21
Storage
cell
S0
Input-Output
(M bits)
Intuitive architecture for N x M memory
Too many select signals:
N words == N select signals
K = log2N
Decoder reduces the number of select signals
Input-Output
(M bits)

Row
Decoder
Bit line
2L 2 K
Word line
A K
A K 1 1
A L 2 1
A 0
M.2K
A K 2 1
Sense amplifiers / Drivers
Column decoder
Input-Output
(M bits)
Array-Structured Memory Architecture
Array-Structured Memory Architecture
Problem: ASPECT RATIO or HEIGHT >> WIDTH
Amplify swing to
rail-to-rail amplitude
Selects appropriate
word

Hierarchical Memory Architecture
Hierarchical Memory Architecture
Advantages:
Advantages:
1. Shorter wires within blocks
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
2. Block address activates only 1 block => power savings
Global
amplifier/driver
Control
circuitry
Global data bus
Block selector
Block 0
Row
address
Column
address
Block
address
Block i Block P 2 1
I/O

Block Diagram of 4 Mbit SRAM
Block Diagram of 4 Mbit SRAM
Clock
generator
CS, WE
buffer
I/O
buffer
Y-address
buffer
X-address
buffer
x1/x4
controller
Z-address
buffer
X-address
buffer
Predecoder and block selector
Bit line load
Transfer gate
Column decoder
Sense amplifier and write driver
[Hirose90]

Contents-Addressable Memory
Contents-Addressable Memory
Address
Decoder
Data (64 bits)
I/O
Buffers
Comparand
CAM Array
2
9
words3 64 bits
Mask
Control Logic R/W Address (9 bits)
Commands
2
9
Validity
Bits
Priority
Encoder

Memory Timing: Approaches
Memory Timing: Approaches
DRAM Timing
Multiplexed Adressing
SRAM Timing
Self-timed
Address
bus
RAS
RAS -CAS timing
Row Address
Address
Bus
Address transition
initiates memory operation
Address
Column Address
CAS

Read-Only Memory Cells
Read-Only Memory Cells
WL
BL
WL
BL
1
WL
BL
WL
BL
WL
BL
0
VDD
WL
BL
GND
Diode ROM MOS ROM 1 MOS ROM 2

MOS OR ROM
MOS OR ROM
WL[0]
VDD
BL[0]
WL[1]
WL[2]
WL[3]
Vbias
BL[1]
Pull-down loads
BL[2] BL[3]
VDD

MOS NOR ROM
MOS NOR ROM
WL[0]
GND
BL [0]
WL [1]
WL [2]
WL [3]
VDD
BL [1]
Pull-up devices
BL [2] BL [3]
GND

MOS NOR ROM Layout
MOS NOR ROM Layout
Programmming using the
Active Layer Only
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (9.5 x 7)

MOS NOR ROM Layout
MOS NOR ROM Layout
Polysilicon
Metal1
Diffusion
Metal1 on Diffusion
Cell (11 x 7)
Programmming using
the Contact Layer Only

MOS NAND ROM
MOS NAND ROM
All word lines high by default with exception of selected row
WL[0]
WL[1]
WL[2]
WL[3]
VDD
Pull-up devices
BL[3]
BL[2]
BL[1]
BL[0]

MOS NAND ROM Layout
MOS NAND ROM Layout
No contact to VDD or GND necessary;
Loss in performance compared to NOR ROM
drastically reduced cell size
Polysilicon
Diffusion
Metal1 on Diffusion
Cell (8 x 7)
Programmming using
the Metal-1 Layer Only

NAND ROM Layout
NAND ROM Layout
Cell (5 x 6)
Polysilicon
Threshold-altering
implant
Metal1 on Diffusion
Programmming using
Implants Only

Equivalent Transient Model for MOS NOR ROM
Equivalent Transient Model for MOS NOR ROM
 Word line parasitics
 Wire capacitance and gate capacitance
 Wire resistance (polysilicon)
 Bit line parasitics
 Resistance not dominant (metal)
 Drain and Gate-Drain capacitance
Model for NOR ROM VDD
Cbit
rword
cword
WL
BL

Equivalent Transient Model for MOS NAND ROM
Equivalent Transient Model for MOS NAND ROM
 Word line parasitics
 Similar to NOR ROM
 Bit line parasitics
 Resistance of cascaded transistors dominates
 Drain/Source and complete gate capacitance
Model for NAND ROM
VDD
CL
rword
cword
cbit
rbit
WL
BL

Decreasing Word Line Delay
Decreasing Word Line Delay
Metal bypass
Polysilicon word line
K cells
Polysilicon word line
WL
Driver
(b) Using a metal bypass
(a) Driving the word line from both sides
Metal word line
WL
(c) Use silicides

Precharged MOS NOR ROM
Precharged MOS NOR ROM
PMOS precharge device can be made as large as necessary,
but clock driver becomes harder to design.
WL[0]
GND
BL[0]
WL[1]
WL[2]
WL[3]
VDD
BL[1]
Precharge devices
BL[2] BL[3]
GND
pre
f

Non-Volatile Memories
Non-Volatile Memories
The Floating-gate transistor (FAMOS)
The Floating-gate transistor (FAMOS)
Floating gate
Source
Substrate
Gate
Drain
n+ n+_
p
tox
tox
Device cross-section Schematic symbol
G
S
D

Floating-Gate Transistor Programming
Floating-Gate Transistor Programming
0 V
2 5 V 0 V
D
S
Removing programming
voltage leaves charge trapped
5 V
22.5 V 5 V
D
S
Programming results in
higher VT.
20 V
10 V 5 V 20 V
D
S
Avalanche injection

A “Programmable-Threshold” Transistor
A “Programmable-Threshold” Transistor
“0”-state “1”-state
DV T
V WL V GS
“ON”
“OFF ”

FLOTOX EEPROM
FLOTOX EEPROM
Floating gate
Source
Substrate
p
Gate
Drain
n1 n1
FLOTOX transistor
Fowler-Nordheim
I-V characteristic
20–30 nm
10 nm
-10 V
10 V
I
VGD

EEPROM Cell
EEPROM Cell
WL
BL
VDD
Absolute threshold control
is hard
Unprogrammed transistor
might be depletion
 2 transistor cell

Flash EEPROM
Flash EEPROM
Control gate
erasure
p-
substrate
Floating gate
Thin tunneling oxide
n1 source n1 drain
programming
Many other options …

Cross-sections of NVM cells
Cross-sections of NVM cells
EPROM
Flash
Courtesy Intel

Basic Operations in a NOR Flash Memory―
Erase
Erase
S D
12 V
G
cell array
BL 0 BL 1
open open
WL 0
WL 1
0 V
0 V

Write
Write
S D
12 V
6 V
G
BL 0 BL 1
6 V 0 V
WL 0
WL 1
12 V
0 V

Read
Read
5 V
1 V
G
S D
BL 0 BL 1
1 V 0 V
WL 0
WL 1
5 V
0 V

NAND Flash Memory
NAND Flash Memory
Unit Cell
Word line(poly)
Source line
(Diff. Layer)
Courtesy Toshiba
Gate
ONO
FG
Gate
Oxide

NAND Flash Memory
NAND Flash Memory
Word lines
Select transistor
Bit line contact Source line contact
Active area
STI
Courtesy Toshiba

Characteristics of State-of-the-art NVM
Characteristics of State-of-the-art NVM

Read-Write Memories (RAM)
Read-Write Memories (RAM)
 STATIC (SRAM)
 DYNAMIC (DRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

6-transistor CMOS SRAM Cell
6-transistor CMOS SRAM Cell
WL
BL
VDD
M5
M6
M4
M1
M2
M3
BL
Q
Q

CMOS SRAM Analysis (Read)
WL
BL
VDD
M5
M6
M4
M1
VDD
VDD VDD
BL
Q = 1
Q = 0
Cbit Cbit

0
0
0.2
0.4
0.6
0.8
1
1.2
0.5 1 1.2 1.5 2
Cell Ratio (CR)
2.5 3
Voltage
Rise
(V)

CMOS SRAM Analysis (Write)
BL = 1 BL = 0
Q = 0
Q = 1
M1
M4
M5
M6
VDD
VDD
WL

6T-SRAM — Layout
6T-SRAM — Layout
VDD
GND
Q
Q
WL
BL
BL
M1 M3
M4
M2
M5 M6

Resistance-load SRAM Cell
Resistance-load SRAM Cell
Static power dissipation -- Want RL large
Bit lines precharged to VDD to address tp problem
M3
RL RL
VDD
WL
Q Q
M1 M2
M4
BL BL

SRAM Characteristics
SRAM Characteristics

3-Transistor DRAM Cell
No constraints on device ratios
Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTn
WWL
BL1
M1 X
M3
M2
CS
BL2
RWL
V DD
V DD 2 VT
DV
V DD 2 VT
BL2
BL1
X
RWL
WWL

3T-DRAM — Layout
3T-DRAM — Layout
BL2 BL1 GND
RWL
WWL
M3
M2
M1

Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV.
M1
CS
WL
BL
CBL
V DD 2 V T
WL
X
sensing
BL
GND
Write 1 Read 1
V DD
V DD /2 V
V BL VPRE
– VBIT VPRE
–
CS
CS CBL
+
------------
= =
V

DRAM Cell Observations
DRAM Cell Observations
 1T DRAM requires a sense amplifier for each bit line, due
to charge redistribution read-out.
 DRAM memory cells are single ended in contrast to
SRAM cells.
The read-out of the 1T DRAM cell is destructive; read
and refresh operations are necessary for correct
operation.
 Unlike 3T cell, 1T cell requires presence of an extra
capacitance that must be explicitly included in the design.
 When writing a “1” into a DRAM cell, a threshold
voltage is lost. This charge loss can be circumvented by
bootstrapping the word lines to a higher value than VDD

Sense Amp Operation
Sense Amp Operation
DV(1)
V(1)
V(0)
t
VPRE
VBL
Sense amp activated
Word line activated

1-T DRAM Cell
1-T DRAM Cell
Uses Polysilicon-Diffusion Capacitance
Expensive in Area
M1 word
line
Diffused
bit line
Polysilicon
gate
Polysilicon
plate
Capacitor
Cross-section Layout
Metal word line
Poly
SiO2
Field Oxide
n+ n+
Inversion layer
induced by
plate bias
Poly

SEM of poly-diffusion capacitor 1T-DRAM
SEM of poly-diffusion capacitor 1T-DRAM

Advanced 1T DRAM Cells
Advanced 1T DRAM Cells
Cell Plate Si
Capacitor Insulator
Storage Node Poly
2nd Field Oxide
Refilling Poly
Si Substrate
Trench Cell Stacked-capacitor Cell
Capacitor dielectric layer
Cell plate
Word line
Insulating Layer
Isolation
Transfer gate
Storage electrode

Static CAM Memory Cell
Static CAM Memory Cell
CAM
Bit
Word
Bit
••• CAM
Bit Bit
CAM
Word
Wired-NOR Match Line
Match
M1
M2
M7
M6
M4 M5
M8 M9
M3
int
S
Word
••• CAM
Bit Bit
S

CAM in Cache Memory
CAM in Cache Memory
CAM
ARRAY
Input Drivers
Tag Hit
Address
SRAM
ARRAY
Sense Amps / Input Drivers
Data
R/W

Periphery
Periphery
 Decoders
 Sense Amplifiers
 Input/Output Buffers
 Control / Timing Circuitry

Row Decoders
Row Decoders
Collection of 2M
complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder

Hierarchical Decoders
Hierarchical Decoders
• • •
• • •
A2
A2
A2A3
WL 0
A2A3
A2A3
A2A3
A3 A3
A0
A0
A0A1
A0A1
A0A1
A0A1
A1 A1
WL 1
Multi-stage implementation improves performance
NAND decoder using
NAND decoder using
2-input pre-decoders
2-input pre-decoders

Dynamic Decoders
Dynamic Decoders
Precharge devices
VDD 
GND
WL3
WL2
WL1
WL0
A0
A0
GND
A1
A1

WL3
A0
A0 A1
A1
WL 2
WL 1
WL 0
VDD
VDD
VDD
VDD
2-input NOR decoder 2-input NAND decoder

4-input pass-transistor based column
4-input pass-transistor based column
decoder
decoder
Advantages: speed (tpd does not add to overall memory access time)
Only one extra transistor in signal path
Disadvantage: Large transistor count
A0
S0
BL 0 BL 1 BL 2 BL 3
A1
S1
S2
S3
D

4-to-1 tree based column decoder
4-to-1 tree based column decoder
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
buffers
progressive sizing
combination of tree and pass transistor approaches
Solutions:
BL 0 BL 1 BL 2 BL 3
D
A0
A0
A1
A1

Decoder for circular shift-register
Decoder for circular shift-register
V DD
V DD
R
WL 0
V DD
f
f
f
f
V DD
R
WL 1
V DD
f
f
f
f
V DD
R
WL 2
V DD
f
f
f
f
• • •

Sense Amplifiers
Sense Amplifiers
tp
C V

Iav
----------------
=
make V as small
as possible
small
large
Idea: Use Sense Amplifer
output
input
s.a.
small
transition

Differential Sense Amplifier
Differential Sense Amplifier
Directly applicable to
SRAMs
M4
M1
M5
M3
M2
V DD
bit
bit
SE
Out
y

Differential Sensing ― SRAM
Differential Sensing ― SRAM
V DD
V DD
V DD
V DD
BL
EQ
Diff.
Sense
Amp
(a) SRAM sensing scheme (b) two stage differential amplifier
SRAM cell i
WL i
2
x
x
V DD
Output
BL
PC
M3
M1
M5
M2
M4
x
SE
SE
SE
Output
SE
x
2
x 2
x

Latch-Based Sense Amplifier (DRAM)
Latch-Based Sense Amplifier (DRAM)
Initialized in its meta-stable point with EQ
Once adequate voltage gap created, sense amp enabled with SE
Positive feedback quickly forces output to a stable operating point.
EQ
VDD
BL BL
SE
SE

Charge-Redistribution Amplifier
Charge-Redistribution Amplifier
0.5
1.0
1.5
2.0
2.5
0.0
0.0 1.00 2.00
time(nsec)
V
V in
V ref 5 3V
V L
V S
(b) Transient response
3.00
Concept
M2 M3
M1
V L VS
Vref
Csmall
Clarge
Transient Response

Charge-Redistribution Amplifier―
Charge-Redistribution Amplifier―
EPROM
EPROM
SE
VDD
WLC
Load
Cascode
device
Column
decoder
EPROM
array
BL
WL
Vcasc
Out
Cout
Ccol
CBL
M1
M2
M3
M4

Single-to-Differential Conversion
Single-to-Differential Conversion
How to make a good Vref?
Diff.
S.A.
Cell
2
x
x
Output
WL
V ref
BL
1
2

Open bitline architecture with
Open bitline architecture with
dummy cells
dummy cells
CS CS CS CS
BLL
L L1 L0 R0
CS
R1
CS
L
… …
BLR
V DD
SE
SE
EQ
Dummy cell Dummy cell

DRAM Read Process with Dummy Cell
DRAM Read Process with Dummy Cell
3
2
1
0
0 1 2 3
BL
BL
t (ns)
reading 0
3
2
1
0
0 1 2 3
SE
EQ WL
t (ns)
control signals
3
2
1
0
0 1 2 3
BL
BL
t (ns)
reading 1

Voltage Regulator
Voltage Regulator
-
+
VDD
VREF
Vbias
Mdrive
Mdrive
VDL
VDL
VREF
Equivalent Model

Charge Pump
Charge Pump
CLK
V DD
A B
M1
M2
V load
Cload
Cpump
2V DD 2 V T
V DD 2 V T
0 V
V B
V load
0 V

DRAM Timing
DRAM Timing

RDRAM Architecture
RDRAM Architecture
memory
array
Data
bus
Clocks
Column
Row
demux packet dec.
packet dec.
Bus
k
k 3l
demux

Address Transition Detection
Address Transition Detection
DELAY
td
A0
DELAY
td
A1
DELAY
td
AN2 1
VDD
ATD ATD
…

Reliability and Yield
Reliability and Yield

Sensing Parameters in DRAM
Sensing Parameters in DRAM
From [Itoh01]
4K
10
100
1000
64K 1M 16M 256M 4G 64G
Memory Capacity (bits/chip)
CD (1F)
CS(1F)
QS(1C)
Vsmax(mv)
V DD (V)
QS 5 CS V DD /2
Vsmax 5 QS/(CS 1 CD)

Noise Sources in 1T DRam
Noise Sources in 1T DRam
Ccross
electrode
a-particles
leakage
CS
WL
BL substrate Adjacent BL
CWBL

Open Bit-line Architecture —Cross Coupling
Open Bit-line Architecture —Cross Coupling
Sense
Amplifier
C
WL1
BL
C BL
C WBL C WBL
C
C
WL0
C
C BL
C C
WL D WL D WL0 WL1
BL
EQ

Folded-Bitline Architecture
Folded-Bitline Architecture
Sense
Amplifier
C
WL 1
CWBL
CWBL
C
WL 0 WL 0 WL D
C
C
WL 1
C
C
WL D
BL CBL
BL CBL
EQ
x
x
y

Transposed-Bitline Architecture
Transposed-Bitline Architecture
SA
Ccross
(a) Straightforward bit-line routing
(b) Transposed bit-line architecture
BL 9
BL
BL
BL 99
SA
Ccross
BL 9
BL
BL
BL 99

Alpha-particles (or Neutrons)
Alpha-particles (or Neutrons)
1 Particle ~ 1 Million Carriers
WL
BL
V DD
n1
a-particle
SiO2
1
1
1
1
1
1
2
2
2
2
2
2

Yield
Yield
Yield curves at different stages of process maturity
(from [Veendrick92])

Redundancy
Redundancy
Memory
Array
Column Decoder
Redundant
rows
Redundant
columns
Row
Address
Column
Address
Fuse
Bank
:

Error-Correcting Codes
Error-Correcting Codes
Example: Hamming Codes
with
e.g. B3 Wrong
1
1
0
= 3

Redundancy and Error Correction
Redundancy and Error Correction

Sources of Power Dissipation in
Sources of Power Dissipation in
Memories
Memories
PERIPHERY
ROW
DEC
selected
non-selected
CHIP
COLUMN DEC
nCDE V INTf
mCDE V INTf
CPT V INTf
IDCP
ARRAY
m
n
m(n2 1)ihld
miact
V DD
VSS
IDD 5 SCiDVif 1S IDCP
From [Itoh00]

Data Retention in SRAM
Data Retention in SRAM
1.30u
1.10u
900n
700n
500n
300n
100n
0.00 .600 1.20 1.80
Factor 7
0.13 m CMOS
m
0.18 m CMOS
m
VDD
I
leakage
SRAM leakage increases with technology scaling

Suppressing Leakage in SRAM
Suppressing Leakage in SRAM
SRAM
cell
SRAM
cell
SRAM
cell
VDD,int
VDD
VDD VDDL
VSS,int
sleep
sleep
SRAM
cell
SRAM
cell
SRAM
cell
VDD,int
sleep
low-threshold transistor
Reducing the supply voltage
Reducing the supply voltage
Inserting Extra Resistance
Inserting Extra Resistance

Data Retention in DRAM
Data Retention in DRAM
10
1
100
102 1
10
2 2
102 3
102 4
10
2 5
10
2 6
15M 64M 255M 1G 4G 15G 64G
Capacity (bit)
Current
(A)
3.3 2.5 2.0 1.5 1.2 1.0 0.8
Operating voltage (V)
0.53 0.40 0.32 0.24 0.19 0.16 0.13
Extrapolated threshold voltage at 25 C (V)
IACT
IAC
IDC
Cycle time : 150 ns
T 5 75 C, S
From [Itoh00]

Case Studies
Case Studies
 Programmable Logic Array
 SRAM
 Flash Memory

PLA versus ROM
PLA versus ROM
 Programmable Logic Array
structured approach to random logic
“two level logic implementation”
NOR-NOR (product of sums)
NAND-NAND (sum of products)
IDENTICAL TO ROM!
 Main difference
ROM: fully populated
PLA: one element per minterm
Note: Importance of PLA’s has drastically reduced
1. slow
2. better software techniques (mutli-level logic
synthesis)
But …

Programmable Logic Array
Programmable Logic Array
GND GND GND GND
GND
GND
GND
V DD
V DD
X0
X0 X1 f0 f1
X1 X2
X2
AND-plane OR-plane
Pseudo-NMOS PLA

Dynamic PLA
Dynamic PLA
GND
GND
V DD
V DD
X0
X0 X1 f0 f1
X1 X2
X2
AND
f
AND
f
OR
f
OR
f
AND-plane OR-plane

Clock Signal Generation
Clock Signal Generation
for self-timed dynamic PLA
for self-timed dynamic PLA
f
tpre teval
f AND
f
f AND
f AND
f OR
f OR
(a) Clock signals (b) Timing generation circuitry
Dummy AND row
Dummy AND row

PLA Layout
PLA Layout
VDD GND

And-Plane Or-Plane
f0 f1
x0 x0 x1 x1 x2 x2
Pull-up devices Pull-up devices

4 Mbit SRAM
4 Mbit SRAM
Hierarchical Word-line Architecture
Hierarchical Word-line Architecture
Global word line
Sub-global word line
Block group
select
Block
select
Block
select
Memory cell
Local
word line
Block 0
•••
Local
word line
Block 1
•••
Block 2...
•••

Bit-line Circuitry
Bit-line Circuitry
Bit-line
load
Block
select ATD
BEQ
Local WL
Memory cell
I/O line
I/O
B/T
CD
Sense amplifier
CD CD
I/O
B/T

Sense Amplifier (and Waveforms)
Sense Amplifier (and Waveforms)
BS
I/O I/O
DATA
Block
select ATD
BS
SA SA
BS
SEQ
SEQ
SEQ
SEQ
SEQ
Dei
I/O Lines
Address
Data-cut
ATD
BEQ
SEQ
DATA
Vdd
GND
SA, SA
Vdd
GND

1 Gbit Flash Memory
1 Gbit Flash Memory
Sense Latches
(10241 32) 3 8
Data Caches
(10241 32) 3 8
Sense Latches
(1024 1 32) 3 8
Data Caches
(1024 1 32) 3 8
Word
Line
Driver
Word
Line
Driver
Word
Line
Driver
Word
Line
Driver
512Mb Memory Array 512Mb Memory Array
BL0 BL1 ····· BL16895 BL16996 BL16897··· BL33791
SGD
WL31
WL0
SGS
Block0
BLT0
Block1023
Block0
Block1023
Bit Line Control Circuit
BLT1
I/O
From [Nakamura02]

Writing Flash Memory
Writing Flash Memory
Number
of
memory
cells
0V 1V 2V
Vt of memory cells
Verify level 5 0.8 V Word-line level5 4.5 V
(a)
3V 4V
Result of 4 times
program
100
0V 1V 2V
Vt of memory cells
3V 4V
102
104
106
108
Evolution of thresholds Final Distribution
From [Nakamura02]

125
125mm
mm2
2
1Gbit NAND Flash Memory
10.7mm
11.7mm
2kB
Page
buffer
&
cache
Charge
pump
16896 bit lines
32 word lines
x 1024 blocks
From [Nakamura02]

125
125mm
mm2
2
 Technology 0.13m p-sub CMOS triple-well
1poly, 1polycide, 1W, 2Al
 Cell size 0.077m2
 Chip size 125.2mm2
 Organization 2112 x 8b x 64 page x 1k block
 Power supply 2.7V-3.6V
 Cycle time 50ns
 Read time 25s
 Program time 200s / page
 Erase time 2ms / block
From [Nakamura02]

Semiconductor Memory Trends
(up to the 90’s)
(up to the 90’s)
Memory Size as a function of time: x 4 every three years

(updated)
(updated)
From [Itoh01]

Trends in Memory Cell Area
Trends in Memory Cell Area
From [Itoh01]

Technology feature size for different SRAM generations

Digital Integrated Circuit A Design Perspective

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