lect13.ppt
- 1. Introduction to CMOS VLSI Design Lecture 13: SRAM David Harris Harvey Mudd College Spring 2004
- 2. CMOS VLSI Design 13: SRAM Slide 2 Outline Memory Arrays SRAM Architecture – SRAM Cell – Decoders – Column Circuitry – Multiple Ports Serial Access Memories
- 3. CMOS VLSI Design 13: SRAM Slide 3 Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Static RAM (SRAM) Dynamic RAM (DRAM) Shift Registers Queues First In First Out (FIFO) Last In First Out (LIFO) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM
- 4. CMOS VLSI Design 13: SRAM Slide 4 Array Architecture 2n words of 2m bits each If n >> m, fold by 2k into fewer rows of more columns Good regularity – easy to design Very high density if good cells are used row decoder column decoder n n-k k 2m bits column circuitry bitline conditioning memory cells: 2n-k rows x 2m+k columns bitlines wordlines
- 5. CMOS VLSI Design 13: SRAM Slide 5 12T SRAM Cell Basic building block: SRAM Cell – Holds one bit of information, like a latch – Must be read and written 12-transistor (12T) SRAM cell – Use a simple latch connected to bitline – 46 x 75 l unit cell bit write write_b read read_b
- 6. CMOS VLSI Design 13: SRAM Slide 6 6T SRAM Cell Cell size accounts for most of array size – Reduce cell size at expense of complexity 6T SRAM Cell – Used in most commercial chips – Data stored in cross-coupled inverters Read: – Precharge bit, bit_b – Raise wordline Write: – Drive data onto bit, bit_b – Raise wordline bit bit_b word
- 7. CMOS VLSI Design 13: SRAM Slide 7 SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 – bit discharges, bit_b stays high – But A bumps up slightly Read stability – A must not flip bit bit_b N1 N2 P1 A P2 N3 N4 A_b word 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 time (ps) word bit A A_b bit_b
- 8. CMOS VLSI Design 13: SRAM Slide 8 SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 – bit discharges, bit_b stays high – But A bumps up slightly Read stability – A must not flip – N1 >> N2 bit bit_b N1 N2 P1 A P2 N3 N4 A_b word 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 time (ps) word bit A A_b bit_b
- 9. CMOS VLSI Design 13: SRAM Slide 9 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 – Force A_b low, then A rises high Writability – Must overpower feedback inverter time (ps) word A A_b bit_b 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 700 bit bit_b N1 N2 P1 A P2 N3 N4 A_b word
- 10. CMOS VLSI Design 13: SRAM Slide 10 SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 – Force A_b low, then A rises high Writability – Must overpower feedback inverter – N2 >> P1 time (ps) word A A_b bit_b 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 700 bit bit_b N1 N2 P1 A P2 N3 N4 A_b word
- 11. CMOS VLSI Design 13: SRAM Slide 11 SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b med A weak strong med A_b word
- 12. CMOS VLSI Design 13: SRAM Slide 12 SRAM Column Example Read Write H H SRAM Cell word_q1 bit_v1f bit_b_v1f out_v1r out_b_v1r 1 2 word_q1 bit_v1f out_v1r 2 More Cells Bitline Conditioning 2 More Cells SRAM Cell word_q1 bit_v1f bit_b_v1f data_s1 write_q1 Bitline Conditioning
- 13. CMOS VLSI Design 13: SRAM Slide 13 SRAM Layout Cell size is critical: 26 x 45 l (even smaller in industry) Tile cells sharing VDD, GND, bitline contacts VDD GND GND BIT BIT_B WORD Cell boundary
- 14. CMOS VLSI Design 13: SRAM Slide 14 Decoders n:2n decoder consists of 2n n-input AND gates – One needed for each row of memory – Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS word0 word1 word2 word3 A0 A1 A1 word A0 1 1 1/2 2 4 8 16 word A0 A1 1 1 1 1 4 8 word0 word1 word2 word3 A0 A1
- 15. CMOS VLSI Design 13: SRAM Slide 15 Decoder Layout Decoders must be pitch-matched to SRAM cell – Requires very skinny gates GND VDD word buffer inverter NAND gate A0 A0 A1 A2 A3 A2 A3 A1
- 16. CMOS VLSI Design 13: SRAM Slide 16 Large Decoders For n > 4, NAND gates become slow – Break large gates into multiple smaller gates word0 word1 word2 word3 word15 A0 A1 A2 A3
- 17. CMOS VLSI Design 13: SRAM Slide 17 Predecoding Many of these gates are redundant – Factor out common gates into predecoder – Saves area – Same path effort A0 A1 A2 A3 word1 word2 word3 word15 word0 1 of 4 hot predecoded lines predecoders
- 18. CMOS VLSI Design 13: SRAM Slide 18 Column Circuitry Some circuitry is required for each column – Bitline conditioning – Sense amplifiers – Column multiplexing
- 19. CMOS VLSI Design 13: SRAM Slide 19 Bitline Conditioning Precharge bitlines high before reads Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b bit bit_b
- 20. CMOS VLSI Design 13: SRAM Slide 20 Sense Amplifiers Bitlines have many cells attached – Ex: 32-kbit SRAM has 256 rows x 128 cols – 128 cells on each bitline tpd (C/I) DV – Even with shared diffusion contacts, 64C of diffusion capacitance (big C) – Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce DV)
- 21. CMOS VLSI Design 13: SRAM Slide 21 Differential Pair Amp Differential pair requires no clock But always dissipates static power bit bit_b sense_b sense N1 N2 N3 P1 P2
- 22. CMOS VLSI Design 13: SRAM Slide 22 Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit_b bit sense sense_b sense_clk isolation transistors regenerative feedback
- 23. CMOS VLSI Design 13: SRAM Slide 23 Twisted Bitlines Sense amplifiers also amplify noise – Coupling noise is severe in modern processes – Try to couple equally onto bit and bit_b – Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b
- 24. CMOS VLSI Design 13: SRAM Slide 24 Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns – Must select 16 output bits from the 128 columns – Requires 16 8:1 column multiplexers
- 25. CMOS VLSI Design 13: SRAM Slide 25 Tree Decoder Mux Column mux can use pass transistors – Use nMOS only, precharge outputs One design is to use k series transistors for 2k:1 mux – No external decoder logic needed B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A0 A1 A1 A2 A2 Y Y to sense amps and write circuits
- 26. CMOS VLSI Design 13: SRAM Slide 26 Single Pass-Gate Mux Or eliminate series transistors with separate decoder A0 A1 B0 B1 B2 B3 Y
- 27. CMOS VLSI Design 13: SRAM Slide 27 Ex: 2-way Muxed SRAM More Cells word_q1 write0_q1 2 More Cells A0 A0 2 data_v1 write1_q1
- 28. CMOS VLSI Design 13: SRAM Slide 28 Multiple Ports We have considered single-ported SRAM – One read or one write on each cycle Multiported SRAM are needed for register files Examples: – Multicycle MIPS must read two sources or write a result on some cycles – Pipelined MIPS must read two sources and write a third result each cycle – Superscalar MIPS must read and write many sources and results each cycle
- 29. CMOS VLSI Design 13: SRAM Slide 29 Dual-Ported SRAM Simple dual-ported SRAM – Two independent single-ended reads – Or one differential write Do two reads and one write by time multiplexing – Read during ph1, write during ph2 bit bit_b wordB wordA
- 30. CMOS VLSI Design 13: SRAM Slide 30 Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of bitlines bA wordB wordA wordD wordC wordF wordE wordG bB bC write circuits read circuits bD bE bF bG
- 31. CMOS VLSI Design 13: SRAM Slide 31 Serial Access Memories Serial access memories do not use an address – Shift Registers – Tapped Delay Lines – Serial In Parallel Out (SIPO) – Parallel In Serial Out (PISO) – Queues (FIFO, LIFO)
- 32. CMOS VLSI Design 13: SRAM Slide 32 Shift Register Shift registers store and delay data Simple design: cascade of registers – Watch your hold times! clk Din Dout 8
- 33. CMOS VLSI Design 13: SRAM Slide 33 Denser Shift Registers Flip-flops aren’t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data – Initialize read address to first entry, write to last – Increment address on each cycle Din Dout clk counter counter reset 00...00 11...11 readaddr writeaddr dual-ported SRAM
- 34. CMOS VLSI Design 13: SRAM Slide 34 Tapped Delay Line A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux – Ex: 0 – 63 stages of delay SR32 clk Din delay5 SR16 delay4 SR8 delay3 SR4 delay2 SR2 delay1 SR1 delay0 Dout
- 35. CMOS VLSI Design 13: SRAM Slide 35 Serial In Parallel Out 1-bit shift register reads in serial data – After N steps, presents N-bit parallel output clk P0 P1 P2 P3 Sin
- 36. CMOS VLSI Design 13: SRAM Slide 36 Parallel In Serial Out Load all N bits in parallel when shift = 0 – Then shift one bit out per cycle clk shift/load P0 P1 P2 P3 Sout
- 37. CMOS VLSI Design 13: SRAM Slide 37 Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) Queue WriteClk WriteData FULL ReadClk ReadData EMPTY
- 38. CMOS VLSI Design 13: SRAM Slide 38 FIFO, LIFO Queues First In First Out (FIFO) – Initialize read and write pointers to first element – Queue is EMPTY – On write, increment write pointer – If write almost catches read, Queue is FULL – On read, increment read pointer Last In First Out (LIFO) – Also called a stack – Use a single stack pointer for read and write