Latch and flip flop
- 1. LATCH AND FLIP FLOP By Dr. Gargi Khanna Electronics & Communication Engg. Deptt. NIT Hamirpur
- 3. Clock
- 4. How do we store info? Feedback • Two inverters can hold a bit • As long as power is applied • Storing a new memory • Temporarily break the feedback path "0" "1" "stored bit" "remember" "load" "data" "stored bit"
- 5. Chap 11 C H 5 S-R Latch • Set-reset latch • Use NOR gate to construct a stable state network
- 6. Chap 11 C H 6 S-R Latch Timing and State • S duration > delay time • S-R latch behavior • Present state • The state of Q output at the time the input signals are applied. • Next state • The state of Q output after the latch has reacted to the input signals.
- 8. Chap 11 C H 8 K-map for Q(t+) • Q+ = S + R’Q (SR=0) • S and R can not be 1 at the same time. • Q: present state • Q+: next state • Next state equation or characteristic equation.
- 9. 1 Bit Memory Element
- 10. Chap 11 C H 10 S-R Latch using NAND gates • S-R Latch, when S= 0 sets Q = 1 and R=0 resets Q = 0 S R Q Q+ 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 0 × 0 0 1 ×
- 12. E S R Qn Q n+1 0 × × × Qn 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 × 1 1 1 1 ×
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- 16. J-K FLIP-FLOP
- 20. Edge Triggered Flip Flop • Output of the F/F changes as per the input only- at pricise instant of CLOCK • Positive Edge Triggered F/F • Negative Edge Triggered F/F
- 22. Positive Edge Triggered SR Flip Flop
- 23. Waveform
- 24. SR FF
- 26. The Master–Slave J–K FLIP-FLOP M v
- 29. T-TYPE FLIP-FLOP
- 33. EDGE-TRIGGERED FLIP-FLOPs Set-up time (ts) Hold time (th) Propagation Delays Clock Pulse Width Preset and Clear Pulse Width Maximum Clock Frequency Setup time is the minimum amount of time the data input should be held steady before the clock event, so that the data is reliably sampled by the clock. Hold time is the minimum amount of time the data input should be held steady after the clock event, so that the data is reliably sampled by the clock.
- 34. Timing Information • Aperture is the sum of setup and hold time. The data input should be held steady throughout this time period. • Recovery time is the minimum amount of time the asynchronous preset or clear input should be inactive before the clock event, so that the data is reliably sampled by the clock. The recovery time for the asynchronous set or reset input is thereby similar to the setup time for the data input. • Removal time is the minimum amount of time the asynchronous Preset or Clear input should be inactive after the clock event, so that the data is reliably sampled by the clock. The removal time for the asynchronous set or reset input is thereby similar to the hold time for the data input.
- 36. EXCITATION TABLE OF FLIP-FLOP
- 37. Conversion from One Type of FLIP-FLOP to Another Type
- 38. Convert SR flip flop into JK flip Flop
- 39. Timing Parameters of TTL and CMOS FLIP-FLOPs