Lec 04 - Gate-level Minimization

Gate-Level Minimization
D.R.V.L.B Thambawita
August 27, 2017
D.R.V.L.B Thambawita Gate-Level Minimization

THE MAP METHOD
The map method is also known as the Karnaugh mapor
K-map
A K-map is a diagram made up of squares, with each square
representing one minterm of the function that is to be
minimized
The simpliﬁed expressions produced by the map are always in
one of the two standard forms:
sum of products or
product of sums

THE MAP METHOD
Figure: Two-variable K-map

THE MAP METHOD
Figure: Representation of functions in the map

THE MAP METHOD
Three-Variable K-Map
There are eight minterms for three binary variables; therefore,
the map consists of eight squares
Only one bit changes in value from one adjacent column to
the next
Figure: Three-variable K-map

THE MAP METHOD
Simplify the Boolean function
F(x, y, z) = Σ(2, 3, 4, 5)
F(x, y, z) = Σ(3, 4, 6, 7)
F(x, y, z) = Σ(0, 2, 4, 5, 6)

THE MAP METHOD
Figure: F(x, y, z) = Σ(2, 3, 4, 5) = x y + xy

THE MAP METHOD
Figure: F(x, y, z) = Σ(3, 4, 6, 7) = yz + xz

THE MAP METHOD
Figure: F(x, y, z) = Σ(0, 2, 4, 5, 6) = z + xy

THE MAP METHOD
Figure: Four-variable map

THE MAP METHOD
F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)
F = A B C + B CD + A BCD + AB C

THE MAP METHOD
Figure: F(w, x, y, z) = Σ(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y + w z + xz

THE MAP METHOD
Figure: A B C + B CD + A BCD + AB C = B D + B C + A CD

Prime Implicants
A prime implicant is a product term obtained by combining
the maximum possible number of adjacent squares in the map
If a minterm in a square is covered by only one prime
implicant, that prime implicant is said to be essential
The prime implicants of a function can be obtained from the
map by combining all possible maximum numbers of squares
Ex: F(A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

Prime Implicants
Figure: Simpliﬁcation using prime implicants

Prime Implicants
The simpliﬁed expression is obtained from the logical sum of the
two essential prime implicants and any two prime implicants that
cover minterms m3, m9, and m11.

PRODUCT-OF-SUMS SIMPLIFICATION
Simplify the Boolean function:
F(A, B, C, D) = Σ(0, 1, 2, 5, 8, 9, 10) into
1 sum-of-products form
2 product-of-sums form

PRODUCT-OF-SUMS SIMPLIFICATION
Combining the squares with 1’s gives the simpliﬁed function in
sum-of-products form:
F = B D + B C + A C D
If the squares marked with 0’s are combined, as shown in the
diagram, we obtain the simpliﬁed complemented function:
F = AB + CD + BD
Applying DeMorgan’s theorem
F=(A’ +B’) (C’ +D’) (B’ +D)

DONT-CARE CONDITIONS
Functions that have unspecified outputs for some input
combinations are called incompletely specified functions
In most applications, we simply don’t care what value is
assumed by the function for the unspecified minterms
For this reason, it is customary to call the unspecified
minterms of a function don’t-care conditions
F(w, x, y, z) = Σ(1, 3, 7, 11, 15)
Which has the dont-care conditions
d(w, x, y, z) = Σ(0, 2, 5)

DON’T-CARE CONDITIONS

NAND AND NOR IMPLEMENTATION
Digital circuits are frequently constructed with NAND or NOR
gates rather than with AND and OR gates.
NAND and NOR gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic
families
NAND Circuits
The NAND gate is said to be a universal gate because any
logic circuit can be implemented with it
A convenient way to implement a Boolean function with
NAND gates is to obtain the simpliﬁed Boolean function in
terms of Boolean operators and then convert the function to
NAND logic

Figure: Logic operations with NAND gates

Figure: Two graphic symbols for a three-input NAND gate
Implement the following Boolean function with NAND gates:
F = AB + CD

The implementation of Boolean functions with NAND gates
requires that the functions be in sum-of-products form.
Figure: Three ways to implement F = AB + CD

The procedure for obtaining the logic diagram from a Boolean
function is as follows:
1 Simplify the function and express it in sum-of-products form.
2 Draw a NAND gate for each product term of the expression
that has at least two literals. The inputs to each NAND gate
are the literals of the term. This procedure produces a group
of first-level gates.
3 Draw a single gate using the AND-invert or the invert-OR
graphic symbol in the second level, with inputs coming from
outputs of first-level gates.
4 A term with a single literal requires an inverter in the first
level. However, if the single literal is complemented, it can be
connected directly to an input of the second level NAND gate.

Multilevel NAND Circuits
F = A(CD + B) + BC
Figure:

The general procedure for converting a multilevel ANDOR diagram
into an all-NAND diagram using mixed notation is as follows:
1 Convert all AND gates to NAND gates with AND-invert
graphic symbols.
2 Convert all OR gates to NAND gates with invert-OR graphic
symbols.
3 Check all the bubbles in the diagram. For every bubble that is
not compensated by another small circle along the same line,
insert an inverter (a one-input NAND gate) or complement
the input literal.

Ex: F = (AB + A B)(C + D )

Implement the following Boolean function with NAND gates:
F(x, y, z) = (1, 2, 3, 4, 5, 7)
Figure: Solution

NOR Implementation
The NOR gate is another universal gate that can be used to
implement any Boolean function.
Figure: Logic operations with NOR gates

Two graphic symbols for the NOR gate

Lec 04 - Gate-level Minimization

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Lec 04 - Gate-level Minimization