Segmentation
          Pradyumna
Definition
• Way of offering protection to different data
  types and code.
Descriptor Tables
• Descriptor table is a array of 8k Descriptors
• 3 types
  – Global Descriptor Table (GDT)
  – Local Descriptor Table (LDT)
  – Interrupt Descriptor Table (IDT)
GDT&LDT
GDT                             LDT
• Contains Global descriptors   • Contains descriptors specific
  common to all tasks             to a particular task
• Contains al the descriptor    • Contains segment , task
  types except interrupt &        gate & call gate descriptors.
  trap descriptors
IDT
• The Interrupt Descriptor Table (IDT) is a data
  structure used to implement an interrupt
  vector table.
• The IDT is used by the processor to determine the
  correct response to interrupts & exceptions.
• Use of the IDT is triggered by three types of
  events: hardware interrupts, software
  interrupts, and processor exceptions, which
  together are referred to as "interrupts".
• The IDT consists of 256 interrupt vectors
Descriptors
• These carry all the info about a segment and its
  access rights
• These have 20 bit segment limit and 32-bit
  segment address.
• 5 types of descriptors
  –   Code or data segment Descriptors
  –   System Descriptors
  –   Local Descriptors
  –   TSS (Task State segment) Descriptors
  –   GATE Descriptors
Segment descriptor
• Segment descriptors are a part of the
  segmentation unit, used for translating
  a logical address to linear address. Segment
  descriptors describe the memory
  segment referred in the logical address
TSS
• The Task State Segment is a structure which
  holds information about a task.
• It is used by the OS kernel for task management.
• Specifically, the following information is stored in
  the TSS:
   –   Processor register state
   –   I/O Port permissions
   –   Inner level stack pointers
   –   Previous TSS link
Gate Descriptors
• Mechanism, for changing the privilege level of
  the CPU when it executes a
  predefined function callusing a CALL FAR
  instruction.
• BASE  Base Address of the         • A Accessed Bit
  segment                            • G  Granularity Bit-1=Segment
• LIMIT the length of the             Length is page
  segment                              granular,0=Segment length is byte
                                       granular
• P Present BIT-1=Present,0=Not
  Present                            • D  Default Operation Size-1=32
                                       bit segment,0=16-segment
• DPL  Descriptor Privilege Level
  0-3                                • 0  Bit must be zero for
                                       compatibility with future
• S  Segment Descriptor -             processors
  0=System Descriptor ,1=Code or
  Data Segment Descriptor            • AVL  Available field for user or
                                       OS
• TYPE  type of segment
Advantages
• memory protection added to segment table
  like paging
• sharing of memory similar to paging (but per
  area rather than per page)
Drawbacks
• Allocation algorithms as for memory partitions
• External fragmentation, back to compaction
  problem.

More Related Content

PPTX
X86 operation types
PDF
Intel x86 Architecture
PPTX
Intel x86 and ARM Data types
PDF
PAI Unit 2 Protection in 80386 segmentation
PPT
Privilege levels 80386
PDF
PAI Unit 2 Segmentation in 80386 microprocessor
PPTX
Microprocessor Protected Mode Memory addressing By DHEERAJ KATARIA
PPTX
X86 Architecture
X86 operation types
Intel x86 Architecture
Intel x86 and ARM Data types
PAI Unit 2 Protection in 80386 segmentation
Privilege levels 80386
PAI Unit 2 Segmentation in 80386 microprocessor
Microprocessor Protected Mode Memory addressing By DHEERAJ KATARIA
X86 Architecture

What's hot (19)

PPTX
Microprocessor
PPTX
Cpu registers
PDF
SE PAI Unit 2_Data Structures in 80386 segmentation
PPTX
x86 architecture
 
PPT
Advanced micro -processor
DOCX
UNIT I- CPLD & FPGA ARCHITECTURE & APPLICATIONS
PPT
Intel+80286
PPTX
The microprocessor and it's architecture
PPTX
Protection mode
PPTX
מצגת פרויקט
PPT
Microprocessor
PPTX
Introduction to 80386
PDF
introduction to computers
PDF
Ch 1 the x86 µprocessor
PDF
Advanced microprocessor
PDF
Microprocessors Assignment
PPT
Memory & I/O interfacing
Microprocessor
Cpu registers
SE PAI Unit 2_Data Structures in 80386 segmentation
x86 architecture
 
Advanced micro -processor
UNIT I- CPLD & FPGA ARCHITECTURE & APPLICATIONS
Intel+80286
The microprocessor and it's architecture
Protection mode
מצגת פרויקט
Microprocessor
Introduction to 80386
introduction to computers
Ch 1 the x86 µprocessor
Advanced microprocessor
Microprocessors Assignment
Memory & I/O interfacing
Ad

Similar to Segmentation (20)

PPTX
DOC-20230509-WA0002..pptx segment pptxe
PPTX
Segment descriptior imp engineering.pptx
PPTX
UNIT-3.pptx digital electronics system 34
PPT
Memory mgmt 80386
PPT
80286 education project compiter application .ppt
PPT
Al2ed chapter3
PDF
Multitasking.pdf good presentation education 8970
PPTX
Protected addressing mode and Paging
PDF
MP - Unit 5 (PPT) (1).pdf8br8h8rbr8hr8h9r9h
PDF
Special of 80386 registers
PDF
Unit 3 se pai_ivt and idt
PDF
PAI Unit 3 Multitasking in 80386
PPT
Al2ed chapter14
PDF
80386_AKRay.pdf study computer programme
PPTX
Pentium (80586) Microprocessor By Er. Swapnil Kaware
PPTX
Advanced Microprocessors By Er. Swapnil Kaware
PPTX
Advanced Microprocessors By Er. Swapnil Kaware
PPTX
INTERRUPT DESCRIPTOR TABLE vv& IDTR.pptx
PPTX
Intel® 80386 microprocessor registers
PPT
x86_1.ppt
DOC-20230509-WA0002..pptx segment pptxe
Segment descriptior imp engineering.pptx
UNIT-3.pptx digital electronics system 34
Memory mgmt 80386
80286 education project compiter application .ppt
Al2ed chapter3
Multitasking.pdf good presentation education 8970
Protected addressing mode and Paging
MP - Unit 5 (PPT) (1).pdf8br8h8rbr8hr8h9r9h
Special of 80386 registers
Unit 3 se pai_ivt and idt
PAI Unit 3 Multitasking in 80386
Al2ed chapter14
80386_AKRay.pdf study computer programme
Pentium (80586) Microprocessor By Er. Swapnil Kaware
Advanced Microprocessors By Er. Swapnil Kaware
Advanced Microprocessors By Er. Swapnil Kaware
INTERRUPT DESCRIPTOR TABLE vv& IDTR.pptx
Intel® 80386 microprocessor registers
x86_1.ppt
Ad

Recently uploaded (20)

PDF
Weekly quiz Compilation Jan -July 25.pdf
PPTX
ELIAS-SEZIURE AND EPilepsy semmioan session.pptx
PDF
OBE - B.A.(HON'S) IN INTERIOR ARCHITECTURE -Ar.MOHIUDDIN.pdf
PDF
LDMMIA Reiki Yoga Finals Review Spring Summer
PDF
What if we spent less time fighting change, and more time building what’s rig...
PDF
AI-driven educational solutions for real-life interventions in the Philippine...
PDF
Complications of Minimal Access-Surgery.pdf
PPTX
Virtual and Augmented Reality in Current Scenario
PPTX
Share_Module_2_Power_conflict_and_negotiation.pptx
PDF
Uderstanding digital marketing and marketing stratergie for engaging the digi...
PPTX
202450812 BayCHI UCSC-SV 20250812 v17.pptx
PPTX
Computer Architecture Input Output Memory.pptx
PPTX
A powerpoint presentation on the Revised K-10 Science Shaping Paper
PDF
1.3 FINAL REVISED K-10 PE and Health CG 2023 Grades 4-10 (1).pdf
PDF
My India Quiz Book_20210205121199924.pdf
PDF
FORM 1 BIOLOGY MIND MAPS and their schemes
PDF
BP 704 T. NOVEL DRUG DELIVERY SYSTEMS (UNIT 2).pdf
PDF
IGGE1 Understanding the Self1234567891011
PDF
HVAC Specification 2024 according to central public works department
PPTX
B.Sc. DS Unit 2 Software Engineering.pptx
Weekly quiz Compilation Jan -July 25.pdf
ELIAS-SEZIURE AND EPilepsy semmioan session.pptx
OBE - B.A.(HON'S) IN INTERIOR ARCHITECTURE -Ar.MOHIUDDIN.pdf
LDMMIA Reiki Yoga Finals Review Spring Summer
What if we spent less time fighting change, and more time building what’s rig...
AI-driven educational solutions for real-life interventions in the Philippine...
Complications of Minimal Access-Surgery.pdf
Virtual and Augmented Reality in Current Scenario
Share_Module_2_Power_conflict_and_negotiation.pptx
Uderstanding digital marketing and marketing stratergie for engaging the digi...
202450812 BayCHI UCSC-SV 20250812 v17.pptx
Computer Architecture Input Output Memory.pptx
A powerpoint presentation on the Revised K-10 Science Shaping Paper
1.3 FINAL REVISED K-10 PE and Health CG 2023 Grades 4-10 (1).pdf
My India Quiz Book_20210205121199924.pdf
FORM 1 BIOLOGY MIND MAPS and their schemes
BP 704 T. NOVEL DRUG DELIVERY SYSTEMS (UNIT 2).pdf
IGGE1 Understanding the Self1234567891011
HVAC Specification 2024 according to central public works department
B.Sc. DS Unit 2 Software Engineering.pptx

Segmentation

  • 1. Segmentation Pradyumna
  • 2. Definition • Way of offering protection to different data types and code.
  • 3. Descriptor Tables • Descriptor table is a array of 8k Descriptors • 3 types – Global Descriptor Table (GDT) – Local Descriptor Table (LDT) – Interrupt Descriptor Table (IDT)
  • 4. GDT&LDT GDT LDT • Contains Global descriptors • Contains descriptors specific common to all tasks to a particular task • Contains al the descriptor • Contains segment , task types except interrupt & gate & call gate descriptors. trap descriptors
  • 5. IDT • The Interrupt Descriptor Table (IDT) is a data structure used to implement an interrupt vector table. • The IDT is used by the processor to determine the correct response to interrupts & exceptions. • Use of the IDT is triggered by three types of events: hardware interrupts, software interrupts, and processor exceptions, which together are referred to as "interrupts". • The IDT consists of 256 interrupt vectors
  • 6. Descriptors • These carry all the info about a segment and its access rights • These have 20 bit segment limit and 32-bit segment address. • 5 types of descriptors – Code or data segment Descriptors – System Descriptors – Local Descriptors – TSS (Task State segment) Descriptors – GATE Descriptors
  • 7. Segment descriptor • Segment descriptors are a part of the segmentation unit, used for translating a logical address to linear address. Segment descriptors describe the memory segment referred in the logical address
  • 8. TSS • The Task State Segment is a structure which holds information about a task. • It is used by the OS kernel for task management. • Specifically, the following information is stored in the TSS: – Processor register state – I/O Port permissions – Inner level stack pointers – Previous TSS link
  • 9. Gate Descriptors • Mechanism, for changing the privilege level of the CPU when it executes a predefined function callusing a CALL FAR instruction.
  • 10. • BASE  Base Address of the • A Accessed Bit segment • G  Granularity Bit-1=Segment • LIMIT the length of the Length is page segment granular,0=Segment length is byte granular • P Present BIT-1=Present,0=Not Present • D  Default Operation Size-1=32 bit segment,0=16-segment • DPL  Descriptor Privilege Level 0-3 • 0  Bit must be zero for compatibility with future • S  Segment Descriptor - processors 0=System Descriptor ,1=Code or Data Segment Descriptor • AVL  Available field for user or OS • TYPE  type of segment
  • 11. Advantages • memory protection added to segment table like paging • sharing of memory similar to paging (but per area rather than per page)
  • 12. Drawbacks • Allocation algorithms as for memory partitions • External fragmentation, back to compaction problem.