Serial link interfaces, with emphasis on the challenges of future links

Serial link interfaces, with emphasis
on the challenges of future links
1
Matteo Bassi
matteo.bassi@unipv.it
Analog Integrated Circuits Lab.
University of Pavia
http://www-3.unipv.it/aic/

Matteo Bassi - Analog Integrated Circuits, University of Pavia - http://www-3.unipv.it/aic/ - Sinano Summer School 2016
Network Traffic Growth
[Cisco Visual Internet forecast]
• 2.8x traffic growth from 2014 to 2019
• Up to 3.5x in busy-hour time
• Traffic from mobile devices will exceed that from wired devices by 2019
400G: what are the challenges of the next-generation SerDes systems?

Outline
• Motivation
• Trends in the wireline world
• Desiderata and challenges for next-gen links
• Increasing Data Rate: PAM-4 vs NRZ
• High-Speed Equalization: Tunable FIR Filters for MMF
• Conclusions
= hot and promising research topic

Typical Data Center Connections
• Copper backplanes are employed for connections inside the same chassis or
among different chassis
• Optical fibers typically employed for long-reach connections between different
buildings or between floors of the same building
• Depending on speed/cost, Multi-Mode Fibers (MMF) or Single-Mode Fibers
(SMF) can be used
Inter-Chassis
Chip to chip interface e.g.
OIC CEI SR/MR IAs
Chip to chip across a Back/Midplane
interface e.g. OIF CEI MR/LR IAs
Chip to Module interface
e.g. OIF CEI VSR IAs
Input/Output to card

Typical SerDes Architecture

Trends in Wireline World
• Per-pin data rate has doubled every four
years across a variety of diverse I/O
standards
• Scaling helps but now we need more than
scaling
• Scaling factor between link power and
signaling loss is slightly less than unity
[ISSCC trends 2016]

Wish List for Next-Generation 400G
2. Improve equalizers
for longer-reach
backplanes
4. Improve boards and
package, main source of
reflections
Backplanes
Optical Fibers
3. Increase the use of
MMF, which is more cost
effective than SMF
1. Increase link speed
without compromising link
efficiency [mW/Gpbs]
5. Improve interface
from fiber to chip

Research Topics at AIC Lab @ UNIPV
Topic Paper Published
Increasing Data Rate:
from NRZ to PAM-4
modulation
• M. Bassi, F. Radice, M. Bruccoleri, S. Erba and A. Mazzanti, "A 45Gb/s PAM-4
transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS
FDSOI," ISSCC 2016
• M. Bassi, F. Radice, M. Bruccoleri, S. Erba and A. Mazzanti, "A High-Swing 45
Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS
FDSOI," IEEE Journal of Solid-State Circuits, 2016
• “A 64Gb/s PAM-4 Transmitter with 4-taps-FFE and 2.26 pJ/bit Energy Efficiency
in 28nm CMOS FDSOI”, just accepted at ISSCC 2017
Analog equalization:
Flexible Data-Rate
FIR filters for Multi-
Mode Fiber Links
• E. Mammei, F. Loi, F. Radice, A. Dati, M. Bruccoleri, M. Bassi and A. Mazzanti, "A
power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s
multi-mode fiber EDC in 28nm LP-CMOS," ISSCC 2014
• E. Mammei, F. Loi, F. Radice, A. Dati, M. Bruccoleri, M. Bassi and A. Mazzanti,
"Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10
Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS," in IEEE Journal of
Solid-State Circuits, 2014
• F. Radice, M. Bruccoleri, E. Mammei, M. Bassi and A. Mazzanti, "A low-noise
programmable-gain amplifier for 25 Gb/s multi-mode fiber receivers in 28nm
CMOS FDSOI," ESSCIRC 2015

Outline
• Motivation
• Trends in the wireline world
• Desiderata and challenges for next-gen links
• Increasing Data Rate: PAM-4 vs NRZ
• High-Speed Equalization: Tunable FIR Filters for MMF
• Conclusions

Issues with Increasing Data Rate
• Thanks to technology scaling, gate count increases, but faster than I/O
speed and available bumps
• Power dissipation, rather than technology itself or routing, mostly limits
max I/O density
• Increasing data rate at > 25Gb/s increases link losses and power
consumption

Possible Solutions
PAM-4 modulation vs NRZ
• Helps maintain loss budget by halving Nyquist frequency
• SNR degradation can be recovered by using FEC
[Courtesy Broadcom, ISSCC 2015]
fN=14GHz
fN=7GHz
1/3
1

PAM-4 SNR and H Opening
Intrinsic H opening = 1.3 [UI]
fNyquist = 1/(4Tbit)
Eye Amplitude = 1/3
Intrinsic H opening = 1 [UI]
fNyquist = 1/(2Tbit)
Eye Amplitude = 1
• Slight increase in horizontal opening
• Noise power is halved, but eye amplitude reduced by 1/3
Delivering high TX amplitude mandatory to preserve high SNR
Tbit 1.3Tbit
56Gb/s, ch. loss is 3dB @ 28GHz

PAM-4 Eye Distortion due to Nonlinearity
• Ratio of Level Mismatch (RLM) quantifies PAM-4 eye distortion
• RLM = 3Vmin/Vppd = 80% (picture above) yields:
o 25% reduction in H opening → H opening advantage lost
o 30% reduction in vertical opening @ 10E-6 with 3mVrms noise
• Standard recommends RLM>92%
Vppd
Vmin
RLM = 80%
PAM-4 TX

PAM-4 Current-Mode Driver
• Theoretical max diff. swing is 4/3(VDD-VOV)
• Linearity limited by tail current sources
• With VDD=1V, typically RLM<85%
• Increasing VDD increases linearity but
reduces efficiency
VDD=1V
VDD=1.4V
VDD=1V VDD=1.4V

PAM-4 Voltage-Mode Drivers
• Robust towards non-linear device on-resistance RT
• With RE/Ron>1/1, RLM is better than 96%
• However, matching constrains max swing to VDD

Proposed Swing-Enhanced PAM-4 TX
• Additional currents (1/3Is,2/3Is) injected in the output node
• With Is=3mA, VDD=1V, output swing is raised to 1.3Vppd
• Compared to increasing VDD to 1.3V, 30% better efficiency
[Joy et al, ISSCC ‘11]

• Driver is transmitting MSB=1 and LSB=1
• Additional current flowing into the load is 𝐼𝐼𝑆𝑆 = 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 + 𝐼𝐼𝐿𝐿𝑆𝑆𝑆𝑆
𝑉𝑉𝐷𝐷𝐷𝐷 + 2𝐼𝐼𝑆𝑆 𝑅𝑅𝐿𝐿
∆𝑉𝑉

𝑉𝑉𝐷𝐷𝐷𝐷
3
+
2𝐼𝐼𝑆𝑆 𝑅𝑅𝐿𝐿
3
• Driver is transmitting MSB=1 and LSB=0
• Additional current flowing into the load is 𝐼𝐼𝑆𝑆/3 = 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 − 𝐼𝐼𝐿𝐿𝑆𝑆𝑆𝑆
∆𝑉𝑉
3

TX Replica Bias for Levels Calibration
• Small headroom across current sources when delivering large swing →
linearity impaired and eye still distorted
• Scaled TX replicas employed for calibration of current sources
𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 − 𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 =
∆𝑉𝑉
6𝑅𝑅𝐿𝐿
𝛼𝛼 𝐼𝐼𝑀𝑀𝑀𝑀𝑀𝑀 + 𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿 =
∆𝑉𝑉
2𝑅𝑅𝐿𝐿
, 𝛼𝛼 < 1

TX Replica Bias for Levels Calibration
Ensures high linearity even with small
headroom across current sources:
• Without cal: RLM=83%
• With cal: RLM=97%
TX
Replica TX

TX Driver with FFE
• Each tap made of 6 slices to implement FFE coefficients
• Multiplexers switch either main tap stream or delayed data to the driver

Serializer, Driver and Output Network

Test Chip
• 10ML CMOS 28nm FDSOI from STMicroelectronics
• Chips encapsulated in flip-chip BGA packages
• Supply Voltage:1V
• Data Rate: 45Gb/s
• Power: 120mW
• Serializer 60mW
• Replica TX 5mW
• Bias 5mW
• Driver 50mW

Measurement Setup
• Channel profile includes PCB trace, connector and cable losses
• At the frequency of 12GHz, loss is 6dB

Output Eyes at 10Gb/s
• Data Rate is 10Gb/s
• FFE disabled
• Swing-enhancing currents improve eye amplitude by 30%
• Output levels calibration loop set (V11, V10, V01, V00) ~ (825mV,
610mV, 390mV, 175mV)
Without Currents With Currents
Amplitude 1Vppd Amplitude 1.3Vppd
diff scale is 85mV/div +10dB attenuator diff scale is 85mV/div +10dB attenuator

Output Eyes at 45Gb/s
• Data Rate is 45Gb/s
• FFE is ON and recovers 6dB at Nyquist
• Swing-enhancing currents improve eye amplitude by 28%
• Output levels calibration loop set (V11, V10, V01, V00) ~ (825mV,
610mV, 390mV, 175mV)
Without Currents With Currents
Amplitude 530mVppd Amplitude 680mVppd
diff scale is 85mV/div +10dB attenuator diff scale is 85mV/div +10dB attenuator

Eye distortion test
• Test proposed by CEI-56G and IEEE 802.3bs emerging standards
• RLM = 3 min(VB-VA,VC-VD,VD-VC)/(VD-VA)
• At 45Gb/s RLM > 0.92 (spec under discussion) for 20 chip samples
VA
VB
VC
VD
16UI
45Gb/s w/o FIR45Gb/s

Summary and comparison
1 Amplitude from picture. Loss recovered by FFE de-embedded.
2 Not including PLL and clock distribution power.
3 Amplitude from picture. Loss recovered by software CTLE de-embedded.
Ref.
Menolfi
ISSCC ‘05
Nazemi
ISSCC ‘15
Chiang
ISSCC ‘14
Kim
ISSCC ‘15
This Work
CMOS Technology 90nm SOI 28nm 65nm 14nm 28 nm FDSOI
Driver Topology CML CML CML SST SST
TX-FFE 4-taps DAC 3-taps No 4-taps
ESD Yes No No Yes Yes
Data-Rate [Gb/s] 25 36 60 40 45
Output Swing Without FFE [Vppd] 0.841 0.8 0.250 0.93
1.3
Vdd [V] 1 1.5 1.2 N/A 1
Power PDC [mW] 102 842 2052 167.52
120
Power Efficiency (Vout
2/2R)/PDC [%] 3.4 3.8 0.15 2.42 7
mw/Gbps 4 2.33 3.4 4.18 2.6
Area [mm2] 0.052 0.05 1.14 0.0279 0.28

Dispersion in Multi-Mode Fibers
• Large fiber core size enables propagation of
several modes
• Different speed leads to different time of
arrival and pulse broadening
• 3 different pulses proposed in IEEE802.3aq
to represent channel response

Electronic Dispersion Compensation
• Flexible DSP-based EDCs proposed for 10GBASE-LRM
• Analog EDC more efficient at Data-Rate > 10Gb/s
• FIR Equalizer is the most critical block:
1. Boost at Nyquist frequency must be tunable from 10 to 25Gb/s
2. Must be low noise and highly linear to sustain high amplitude
levels to preserve SNR
3. Must be area-efficient to be fitted in between two bumps

FIR Equalizer Block Diagram
Td Implementation options:
• Continuous-time LC-base
delay lines, but large area and
low tuning range
• Discrete-Time sampled delay
lines, but clock generation and
distribution issues with
Proposed FIR:
• Compact 7 TAP active tunable
delay
• 10 to 25Gb/s with scalable
power dissipation

• Bandwidth independent from
delay
• Variable delay by tuning the
pole time constant
• Group delay roll-off is not an
issue
Analog Delay: First Order All Pass Filter

• gm1 and the RC load form the programmable lowpass filter
• gm2 and gm3 are used to subtract input signals
• gm2 has maximum input swing (2Vin) and limits linearity
Analog Delay: Circuit Realization

• Maximum now on gm1 limited to Vin
• 1dB C.P ~220mV 0-pk diff (~ +6dB)
• Programmable group delay from 30 to 75ps
• Cell bandwidth from 14GHz to 25GHz
Analog Delay: Circuit Realization

Taps: Programmable Transconductors
• Resolution: 6BIT thermometric
• Very large capacitance (~250fF) on
the summing node
• Transimpedance amplifier used for
summing output currents

Trans-Impedance Amplifier
• Common source topology with
peaking inductors
• Programmable bandwidth, gain
and dissipation
• Low MOS gain (gm/gds~5) impair
performances
• Negative R to cancel output
conductances

Test Chip
• 10ML CMOS 28nm LP from
STMicroelectronics
• Core area: 0.085mm2
• Supply Voltage:1V
• Data rate: 10 to 25Gb/s
• Power: 55 to 90mW
• 5.5 to 9mW Delay
• 10 to 25mW TIA
• 7x1.5mW Multipliers

MMF Link Emulation Setup
Pulse responses spread
over 4-5 symbol periods
• First chip emulates MMF
pulse response
• A second chip (DUT)
performs equalization
• Output connected to a
sampling scope
• Coefficients adapted with
a PC running a MMSE
algorithm

25Gbps Eye Diagram Measurement Results
• Td=3/4 Tbit (30ps)
• H. and V. openings
better than 43% and
57%
• ~100mV vertical
amplitude
• Integrated output noise
<4mVrms

Eye Diagram at 10Gbps
• “Postcursor” channel has a fairly regular low-pass shape
• Can be equalized with a simple high-pass response
• Adjusting Td gives minor performance improvement

Eye Diagram at 10Gbps
• “Split-A” channel has ad in-band notch
• Setting a larger Td shifts the FIR equalizing capability to lower
frequency
• Increasing Td improves H. opening from 48% to 69%

Summary and comparison
* Estimated from chip micrograph
Ref. Tech.
Data
Rate
[Gb/s]
#
Taps
Total
Delay [ps]
Power
[mW]
Power /
(DataRateTotalDelay)
[mW]
Core
Area*
[mm2]
Wu
JSSC 2003
180n
SiGe
10 7 300 40 13.3 1.9
Reynolds
ISSCC 2005
130n
CMOS
10 7 450 325 72.2 3.8
Sewter
JSSC 2006
90n
CMOS
24 - 30 3 70 25 14.8 - 11.9 0.3
Sewter
JSSC 2006
180n
CMOS
30 - 40 3 50 70 46.6 - 35 0.45
Momtaz
JSSC 2010
65n
CMOS
40 7 75 65 21.6 0.75
This Work
28n
CMOS
10 - 25 7 450 - 180 55 - 90 12.2 - 20 0.085

• Evolution of serial links is fast and challenging - and several
technologies still need to converge to achive 400Gb/s operation
• Key research topics are:
• PAM-4 modulation to decrease Nyquist frequency
• How to deliver efficient high TX amplitude with CMOS supply
• How to make a reconfigurable NRZ/PAM-4 TX
• How to get high linearity for TX and RX chain
• How to deal with increased number of DFE samplers
• Analog equalizers: low area, high linearity (key for PAM-4), delay
tunability, LMS-friendly
Conclusions

Serial link interfaces, with emphasis on the challenges of future links

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