Serializer
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This document outlines the design of a serializer circuit. It discusses the fundamentals of serial links and phase locked loops (PLLs), including phase frequency detectors (PFDs), charge pumps, voltage controlled oscillators (VCOs), and dividers. It also covers serializer cells, circuits, and output drivers. Simulation results are presented on PLL parameters like bandwidth and jitter. The design is aimed at serial data transmission rates of 1.6Gbps and above.
Serializer
- 2. OUTLINE Introduction Fundamental of serial links Fundamental of PLL PFD Charge pump VCO Divide Output driver reference
- 3. Introduction why use serializer? In order to achieve higher data transfer rate, the internal bus width has been increased, increasing the bus width, however, costs more pins and enlarge the chip area, so using parallel is not a good method ,that’s why we use the serializer
- 4. Fundamental of serial links
- 5. Fundamental of serial links
- 6. Fundamental of PLL
- 9. Fundamental of PLL PFD
- 11. Fundamental of charge pump
- 12. Simulation of charge pump
- 13. PLL with freq domain
- 17. Simulation of loop filter c1 vctrl gnd 2.28p c2 vctrl net1 36.49p r1 net1 gnd 3.442k
- 19. VCO delay cell
- 21. VCO differential to single end
- 25. Divider
- 26. Divide by 8
- 28. PLL device Bandwidth=5M Kvco=953.8Mhz/v r=4 Phase margin=61.9 Divide by 8 Charge current 150ua c1 vctrl gnd 2.28p c2 vctrl net1 36.49p r1 net1 gnd 3.442k
- 30. The structure of PLL
- 31. serializer
- 32. PRBS
- 36. Serializer cell
- 39. Output driver
- 41. cable r (propagation constant) (attenuation constant) B (phase constant)
- 44. Cycle to cycle jitter 0.010417 the period jitter is : 0.329201 total voltage source power dissipation= 85.7196m watts
- 45. reference Design of CMOS transmitter circuit for 2.5Gps NRZ data transmission 1Gbps serial-link transceiver A 30phase 500MHz pll for3X over-sampling clock Data redcovery