Track h asic prototyping - logtel
- 1. ASIC PROTOYPING ON FPGAZvi Goldenberg Engineer at Intel Senior Lecturer at Logtel May 4, 2011
- 2. Methodology and ChallengesVery few code modificationsCompromise readiness Identifying our customer ! (sw, design, be )Define priorities – what is covered well by verification team ?Should I verify external IP’s ?Good system partition
- 3. Methodology and ChallengesLower system clocks (flow control may be used)Reduce design & synthesis cycle times (use compile point, FPGA editor etc.)
- 5. Simplifying clock tree Use FPGA PLL/MMCM by coregen Instantiate BUFG/BUFGCE/BUFGMUX Delete test mode clocking Use “fix gated clock” carefully Consider bypass clock gaters Refer to “gated clock” warning
- 6. System partitioningTry to locate FF at I/O pads (otherwise, in/out pad delay will reduce dramatically system performance)To save pin count: connect DDR/QDR/serdes between units (Adds latency , check if possible)Usually , phase of 2 FPGA’s must be equal Use PLL carefully to adjust Assign clk_FPGA_1_to_FPGA_2 = sys_clk_FPGA_1 won’t work – why ? Cont…
- 7. System partitioningInter-connection pins : ddr/qdr/serdes may be added between units to save pins Tip : consider GTX serdes connection between 2 FPGA’s . This will enable system expansion.Tip : connect _gc pins from FPGA-1 to FPGA_2 to eliminate parasitic input delay on clock pins.
- 8. Reviewing reportsDo I have slacks ?Are all pins located ?Are all pins got drive level + correct standard ? Did I constraint all clocks ? Answer: Run trce with –uDid I constrained all I/O’s offset ? - SameDo I understand all clock tree ? Search for derived clocks Cont…
- 9. Reviewing reports Do I have local clocks with large skew ? Did the tool understand my timing exceptions ? What is sampling window of main interfaces ?Answers can be found in .twr + .par + .csv reportsCont…
- 10. Reviewing reportsI changed only version number and design stopped working !!! Possible reasons :
- 11. FPGA editor usageInvert input signalDCM /PLL Phase shift adjustment(manual calibration)Add pullup/down to padChange drive level Change init value of FF/RAMChange logic equation of LUTadd probes
- 12. Synthesis warning examplecase 0case 1 …case 9 case 0case 11..case 19Warning : case repetition
- 13. BUG example
- 14. TX RACEInactive state must be ‘1’ (held by pull-up)when oen ↓ (close tx buffer) , input 1 of AND gate is driven to 0 >> data out_pad ==0300 ps later buffer is closed >> data ↑ by pull-up (very slowly)Result : glitch detected by RX logic !!!!!!!!Found in Customer site