Assic 4th Lecture
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This document provides an introduction and overview of Verilog HDL (Hardware Description Language). It discusses how Verilog is used to model event-driven digital systems through simulation. It describes the basic limitations of Verilog in only describing digital systems. It also outlines the different abstraction levels in Verilog including data flow, behavioral, gate, and switch levels. Finally, it covers some main language concepts in Verilog including concurrency, structure, procedural statements, time, user identifiers, comments, value sets, numbers, nets, registers, and vectors.
![8
User Identifiers
Sep 4 2012 Lecture 4
• Formed from {[A-Z], [a-z], [0-9], _, $},
but can’t begin with $ or [0-9]
• myidentifier
• m_y_identifier
• 3my_identifier (X)
• $my_identifier (X)
• _myidentifier$
•Case sensitivity
• myid ≠ Myid](https://image.slidesharecdn.com/veriloglect4-130831044116-phpapp01/85/Assic-4th-Lecture-8-320.jpg)
![18
Vectors
Sep 4 2012
• Represent buses
wire [3:0] busA;
reg [1:4] busB;
reg [1:0] busC;
• Left number is MS bit
• Slice management
Lecture 4
busC[1] = busA[2];
busC[0] = busA[1];
⇔busC = busA[2:1];](https://image.slidesharecdn.com/veriloglect4-130831044116-phpapp01/85/Assic-4th-Lecture-18-320.jpg)
Assic 4th Lecture
- 1. 1 Verilog HDLVerilog HDL ASIC DESIGN USING FPGA BEIT VII KICSIT Sep 4 2012 Lecture 4
- 2. 2 Introduction Sep 4 2012 • Hardware Description Language (HDL) • Verilog was introduced in 1984 by Gateway Design System Corporation, now a part of Cadence Design Systems • Verilog-based synthesis tool introduced by Synopsys in 1987 • Standard: IEEE 1364 in 1995 Lecture 4
- 3. 3 Event Driven Simulation Sep 4 2012 • Verilog is really a language for modeling the event driven systems • Event : change in state • Simulation starts at t = 0 • Processing events generates new events • When all events at time t have been processed simulation time advances to t+1 • Simulation stops when there are no more events in the queue Lecture 4
- 4. 4 Basic Limitation of Verilog Sep 4 2012 • Lecture 4 Description of digital systems only
- 5. 5 Abstraction Levels in Verilog Sep 4 2012 Lecture 4 Data Flow Behavioral Gate Switch
- 6. 6 Main Language Concepts Sep 4 2012 •Concurrency •Structure Lecture 4
- 7. 7 Main Language Concepts Sep 4 2012 Lecture 4 • Procedural Statements • Time
- 8. 8 User Identifiers Sep 4 2012 Lecture 4 • Formed from {[A-Z], [a-z], [0-9], _, $}, but can’t begin with $ or [0-9] • myidentifier • m_y_identifier • 3my_identifier (X) • $my_identifier (X) • _myidentifier$ •Case sensitivity • myid ≠ Myid
- 9. 9 Comments Sep 4 2012 Lecture 4 • // The rest of the line is a comment •/* Multiple lines comment */ • /* Nesting /* comments */ do NOT work */
- 10. 10 Verilog Value Set Sep 4 2012 • 0 represents low logic level or false condition • 1 represents high logic level or true condition • x represents unknown logic level • z represents high impedance logic level Lecture 4
- 11. 11 Numbers in Verilog Sep 4 2012 <size>’<radix> <value> Lecture 4 • 8’h ax = 1010xxxx •12’o 3zx7 = 011zzzxxx111
- 12. 12 Numbers in Verilog Sep 4 2012 • You can insert “_” for readability • 12’b 000_111_010_100 • 12’b 000111010100 • 12’o 07_24 • Bit extension • MS bit = 0, x or z extend this⇒ • 4’b x1 = 4’b xx_x1 • MS bit = 1 zero extension⇒ • 4’b 1x = 4’b 00_1x Lecture 4 Represent the same number
- 13. 13 Nets Sep 4 2012 • Can be thought as hardware wires driven by logic • Equal to z when unconnected • Various types of nets • wire • wand (wired-AND) • wor (wired-OR) • tri (tri-state) Lecture 4
- 14. 14 Nets Sep 4 2012 •In following examples: Y is evaluated, automatically, every time A or B changes Lecture 4
- 15. 15 Nets Sep 4 2012 Lecture 4
- 16. 16 Registers Sep 4 2012 •Variables that store values • Do not represent real hardware but .. • .. real hardware can be implemented with registers Lecture 4
- 17. 17 Registers Sep 4 2012 • Only one type: reg • reg A, C; // declaration // assignments are always done inside a procedure A = 1; C = A; // C gets the logical value 1 A = 0; // C is still 1 C = 0; // C is now 0 • Register values are updated explicitly!! Lecture 4
- 18. 18 Vectors Sep 4 2012 • Represent buses wire [3:0] busA; reg [1:4] busB; reg [1:0] busC; • Left number is MS bit • Slice management Lecture 4 busC[1] = busA[2]; busC[0] = busA[1]; ⇔busC = busA[2:1];
- 19. 19 Vectors Sep 4 2012 • Vector assignment (by position) Lecture 4