A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator

M. Saber, Y. Jitsumatsu & M. T. A. Khan
Signal Processing: An International Journal (SPIJ), Volume (5) : Issue (4) : 2011 142
A Low Power Digital Phase Locked Loop With ROM-Free
Numerically Controlled Oscillator
M. Saber mohsaber@tsubaki.csce.kyushu-u.ac.jp
Department of Informatics
Kyushu University
744 Motooka, Nishi-ku, Fukuoka-shi,89-0395,Japan
Y. Jitsumatsu jitsumatsu@inf.kyushu-u.ac.jp
Department of Informatics
Kyushu University
744 Motooka, Nishi-ku, Fukuoka-shi,89-0395,Japan
M. T. A. Khan tahir@apu-u.ac.jp
Ritsumeikan Asia Pacific University, College of Asia Pacific Studies
1-1 Jumonjibaru, Beppu, Oita, 874-8577, Japan
Abstract
This paper analyzes and designs a second order digital phase-locked loop (DPLL), and presents
low power architecture for DPLL. The proposed architecture reduces the high power consumption
of conventional DPLL, which results from using a read only memory (ROM) in implementation of
the numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, in
which no ROM is used. DPLL is designed and implemented using FPGA, consumes 237 mw,
which means more than 25% saving in power consumption, and works at faster clock frequency
compared to traditional architecture.
Keywords: Digital Phase locked loop (DPLL), Field Programmable Gate Array (FPGA), Software
Defined Radio (SFDR), Read Only Memory (ROM), Spurious Free Dynamic Range (SFDR).
1. INTRODUCTION
Software Defined Radios (SDRs) are leading the integration of digital signal processing (DSP)
and radio frequency (RF) capabilities. This integration allows software to control communications
parameters such as the frequency range, filtering, modulation type, data rates, and frequency
hopping schemes. SDR technology can be seen in wireless devices used for different
applications in military, civil applications, and commercial network. Compared to conventional RF
transceiver technologies, the advantage of SDR is its flexibility. SDR provides the ability to
reconfigure system performance and functions on the fly [1].
In order to take advantage of such digital processing, analog signals must be converted to and
from the digital domain. This is done using analog-to-digital (ADC) and digital-to-analog (DAC)
converters. To take full advantage of digital processing, SDRs keep the signal in digital domain as
much as possible, digitizing and reconstructing as close as possible to the antenna. Despite an
ADC or DAC connected directly to an antenna is a required end goal, there are issues with
selectivity and sensitivity that need an analog front [2].
Phase-locked loop (PLL) is one of the most important building blocks necessary for modern
digital communications, which is used as a frequency synthesizer in RF circuits, or to recover
time and carrier in the baseband digital signal processing. A complete understanding of the
concept of PLL includes many study areas such as RF circuits, digital signal processing, discrete
time control systems, and communication theory [3]. Traditional PLL consists of three parts;
phase frequency detector (PFD), loop filter, and voltage controlled oscillator (VCO).

The traditional analog PLL faces many design problems such as voltage supply noise,
temperature noise, and large area consumed by loop filter components like resistors and
capacitors. On the other hand DPLL, formed of all digital components, provides a high immunity
to supply voltage noise and temperature variation. Moreover, DPLL can be designed by using
hardware description language (HDL) with any standard cell library. Thus, the time for redesign
and check for errors is reduced. Therefore, DPLL provides a good solution to analog PLL design
problems. Unfortunately, DPLL has a critical disadvantage, i.e., high power consumption resulting
from the numerically-controlled oscillator (NCO) [4].
The high power consumption of NCO is the result of using ROM, which contains the sampled
amplitudes of a sinusoidal waveform. As accuracy of the generated signal increases, the size of
ROM increases, which causes high power consumption and reduces the speed of the circuit. We
propose a DPLL architecture in which the traditional NCO is replaced by a circuit which generates
a cosine waveform using a piecewise-linear approximation.
In section 2, PLL operation is explained. The traditional NCO is described in section 3. Section 4
illustrates a modified NCO which can solve the problems of traditional NCO. In section 5
mathematical model of DPLL in both Z-domain and S-domain is illustrated. In section 6 simulation
results. In section 7 hardware implementation of modified NCO and modified DPLL is presented
and in the end some conclusions are given.
2. PHASE LOCKED LOOP
PLL is an important component in many types of communication systems. It works in two different
manners; to synchronize a carrier in frequency and phase or to operate as a synthesizer. The
block diagram of DPLL is shown in Fig. 1. It consists of three main blocks, phase/frequency
detector (PD), loop filter and NCO.
FIGURE 1: Digital phase locked loop in discrete time domain.
The operation of DPLL is as follows: without input signal applied to the system, NCO generates a
signal with a center frequency ( cf ), which is called the free running frequency. The input signal
applied to the system is
i i i iv (n) A sin( n ),= +ω θ (1)
where iA is the amplitude, ωi is the angular frequency, and θi is the phase of the input signal.
Feedback loop mechanism of PLL will force NCO to generate a sinusoidal signal ncov (n)
onco nco ncov (n) A sin( n ),+ω θ= (2)
Phase/ Frequency
Detector
Loop Filter
NCO
Input signal
ω θi i iv (n), (n), (n)
Generated
synchronized signal
±ω θ±ω θd i nco i ncov (n), ,
−ω θ−ω θf i nco i ncov (n), ,ω θncnco o ncov (n), ,

where oA is the amplitude, ncoω is the angular frequency and ncoθ is the phase of the signal
generated by NCO. ncoθ is given by
nco v f
N
i
(n) k v (i),
=−∞
θ = ∑ (3)
where vk is the NCO gain constant and fv (n) is the filter output. If mk denotes the phase detector
(multiplier) gain, then output of the phase detector is
i o
d i i nco nco
i o
i nco i nco i nco i
m
n
m
co
k A A
v (n) sin( n )cos( n )
2
k A A
[sin(( ) n ) sin(( ) n ],
2
= + +
= + + + + − + −
ω θ ω θ
ω ω θ θ ω ω θ θ (4)
The first term in (4) corresponds to high frequency component, and the second term corresponds
to the phase difference between iv (n) and ncov (n) . Loop filter will remove the first term in (4).
If i ncoω = ω , then phase difference can be obtained as
f d i ncov (n) k [sin( )],−θ θ= (5)
where m i o
d
k A A
k
2
= . If i nco( ) 1−θ θ , then fV (n) is approximated by
d i o
f i nco
k A A
v (n) ( ).
2
−θ θ≈ (6)
This difference voltage is applied to the NCO. Thus, the control voltage fv (n) forces the NCO
output frequency to change up or down to reduce the frequency difference between ωnco and ωi .
The equation of the generated frequency of NCO is
nco c f(n) v (n),ω ω= + (7)
where cω is the center frequency of NCO. If the input frequency ωi is close to ωnco , the feedback
manner of PLL causes NCO to synchronize or lock with the incoming signal. Once it is locked, the
generated signal of NCO will synchronize the input signal in phase and frequency.
3. TRADITIONAL NCO
Voltage Controlled Oscillator (VCO), which is used in analog PLL generates a sinusoidal
waveform whose frequency depends on the input voltage. NCO, which is used in DPLL,
generates a digital (sampled) sinusoidal waveform with a fundamental frequency determined by
the digital input value (n-bits). As shown in Fig. 2, NCO consists of ROM, and accumulator. The
output signal of the accumulator is used as address to the ROM. The input signal to the
accumulator consists of the sum of an offset ( cω ) corresponding to the free running frequency,
and fv which is the output of the loop filter [5]. The general equation of generated frequency from
NCO is
f
nco c clkj
v
f ( ) .
2
f= + ω × (8)
where ncof is the generated frequency, cω is the center frequency, fv is an integer value and lies in
the range j 1 j 1
f( 2 v 2 )− −
− ≤ ≤ , j is number of bits or width of the accumulator, which is 16 bits, and
clkf is the clock frequency.

The operation of NCO is as follows: first assuming that the system clock frequency is 50MHz,
j=16 and c 1310ω = , the free running frequency is 1 MHz. Then, as shown in Fig. 3 there are 50
sampling points in one cycle of 1 MHz sinusoidal waveform. NCO generates exactly one cycle of
sinusoidal waveform when the input value ( fv ) is equal to zero. Since the offset value is 1310,
every clock cycle the accumulator accumulates the offset value. Then in 50 cycles the
accumulated value will increase by one. The accumulator output will address this value to the
ROM and extract the cosine amplitudes values stored in it.
When the input value is greater than zero, the accumulation speed becomes higher. Thus in less
than 50 cycles of clock frequency the accumulator increases by 1, this will generate a higher
frequency than 1MHz. When the input value is less than 0, a frequency lower than 1 MHz is
generated. The problem with using a ROM is that, its size increases to achieve a high spectral
purity of the generated waveform. This leads to high power consumption and slow operation of
the system.
FIGURE 2: Numerically controlled oscillator structure.
0 0.5 1 1.5 2
x 10
-6
-1
-0.5
0
0.5
1
Time (s)
Amplitude
50 samples in one cycle
Sampling frequency 50MHz
FIGURE 3: Output waveform of NCO.
Cos
ROM
D
Cos
Waveform
Clock
fv
cω
Q
Delay
Accumulator

3.1 Previous Work
NCO which generates sine or cosine output as shown in Fig. 2 differs mostly in the
implementation of ROM block. This block is the slowest and consumes high power. The problem
of ROM is that, its size grows exponentially with the width of the phase accumulator. Since one
normally desires a large number of bits to achieve fine frequency tuning and high spectral purity,
several techniques have been invented to limit the ROM size while maintaining suitable
performance.
One technique uses the quarter wave symmetry of sine function to reduce the number of saved
samples by 4, in which ROM saves only the amplitudes of first quarter and through additional
hardware the other quarters are generated [6]. Truncating accumulator output (remove number of
most significant bits (MSBs)) is a common method to reduce the size of ROM but this method
introduces spurious harmonics [7].
Different angular decomposition techniques proposed to reduce the ROM size consist of splitting
the ROM into a number of smaller ROMs, each ROM is addressed by a portion of truncated
accumulator output. Generated samples of each ROM are added to form a complete sinusoidal
waveform. In order to introduce more reduction in the ROM size, many techniques have been
proposed to make an initial approximation of the sine amplitude from the value of the phase
angle, and to use the ROM or a combination of ROMs to store correction values [8:11]. Although
these methods reduce the power consumption but they still use ROM which causes a residual of
high power consumption.
Many other techniques have been proposed using piecewise continuous polynomials to
approximate the first quadrant of the sine function. One of them is based on a Taylor-series
expansion [12], a simplified 4th degree polynomial [13] and 4th degree Chebyshev polynomials
[14]. The drawbacks of the above techniques are that they require additional hardware to make
extra computations which increase the complexity of the circuit. The additional hardware
consumes power consumption which supposed to reduce.
4. MODIFIED NCO
4.1 Proposed Architecture
In proposed architecture no ROM is used, to provide fast switching, and less power consumption.
Instead of using a ROM a piecewise linear approximation is used, that is representing the first
quarter of the cosine waveform as linear lines, each line fits a linear equation with slope and bias.
Depending on the symmetry of the cosine waveform (have 4 quarters), it can easily deduce the
other 3 quarters of the cosine waveform from only the first quarter. The first quarter of the cosine
function is divided into eight piecewise linear segments of equal length of the form:
+
π ≤ <+ π≈ i i
i
cos(t)
i 1
t , i=0a t b ,
16
,1,.....7,
16
(9)
where ia is the segment slope and is limited to 4 bits, and ib is the constant or bias limited to 8
bits. Slopes and biases are chosen using the minimum mean square error (MMSE) criterion, that
minimizes the integrated mean square error between the ideal cos(t) and the approximated
cosine functionp (t).
/2
0
2
t
mmse [cos(t) p(t)] dt.
π
=
= −∫ (10)
Fig. 4 shows a comparison between ideal and approximated cosine waveforms. It seems to be the
same except the top and bottom of the waveform, that is because of the linear segments.

0 5 10 15
-1
-0.5
0
0.5
1
Time (s)
Amplitude
cos(t)
p(t)
FIGURE 4: Approximated and Ideal cosine waveforms.
The modified NCO consists of two main components and two negation units. Fig. 5 shows the
block diagram of each component and the corresponding waveform. Accumulator receives the
input signal fv (n) which represents the phase difference between θi and θnco . The accumulator
works as a circular counter. A complete rotation of the accumulator represents one cycle of the
output waveform. The accumulator receives a signal with eight bits-length, and the width of the
accumulator is j=16 bits, so truncation is done to the output signal of the accumulator to be X
signal with L=10 bits’ length. The first two most significant (MSBs) bits of the accumulator are used
to control the operation of NCO. 2nd MSB controls the sign of signal X before performing the
piecewise linear calculation. This negative sign is needed to substitute in the linear function to
generate all quarters of the cosine waveform. Second negation is done at the output stage to
correct position of second and third quarters. This negation is controlled using XOR function
between 1st, and 2nd MSB.
output signal from
accumulator
output signal from
1
st
negation
output signal from linear
function
output signal from NCO
FIGURE 5: Structure of modified NCO.
fv (n)
Clock
1
st
MSB 2
nd
MSB
X
(L bits)
X or -X
ωncocos( n)
Accumulator
(j bits)
2
nd
, and 3
rd
quarters
Negation Piecewise
linear function
Negation
Time Time
Amplitude
Amplitude
Amplitude
TimeTime
Amplitude
X
2L

4.2 Spurious Free Dynamic Range (SFDR)
SFDR is defined as the ratio between the RMS value of the fundamental frequency (maximum
signal component) and the RMS value of the next largest noise or harmonic distortion
component, (which is referred to as a “spurious” or a “spur”) at its output. SFDR is usually
measured in dBc (i.e. with respect to the carrier frequency amplitude) or in dBFS (i.e. with respect
to the ADC's full-scale range). Depending on the test condition, SFDR is observed within a pre-
defined frequency window or from DC up to Nyquist’s frequency of the converter (ADC or DAC).
Fig. 6 shows how SFDR is measured [15]. Since the modified NCO depends on linear
approximation to generate digital samples of cosine waveform, the spectrum of the generated
waveform contains spurs at all the spectrum frequencies, and SFDR is used to measure the
spectral purity of the generated frequencies.
FIGURE 6: SFDR measure.
5. DPLL MATHEMATICAL MODEL
A mathematical model for DPLL is built in z-domain, and s-domain to study the ability of the
system to maintain phase tracking when exited by phase steps, frequency steps, or other
excitation signals. Fig. 7 and Fig. 8 shows mathematical model of the system in both Z-domain
and S-domain respectively.
FIGURE 7: DPLL in Z-domain.
FIGURE 8: DPLL in S-domain.
Frequency
Fundamental
Frequency
Largest
Amplitude(dB)
ncof / 2sf
SFDR
d(z)θ dv (z)
dk
z 1
G(z)
64 (z 1)
+
=
−
0.0625 (z 1)
F(z)
z 0.9375
+
=
−
i
i
v (z)
(z)θ
fv (z)
Phase Detector Loop Filter
NCO
nco(z)θ
dv (s)
dk
1
G(s)
64 s
=
1
F(s)
15.5 s 0.5
=
+
i
i
v (s)
(s)θ
d(s)θ
Phase Detector Loop Filter
NCO
nco(s)θ
fv (s)

The phase transfer function of the system in Z-domain is
1 2
nco d
1 2
i d
(z) k F(z) G(z) 1 z z
.
(z) 1 K F(z) G(z) 1025 1982 z 961 z
− −
− −
+ +
= =
+ −
θ
+θ
(11)
To get the step response of the system a relation between fv (z) and iv (z) is needed. Assuming
the input signal is a unit step of frequency at constant phase
2
f
1 2
i
v (z) F(z) 64 (1 z )
.
v (z) 1 F(z) G(z) 1025 1982 z 961 z
−
− −
−
= =
+ − +
(12)
Using bilinear transformation, the previous equations are obtained in S-domain
nco d
2
i d
(s) k F(s) G(s) 1
(s) 1 k F(s) G(s) 992 s 32 s 1
=
+
θ
θ
=
+ +
(13)
f
2
i
v (s) F(s) 64 s
v (s) 1 G(s) F(s) 992 s 32 s 1
= =
+ + +
(14)
In the test for stability, DPLL is subjected to a test signal representing a unit step of frequency at
constant phase using (14) with sf 50 MHz= [16-17]. As shown in Fig. 9, the system is stable with
overshoots at the transient state.
0 0.5 1 1.5 2 2.5 3 3.5 4
x 10
-6
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
Step Response
Time (sec)
Amplitude
FIGURE 9: DPLL in S-domain.
6. SIMULATION RESULTS
6.1 SFDR of Modified NCO
To measure the SFDR a discrete Fourier transform (DFT) is done for a long repetition period of
the generated signal from modified NCO. Difference between the amplitude of the fundamental
output frequency and the amplitude of the largest spurs in the dynamic range is noted. Fig. 10
shows the output spectrum for input word of value 1317 representing fv (n) , at a clock frequency

of 50 MHz and an accumulator width j=16. The fundamental frequency is approximately 2 MHz
with -30.057 dB, and the spurious appears at 14.46 MHz with -89.925 dB, so SFDR=59.868 dBc.
0 5 10 15 20 25
-90
-80
-70
-60
-50
-40
-30
-20
Frequency (MHz)
Power(dB)
FIGURE 10: SFDR for fundamental frequency of 2 MHz.
6.2 DPLL Synchronization
In this section, we investigate the performances of proposed DPLL’s using computer simulations.
The proposed DPLL has the following parameters:
sf 10 MHz,= mk 1,= vk 1024,= i oA A 1,= = nco 1 MHz,=ω and nco 0.θ =
Two types of simulations are done. In the first one, DPLL receives a signal with phase difference
( i i1 MHz, 4/ω θ= = π ), DPLL response is shown in Fig. 11. In the second case input signal has
both phase difference and frequency difference ( i i1.01 MH /z, 4=ω θ = π ), DPLL response is
shown in Fig.12.
0 1 2 3 4 5
x 10
-5
-0.05
0
0.05
0.1
0.15
0.2
Time (s)
v
F
FIGURE 11: DPLL response in case of phase difference.

0 1 2 3 4 5
x 10
-5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Time (s)
V
F
FIGURE 12: DPLL response in case of phase and frequency difference.
6.3 Proposed DPLL vs. Traditional DPLL
The main objective of this simulation is to compare the performance of the proposed DPLL with
traditional DPLL; to be sure that replacing ROM with linear approximation did not affect the
operation of DPLL. In this simulation both architectures have the same parameters.
sf 10 MHz,= mk 1,= vk 1024,= i oA A 1,= = nco 1 MHz,=ω and nco 0.θ =
An input signal with i 1.02 MHz=ω and i / 2.θ = π is applied to both architectures. Both
responses are shown in Fig.13 which indicates that the performance of the proposed DPLL is not
affected by the modified NCO. i.e. the ability of locking phase or frequency of the input signal is
not affected. This means the proposed DPLL saves power consumption compared to traditional
DPLL without affecting the performance of DPLL.
0 1 2 3 4 5
x 10
-5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Time (s)
a)
V
F
0 1 2 3 4 5
x 10
-5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Time (s)
b)
V
F
FIGURE 13: DPLL response in case of phase and frequency difference
a) Response of traditional DPLL. b) Response of proposed DPLL.
7. HARDWARE IMPLEMENTATION
Hardware implementation of modified NCO, and modified DPLL is done using VHDL code using
Xilinx system generator Simulink tool [18:20]. The architecture of modified NCO is shown in Fig.
14.

FIGURE 14: Modified NCO model
Implementation of linear segments requires slopes and constants. The slopes are chosen using
MMSE as mentioned before and the slopes’ accuracy is limited to a fraction four bits. m1
represents the full truncated output from the accumulator, m2 is half m1, m4 is half m2 (quarter
m1) and m8 is half m4 (eighth m1). The first three MSBs generated from the accumulator are
used to control three multiplexers. The first two multiplexers are forming the slope value, and the
third multiplexer form the constant value. According to the selected signal, the linear equations
are chosen through the multiplexers to form the complete linear equation.
The architecture of modified DPLL is shown in Fig. 15; the architecture uses the modified NCO
instead of traditional NCO. The simulation is done at clock frequency 50 MHz. All signals are
binary signals with different widths. The input signal is a binary signal of 8 bits width representing
a sinusoidal signal at frequency 1 MHz. Fig.16 shows the simulation waveforms as an analog
signal, the input signal (input1) of frequency 1 MHz is multiplied by the modified NCO signal
(input2), and the output signal is passed through the digital filter. The final output shows that
digital implementation agrees with the simulation waveform.
FIGURE 15: Modified DPLL model.

0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 10
-5
-0.5
0
0.5
1
inputsignal
0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 10
-5
-0.5
0
0.5
1
Outputsignal
0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 10
-5
0
0.5
1
Multipliero/p
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 10
-5
-0.2
0
0.2
0.4
Time (s)
Filtero/p
FIGURE 16: VHDL simulations of DPLL.
To recognize how much the modified NCO reduces the power consumption, logic elements and
operation with faster frequency. A comparison between traditional NCO, which uses ROM block
and modified NCO, is done by implementing both architectures on the same FPGA device (Xilinx-
Spartan-3A DSP Xc3d3400a-5fg676). This comparison gives an idea of how much could be the
improvements in power consumption, reduction in the occupied number of logic elements and
faster frequency. As illustrated in Table1, the modified NCO reduces about 40% of total logic
elements used in traditional NCO, and did not use memory bits, which leads to save the power
consumption by about 25% and operation at a faster frequency about 1.8 times the speed of
traditional NCO. Comparison is also done with the traditional DPLL (which uses a traditional
NCO) and modified DPLL (which uses modified NCO). Table 2 shows the result of comparison; it
is clear that the modified DPLL consumed less power, occupied less area and worked faster than
the traditional DPLL, with no degradation in system operation such as locking range.
TABLE 1: Implementation results comparison of NCO.
TABLE 2: Implementation results comparison of DPLL.
Traditional NCO Modified NCO
Slices 108 64
Flip Flops 21 17
Block RAMs 60 0
Look up table (LUT) 210 116
IOBs 24 24
Maximum Frequency 151.461 MHz 284.738 MHZ
Power consumption 0.264 Watt 0.197 Watt
Traditional DPLL Modified DPLL
Slices 162 64
Flip Flops 37 17
Block RAMs 60 0
Look up table (LUT) 299 116
IOBs 24 24
Maximum Frequency 101.241 MHz 205.279 MHZ
Power consumption 0.314 Watt 0.237 Watt

8. CONCLUSION
Second order DPLL architecture has been described, analyzed and implemented to be suitable
for any application. The problem of high power consumption of DPLL has been solved by
replacing the traditional NCO (the main component in DPLL) with a modified ROM. The traditional
NCO uses ROM, which results in high power consumption as well as slower operation. The
proposed architecture reduces power consumption, area consumption and works at a higher
frequency than the traditional one.
9. ACKNOWLEDGEMENT
This research is partially supported by Grant-in-Aid for Scientific Research (B) no.20360174, and
the Aihara Project, the First program from JSPS, initiated by CSTP.
10.REFERENCES
[1] M. Dillinger. K. Madani, N. Alonistioti. Software Defined radio: Architectures, systems, and
functions. John Willey & Sons Inc., 2003.
[2] T. J. Rouphael. RF and Digital Signal Processing For Software-Defined Radio: A Multi
standard Multi-Mode Approch. John Willy & Sons Inc., 2008
[3] R. E. Best. Phase-Locked Loops: Design, Simulation, and Application. 6
th
ed, McGraw-Hill,
2007.
[4] S. Goldman. Phase Locked-Loop Engineering Hand Book of Integrated Circuit. Artech House
Publishers, 2007
[5] B. Goldberg. Digital Frequency Synthesis Demystified: DDS and Fractional-N PLLs. Newnes
,1999.
[6] V.F. Kroupa, Ed. Direct Digital Frequency Synthesizers. IEEE Press,1999.
[7] V.F. Kroupa, V. Cizek, J. Stursa, H. Svandova. “Spurious signals in direct digital frequency
synthesizers due to the phase truncation.” IEEE Transactions on Ultrasonics,
Ferroelectrics, and Frequency Control, vol. 47, no. 5, pp. 1166-1172, September 2000.
[8] H.T. Nicholas III, H. Samueli and B. Kim. “The optimization of direct digital frequency
synthesizer performance in the presence of finite word length effects,” in Proc. of the 42nd
Annual Frequency Control Symposium, 1988, pp. 357-363.
[9] A. Yamagishi, M. Ishikawa, T. Tsukahara, and S. Date. "A 2-V, 2-GHz low-power direct
digital frequency synthesizer chipset for wireless communication." IEEE Journal of Solid-
State Circuits, vol. 33, pp.210-217, February 1998.
[10] A. M. Sodagar, G. R. Lahiji, “Mapping from phase to sine-amplitude in direct digital
frequency synthesizers using parabolic approximation.” in IEEE Transactions on Circuits
and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 1452-1457, December
2000.
[11] J.M.P. Langlois, D. Al-Khalili. “ROM size reduction with low processing cost for direct digital
frequency synthesis,” in Proc. of the IEEE Pacific Rim Conference on Communications,
Computers and Signal Processing, August 2001, pp. 287-290.
[12] L.A. Weaver, R.J. Kerr. “High resolution phase to sine amplitude conversion.” U.S. patent 4
905 177, Feb. 27,1990.

[13] A.M. Sodagar, G.R. Lahiji. “A novel architecture for ROM-less sine-output direct digital
frequency synthesizers by using the 2nd-order parabolic approximation,” in Proc. of the
2000 IEEE/IEA International Frequency Control Symposium and Exhibition, 7-9 June 2000,
pp. 284-289.
[14] K.I. Palomaki, J. Niitylahti. “Direct digital frequency synthesizer architecture based on
Chebyshev approximation,” in Proc. of the 34th Asilomar Conference on Signals, Systems
and Computers, Oct. 29th – Nov. 1st., 2000, pp. 1639-1643.
[15] J. Rudy. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Springer,
2003.
[16] J. G. Proakis, G. Dimitri, Manolakis. Digital Signal Processing. Prentice Hall,1996.
[17] Naresh K. Sinha. Linear Systems. John Wiley & Sons Inc.,1991.
[18] Xilinx Inc. system generator for DSP user guide. Xilinx, 2009.
[19] W.Y. Yang. Matlab/Simulink for Digital Communication. A-Jin, 2009.
[20] P. Chu. FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version. Wiley-Interscience,
2008.

A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator

More Related Content

What's hot (20)

Viewers also liked (10)

Similar to A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator (20)

Recently uploaded (20)

A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator