Dileep Random Access Talk at salishan 2016
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This document summarizes the evolution of integrated circuits and microprocessors from their inception in the late 1950s to recent developments in the multicore era. It discusses how Moore's law drove scaling over the decades, enabling exponential increases in transistor counts. However, Dennard scaling broke down around 2004, necessitating new approaches like multicore designs to continue performance gains within power constraints. Going forward, significant challenges remain to further scaling, suggesting future progress may rely more on heterogeneous architectures and higher parallelism rather than traditional scaling alone.
Dileep Random Access Talk at salishan 2016
- 1. Random Access @ The Salishan Conference 27 April 2016 Dileep Bhandarkar, Ph. D. IEEE Life Fellow
- 2. Disclaimer This presentation is based on personal Experiences over the last 40+ years in industry As a Computer Architect and Is not presented on behalf of current or past employers.
- 3. 1958: Jack Kilby’s Integrated Circuit SSI -> MSI -> LSI -> VLSI -> OMGWLSI
- 4. In < 40 Years of Moore’s Law 4004 8008 8080 8085 8086 286 386 486 Pentium proc Pentium® Pro Pentium® 4 Itanium® 2 • 221M in 2002 • 410M in 2003 0.001 0.01 0.1 1 10 100 1,000 10,000 ’70 ’80 ’90 ’00 ’10 Million Transistors More than 1 Billion Transistors in 2006! Montecito 1.7 Billion Tulsa 1.3 Billion Penryn 410M in 2007 From 2300 to >1Billion Transistors
- 5. Dennard Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/K Doping concentration Na K Voltage V 1/K Current I 1/K Capacitance eA/t 1/K Delay time per circuit VC/I 1/K Power dissipation per circuit VI 1/K2 Power density VI/A 1 Dennard’s 1974 paper summarizes transistor or circuit parameter changes under ideal MOSFET device scaling conditions, where K is the unitless scaling constant. The benefits of scaling : as transistors get smaller, they can switch faster and use less power. Each new generation of process technology was expected to reduce minimum feature size by approximately 0.7x (K ~1.4). A 0.7x reduction in linear features size provided roughly a 2x increase in transistor density. Dennard scaling broke down around 2004 with unscaled interconnect delays and our inability to scale the voltage and the current due to reliability concerns. But our the ability to etch smaller transistors has continued spawning multicore designs.
- 6. THE MULTICORE ERA NEW DEVICE STRUCTURES & MATERIALS ENERGY EFFICIENCY WITH POWER CONSTRAINTS Post Dennard Scaling Moore’s Law continued for 10 more years! Instruction Level Parallelism harder to find Increasing single-stream scalar performance often requires non-linear increase in design complexity, area, and power Vectorization for increasing floating point performance Something New Needed Every Two Process Generations to Keep Moore’s Law Going 22 nm 32 nm 45 nm
- 7. 4 is Better Than 2! And 8 is Even Better! 22 nm Intel Ivy Bridge Xeon E5/E7 had 15 cores in 525 mm2 22 nm Intel Haswell Xeon E5/E7 had 18 cores in 662 mm2 14 nm Intel Broadwell Xeon E5/E7 has 24 cores in 456 mm2 FLOPS per core also doubled with each generation
- 8. 8 © 2013 Qualcomm Technologies, Inc. All Rights Reserved. CPU scaling is reaching diminishing returns Time Single Core Era Uniprocessor scaling • Hitting a limit on: • Clock rate • Instructions per cycle • Becomes energy inefficient Single-Core CPU Multi-Core Era Multiprocessor scaling • Works well for scale out and embarrassingly parallel applications • Memory bandwidth lags core count increase Multi-Core CPU Multi-Core Era What is next? ? Heterogenuous Computing Era New Architectures
- 9. Thoughts about the Future? 14 nm is in production but ramping slower than previous generations – Future Generations will be even harder! Costs per wafer increasing – Capital, more process steps, increased mask costs, EUV cost – Cost per transistor decreasing, but at a slower rate Moore’s Law is slowing down beyond 14 nm – New process generation every 30 months – Economics, Physics, Materials, Power, Lithography – What is the best use for increased transistor density? – Other architectures? – Heterogenuous Processing Engines? Is vectorized floating point sufficient? Can we truly exploit higher levels of parallelism in large “traditional” systems effectively & efficiently?
- 10. Thank You dbhandarkar@outlook.com 5 nm 7 nm 10 nm 65 nm 45 nm 32 nm 22 nm 14 nm