Impact of parameter variations and optimization on dg pnin tunnel fet

International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.3, June 2014
DOI : 10.5121/vlsic.2014.5305 47
IMPACT OF PARAMETER VARIATIONS AND
OPTIMIZATION ON DG-PNIN TUNNEL FET
Priya Jhalani and Manisha Pattanaik
ABV-Indian Institute of Information Technology and Management,
Gwalior, India
ABSTRACT
The downscaling of conventional MOSFETs has come to its fundamental limits. TFETs are very attractive
devices for low power applications because of their low off-current and potential for smaller sub threshold
slope. In this paper, the impact of various parameter variations on the performance of a DG-PNIN Tunnel
field effect transistor is investigated. In this work, variations in gate oxide material, source doping, channel
doping, drain doping, pocket doping and body thickness are studied and all these parameters are optimized
as performance boosters to give better current characteristics parameters. After optimization with all these
performance boosters, the device has shown improved performance with increased on-current and reduced
threshold voltage and the Ion/Ioff ratio is > 106
.
KEYWORDS
Tunnel Field Effect Transistor (TFET), Band to Band Tunneling (BTBT), DG-PIN TFET, DG-PNIN TFET,
Ion/Ioff Ratio
1. INTRODUCTION
Since the invention of transistor at Bell labs, the semiconductor industry has been witnessed a
record growth in terms of revenue and transistor count on a chip with the trend following the well
known Moore’s law [1]. With each generation of scaled technology, the transistor performance
has been improved. But, the aggressive scaling of MOSFET to meet various design constraints
like low power consumption, smaller area, higher speed etc. is approaching to its fundamental
limits [2-3]. To replace conventional MOSFET, new device structures are being investigated
which must be compatible to CMOS circuit architecture and technology. Due to their low sub
threshold swing (SS<60mv/dec), less susceptibility to short channel effects (SCEs), very low
leakage current, Tunnel Field Effect Transistor (TFET) has been considered as an alternative for
low power CMOS applications[4-12].
However the main disadvantage of TFET is, its low on-current. Therefore many TFET
performance enhancing solutions have been proposed to enhance on-current such as 1)
Modification of the TFET architecture (Like Hetero structures [13-15], Strained Silicon [16],
High-k gate dielectric [17-18]), 2) Use of small band gap materials at tunnel junction to reduce
the tunneling height [19-23]), 3) Use of a pocket at source channel tunnel junction to reduce the
tunneling width[24] etc. All these ideas are considered as performance boosters but, all of these
performance boosters are often applied independently. Therefore, in consideration to achieve
better current characteristics of TFET, as many as possible performance boosters should be
applied to the device.
Tunnel FETs are gated reverse biased PIN diodes, where the gate is used to modulate an effective
tunneling barrier height. The injection mechanism of Tunnel FETs is based on band to band
tunneling (BTBT). To switch the device on, the diode is reverse biased and a voltage is applied to

48
the gate. When device is off, there will be a large tunnel barrier between the bands. Hence, charge
carriers will not tunnel from valence band to conduction band and a very small off-current will
flow. When the device is on, the bands are pushed down towards each other and current flows.
In this work, a double gate PNIN Tunnel field effect transistor (DG-PNIN-TFET) device is
designed and the impact of various parameter variations (like gate oxide material, doping, and
body thickness variations) has been investigated. Now based on the variation analyses, the device
parameters are optimized in order to work as performance boosters. After that, all these
performance boosters are applied to the device to get superior current characteristics.
2. DEVICE STRUCTURE AND SIMULATION PARAMETERS
By increasing the doping level of some part of channel region near the source region, electric
field can be increased. This small region is known as pocket and the device is called pocket doped
TFET [24]. In this paper, an n-type pocket layer is used near the p+ heavily doped source region.
The intrinsic region is lightly doped and drain region is n+ heavily doped. This device can be also
termed as PNIN TFET device. Fig.1 shows the basic device structure of double gate PNIN (DG-
PNIN) TFET. In this paper, double gate structure will be used due to better gate control provided
by both gates.
Figure 1. DG-PNIN-TFET Device Structure
The fundamental device parameters used for the device simulations are listed in table 1. All
simulations are performed using SILVACO ATLAS with nonlocal BTBT model, Shockley Read
Hall (SRH) and Fermi Dirac models [25] at room temperature with Vgs=1V.
Table 1. Parameters used in the simulation of the TFET
No. Parameter Value
1 Gate Oxide Thickness (tox) 3nm
2 Silicon Body Thickness (tBody) 15nm
3 Gate Length (Lg) 60nm
4 Gate Work Function 4.0ev
5 Channel Doping (Nchannel) 1017
atoms/cm3
6 Source Doping (p+
) and Drain Doping (n+
) 1020
atoms/cm3
7 Pocket Doping (Npocket) 1019
atoms/cm3
8 Pocket Length (Lpocket) 10nm
9 Gate Source Overlap (Lov) 5nm
A comparison graph of Ids-Vgs characteristics of various TFET topologies like SG-PIN, SG-
PNIN, DG-PIN and DG-PNIN TFET is presented in Fig. 2 and from the graph it can be seen that

49
for PNIN-TFET device, on current is higher than the PIN -TFET device. The impact of double
gate with improved performance can also be seen in the graph. All these devices are simulated
with parameters listed in table 1 and SiO2 layer is used as gate oxide material.
Figure 2. Comparison of Ids-Vgs characteristics of DG-PNIN, DG-PIN, SG-PNIN and SG-PIN
TFET
3. IMPACT OF PARAMETER VARIATIONS
In this section the impact of various parameter variations on DG-PNIN TFET device is studied
and investigated.
3.1. Gate Oxide Material Variations
Effect of gate oxide material on the performance of DG-PNIN TFET is evaluated and the
materials that have been analyzed are SiO2, Si3N4 and HfO2 whose dielectric constant is 3.9, 7and
25 respectively. Fig.3 shows the Id-Vgs characteristics of the PNIN TFET device with different
gate oxide material. From the figure, it is clear that by using high-k gate oxide dielectric layer (i.e.
HfO2) the on-current is increased due to better gate coupling provided by the high-k dielectric.
With high-k dielectric, the Off-current is also increased but it is acceptable because it’s still very
low. So for all the further simulations HfO2 layer will be used as a gate oxide for better
performance.
3.2. Doping Variations
The doping levels of the Tunnel FET device must be carefully optimized in order to maximize
on current and Ion/Ioff ratio and minimize off-current. In DG-PNIN TFET, there are four types
of doping level and these are source, drain, intrinsic and pocket doping levels. When doping level
increases, the band gap reduces. With the reduction in band gap, current characteristics
parameters of the device will improve. Here, by using this fact, these doping levels are studied
and investigated.

50
Figure 3. Ids-Vgs characteristics of DG-PNIN TFET with varying gate oxide materials
3.2.1 Source Doping Variations
In TFET tunneling takes place between source and intrinsic region therefore, source doping (Ns)
has a great effect on that tunneling phenomenon. The PNIN TFET device is simulated at various
source doping levels such as 1*1020
, 1.5*1020
and 2*1020
. Fig. 4 shows, the comparison graph of
Id-Vgs characteristics of DG-PNIN TFET device with varying source doping. As source doping
increases, on-current also increases due to electric field enhancement at tunneling junction. Thus,
the highest feasible source doping is preferable for DG-PNIN TFET optimization.
Figure 4. Ids-Vgs characteristics of DG-PNIN TFET with varying Source doping

51
3.2.2 Drain Doping Variations
Now the next doping level is drain doping level and this doping level is important for another
reason. The effect of drain doping level on a device characteristic can be seen when it is operating
in negative region. Fig. 5 shows, the comparative graph of current characteristic of DG-PNIN
TFET device with varying drain doping. When the device is in positive region there is no effect
of drain doping variations on the current characteristic but, for negative region it shows the
ambipolar characteristics which are undesirable for the circuit designers. The DG-PNIN TFET
shows ambipolar behavior when drain doping level is equal to the source doping level. So for the
device optimization, a low drain doping is preferable but it should not be too low that the contact
formation becomes difficult.
Figure 5. Ids-Vgs characteristics of DG-PNIN TFET with varying Drain doping
3.2.3 Intrinsic Doping Variations
Now the next doping level is intrinsic region doping level. This doping level has a little effect on
Tunnel FET characteristics until the doping level becomes high. Fig. 6 shows the comparative
graph of current characteristic of device with varying intrinsic doping from 1015
atoms/cm3
to 1019
atoms/cm3
. When intrinsic doping is less than 1018
atoms/cm3
it has a little effect on the current
characteristics of DG-PNIN TFET device and exact concentration and type is not important
because at low concentration it does not affect the gates ability to control the band to band
tunneling at tunneling junction. But when the intrinsic doping level increases, off-current also
increases rapidly because at higher doping level intrinsic region is no more intrinsic. Thus a
lightly doped intrinsic region is preferable for DG-PNIN TFET optimization.
3.2.4 Pocket Doping Variations
Now the next and the last doping level is pocket doping level which has to be considered for
TFET optimization. In PNIN TFET device, an n-type layer is used as pocket in channel region
near the source region to increase Ion/Ioff ratio. So this pocket doping level also has a great effect
on the device characteristics. Here, the DG-PNIN TFET device is simulated at various pocket
doping levels and the comparative current characteristics of the device is shown in Fig. 7. When
the pocket doping increases or becomes equal to source doping then it gives a large amount of
off-current due to great amount of charge carrier available at the channel region which will tunnel

52
from channel to source in off-state resulting off-current. And if the pocket doping is made too low
then the advantage of using pocket cannot be utilized. So balanced pocket doping level is
preferable for the DG-PNIN TFET optimization.
Figure 6. Ids-Vgs characteristics of DG-PNIN TFET with varying Intrinsic doping
Figure 7. Ids-Vgs characteristics of DG-PNIN TFET with varying Pocket doping
3.3. Body Thickness Variations
Another important parameter is body thickness of Silicon and TFET device is very much
sensitive to this thickness. Fig. 8 shows, the comparison of current characteristics of DG-PNIN
TFET device with varying body thickness. For larger body TFET device, the tunneling
probability reduces thus on-current also reduces. Therefore, thin body TFET structures are needed
for better performance. As body thickness becomes smaller than 10nm the on-current decreases in
a large amount due to decreased tunneling area for the current flow of the device. So for DG-

53
PNIN TFET optimization, thin body structures are beneficial but it must stay above some critical
thickness so that on-current will not degrade.
Figure 8. Ids-Vgs characteristics of DG-PNIN TFET with varying Body thickness
4. DG-PNIN TFET OPTIMIZATION
In this section the optimization of fundamental DG-PNIN TFET parameters has been done based
on the parameter variation analysis. The main analysis that has been done is, the on-current
increases with the high-k gate oxide layer due to increased dielectric permittivity, At source
channel tunnel junction with increased source doping on-current also increases due to band
bending in between conduction and valance bands, to suppress ambipolar behavior drain doping
should be low, at high intrinsic doping off-current increases so low intrinsic doping is desirable,
pocket doping should be moderate because at high pocket doping off-current increases and low
doping leads to on-current decrement, Finally a thin body TFET structure is needed for current
improvement but it must be above 10nm because below 10nm the performance degrades badly
due to small tunneling area.
The Tunnel FETs have a low off-current and the potential for a small SS, but they suffer from a
lower on-current than conventional MOSFETs. Many solutions and topologies have been
proposed, but performance boosters are often suggested independently, like just adding a high-k
dielectric, or just using a thin body or just decreasing the band gap at the tunnel junction etc.
These techniques, though they increase on-current and reduce sub threshold swing, only have
limited power to improve device characteristics. In order to achieve superior characteristics for
Tunnel FETs, it is essential to apply as many boosters as possible to the same device, so that the
improvements in device performance are progressive. Then with the fully optimized device,
parameter fluctuations can be investigated in great detail.
With Wentzel-Kramer-Brillouin (WKB) approximation and taking the tunnel barrier as a
triangularly shaped potential barrier the band-to-band tunneling transmission is given by equation
1.

54
In this equation Eg represents the band-gap of the material, m* is the effective mass of the
tunneling particle (material dependent), is the energy range over which tunneling takes place,
is the screening length and it depends on (permittivity of silicon), tox (oxide thickness), tSi
(Silicon body thickness) and (permittivity of gate oxide layer). To get higher current, tunneling
probability must be higher.
There are three main parameters that can help to increase T(E) of TFET device. These
parameters are m*, Eg and . Where m* and Eg are material dependent and by using small band
gap and smaller mass materials the tunneling probability can increase, is the device dependent
parameter. It depends on dielectric layer thickness, body thickness etc. and by optimizing these
parameters, can also be optimized and tunneling probability will increase. That is why m*, Eg
and are considered as performance boosters for TFET. With the help of these performance
boosters, TFET performance can be boosted to meet its target parameters, that are high on-current
(in the range of hundreds of mA), sub threshold slope (SS) less than 60mv/dec and Ion/Ioff ratio
greater than 10
6
. By achieving these target parameters, TFET can give the performance
comparable to CMOS in future technology. Based on the above all parameter variations analysis,
these parameters are optimized in such a manner that device current characteristics parameters
improves. The optimized parameters of the TFET device are listed in table 2. The column 2 of the
table 2 describes the parameter on which optimization has been performed and column 3 and 4
describes the value of these parameters before and after optimization.
. Table 2. DG-PNIN TFET parameters before and after optimization
No. Parameter Before Optimization After Optimization
1 Gate Oxide Material SiO2 HfO2
2 Source Doping (Ns) 1020
atoms/cm3
2*1020
atoms/cm3
3 Drain Doping (Nd) 1020
atoms/cm3
1019
atoms/cm3
4 Channel Doping (Nchannel) 1017
atoms/cm3
1015
atoms/cm3
5 Pocket Doping (Npocket) 1019
atoms/cm3
5*1018
atoms/cm3
6 Body Thickness(Tbody) 15nm 10nm
Now the DG-PNIN TFET device (Fig.1) is simulated in SILVACO ATLAS with all optimized
parameters with tox=3nm, Lg=60nm with nonlocal band to band tunneling (BTBT), Shockley
Read Hall (SRH) and Fermi Dirac models at room temperature. Fig. 9 shows the comparative
graph of current characteristics of the device with and without parameter optimization. From the
figure it is clear, that due to heavy source doping, lesser body thickness and due to high-k
dielectric layer the on-current is increased. Because, as source doing increases the electric field
increases at tunnel junction and because of that, band bending occurs between valence and
conduction bands. As intrinsic doping is reduced, so there will be lesser electric field in reverse
direction so, off-current is still low and in acceptable range.
A comparison of current characteristics parameters for before and after optimization has been
done in table 3. By applying all optimized parameters together the device performance improves
with on-current enhancement from 0.8µA to 45µA. Its off-current also increases slightly but still
very low in pA and lies within the acceptable range. The threshold voltage (Vth) for optimized
device is 0.39V calculated by constant current method. The Ion/Ioff ratio is greater than 106
which
is good.

55
Figure 9. Comparison of Ids-Vgs characteristics of DG-PNIN-TFET before and after optimization
Table 3. DG-PNIN TFET current characteristics parameters before and after optimization
Ion Ioff Ion/Ioff Vth
Before Optimization 0.8µA 6pA 1.33*105
0.71V
After Optimization 45 µA 10pA 4.5*106
0.39V
5. CONCLUSIONS
A DG-PNIN Tunnel field effect transistor is designed and investigated with different parameter
variations. The main findings are:- (1) By using HfO2 as dielectric layer material instead of SiO2
dielectric layer material, the on-current increases due to better gate coupling provided by high-k
dielectric material (i.e. HfO2 ). (2) To improve the current characteristics, a high source doping
is beneficial to increase tunneling between source and channel regions by increasing electric
fields, a low drain doping is desirable to suppress the ambipolar behavior in negative regions and
a lightly doped intrinsic region (below 1018
atoms/cm3
) is desirable to decrease off-current in off-
state. (3) Smaller body thickness is required to increase tunneling probability by optimizing the
tunneling area of the device but, it must not be below from the critical thickness of body
(i.e. 10nm). Based on these analyses, an optimization has been performed on PNIN TFET device
parameters for on-current improvement. So resulting optimized device had a double gate, a high-k
dielectric layer, a high source doping, a low drain doping, a lightly doped intrinsic region, smaller
body thickness that should be above of its critical thickness. With these optimized parameters the
on-current increases from 0.8µA to 45µA with high Ion / Ioff ratio (>106
). But the on-current is still
in µA range and the further enhancement of on-current is required without any compromise in
off-current to meet the TFET target parameters.

56
ACKNOWLEDGEMENTS
The authors would like to thank to VLSI Design Lab., ABV-Indian Institute of Information
Technology and management, Gwalior, for providing the computational resources.
REFERENCES
[1] G.E. Moore, “Cramming more components on to the integrated circuits”, Electronics, vol. 38, no. 8,
pp. 114-117, Apr. 1965.
[2] Seabaugh, Alan C.; Qin Zhang, “Low-Voltage Tunnel Transistors for Beyond CMOS Logic”,
Proceedings of the IEEE, vol.98, no.12, pp. 2095-2110, Dec. 2010.
[3] J. D. Meindehl, Q. Chen, J. A. Davis, “Limits of Silicon Nano electronics for Terascale
Integration”,Science, vol. 293, pp. 2044-2049, 2001.
[4] Pan, A.; Songtao Chen; Chi On Chui, “Electrostatic Modeling and Insights Regarding Multigate
Lateral Tunneling Transistors”, Electron Devices, IEEE Transactions on, vol.60, no.9, pp. 2712-2720,
Sept. 2013.
[5] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Drain-conductance optimization in nanowire
TFETs by means of a physics-based analytical model”, Solid-State Electron., vol. 84, pp. 96-102, Jun.
2013.
[6] A. Mallik, and A. Chattopadhyay, “The impact of fringing field on the device performance of a p-
channel tunnel field-effect transistor with a high-k gate dielectric”, IEEE Transactions on Electron
Devices, Vol. 59, No. 2, pp. 277-282, 2012.
[7] A. M. Ionescu, and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches”,
Nature, Vol. 479, pp. 329-337, 2011.
[8] D. Leonelli, A. Vandooren, R. Rooyackers, S. De Gendt, M. M. Heyns, and G. Groeseneken, “Drive
current enhancement in p-tunnel FETs by optimization of the process conditions,” Solid-State
Electron., vol. 65, no.6, pp. 28-32, Nov. 2011.
[9] A. Chattopadhyay, and A. Mallik, “Impact of a spacer dielectric and a gate overlap/underlap on the
device performance of a tunnel field-effect transistor”, IEEE Transactions on Electron Devices, Vol.
58, No. 3, pp. 677-683, 2011.
[10] W. Lee, and W. Choi, “Influence of inversion layer on tunneling field-effect transistors”, IEEE
Electron Device Lett., Vol. 32, No. 9,pp. 1191-1193, 2011.
[11] W. Y. Choi, B.-G. Park, J. D. Lee, and T.-J. K. Liu, “Tunneling field-effect transistors (TFETs) with
sub threshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Lett., vol. 28, no. 8, pp. 743–
745, Aug. 2007.
[12] Brinda Bhowmick, Srimanta Baishya,” An Analytical Model for Fringing Capacitance in Double gate
Hetero Tunnel FET and Analysis of effect of Traps and Oxide charges on Fringing Capacitance”, in
International Journal of VLSI design & Communication Systems (VLSICS), vol. 3, no.1, Feb. 2012.
[13] A. S. Verhulst, W. G. Vandenberghe, K. Maex, S. De Gendt, M. M. Heyns, and G. Groeseneken,”
Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates,” IEEE Electron
Device Lett., vol. 29, no. 12, pp. 1398–1401, Dec. 2008.
[14] L. Wang, E. Yu, Y. Taur and P. Asbeck, “Design of tunneling fieldeffect transistors based on
staggered hetojunctions for ultralowpower applications,” IEEE Electron Device Lett., vol. 31, no. 5,
pp- 431-433, May 2010.
[15] O. M. Nayfeh, C. N. Chleirigh, J. Hennessy, L. Gomez, J. L. Hoyt and D. A. Antoniadis, “Design of
Tunneling Field-Effect Transisitors Using Strained-Silicon/Strained-Germanium Type-II Staggered
Heterojunctions,” IEEE Electron Device Lett., vol. 29, no. 9, pp- 1074-1077, Sept. 2008.
[16] K. Boucart, W. Riess, and A. M. Ionescu, “Lateral strain profile as key technology booster for all-
silicon Tunnel FETs,” IEEE Electron Device Lett.,vol.30,no. 6, pp. 656-658, Jun.2009.
[17] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-κ gate dielectric,” IEEE
Trans.Electron Devices, vol. 54, no. 7, pp. 1725–1733, Jul. 2007.
[18] M. Schlosser, K. K. Bhuwalka, M. Sauter, T. Zilbauer, T. Sulima, and I. Eisele, “Fringing-induced
drain current improvement in the tunnel fieldeffect transistor with high-κ gate dielectrics,” IEEE
Trans. Electron Devices, vol. 56, no. 1, pp. 100–108, Jan. 2009.
[19] Beneventi, G.B.; Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G., “Dual-Metal-Gate InAs Tunnel
FET With Enhanced Turn-On Steepness and High On-Current,” Electron Devices, IEEE Transactions
on, vol.61, no.3, pp. 776-784, March 2014.

57
[20] A. Dey, B. Borg, B. Ganjipour, M. Ek, K. Dick, E. Lind, P. Nilsson, C. Thelander, and L.
Wernersson, “High current density InAsSb/GaSb tunnel field effect transistors,” in Device Research
Conference (DRC), 70th Annual, pp. 205-206, 18-20 June 2012.
[21] Moselund, K. E.; Schmid, H.; Bessire, C.; Bjork, M.T.; Ghoneim, H.; Riel, H., “InAs-.Si Nanowire
Heterojunction Tunnel FETs,” Electron Device Letters, IEEE, vol.33, no.10, pp. 1453-1455, Oct.
2012.
[22] Guangle Zhou; Li, R.; Vasen, T.; Qi, M.; Chae, S.; Lu, Y.; Zhang, Q.; Zhu, H.; Kuo, J.-M.; Kosel, T.;
Wistey, M.; Fay, P.; Seabaugh, A.; Huili Xing, “Novel gate-recessed vertical InAs/GaSb TFETs with
record high ION of 180 µA/µAm at VDS = 0.5 V,” Electron Devices Meeting (IEDM), IEEE
International , pp.32.6.1-32.6.4, 10-13 Dec. 2012.
[23] Zhao, H.; Chen, Y.; Wang, Y.; Zhou, F.; Xue, F.; Lee, J., “InGaAs Tunneling Field-Effect-Transistors
With Atomic-Layer-Deposited Gate Oxides,” Electron Devices, IEEE Transactions on, vol.58, no.9,
pp. 2990-2995, Sept. 2011.
[24] Ritesh Jhaveri, Venkatagirish Nagavarapu,Jason C. S. Woo, “Effect of Pocket Doping and Annealing
Schemes on the source -Pocket Tunnel Field-Effect Transistor” in IEEE transaction on Electron
Device. Vol.58, no. 1,pp. 80-86, Jan 2011.
[25] Atlas User manual, Silvaco Int., Santa Clara CA, 2013.

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